1 /*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mystery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
84
85 #include <linux/module.h>
86 #include <linux/sched.h>
87 #include <linux/types.h>
88 #include <linux/errno.h>
89 #include <linux/list.h>
90 #include <linux/ioport.h>
91 #include <linux/pci.h>
92 #include <linux/kernel.h>
93 #include <linux/mm.h>
94 #include <linux/slab.h>
95
96 #include <asm/system.h>
97 #include <asm/cache.h>
98 #include <asm/byteorder.h>
99 #include <asm/uaccess.h>
100 #include <asm/io.h>
101 #include <asm/irq.h>
102
103 #include <linux/init.h>
104 #include <linux/interrupt.h>
105 #include <linux/string.h>
106
107 #include <linux/if_arp.h>
108 #include <linux/netdevice.h>
109 #include <linux/skbuff.h>
110 #include <linux/delay.h>
111 #include <linux/hdlc.h>
112 #include <linux/mutex.h>
113
114 /* Version */
115 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
116 static int debug;
117 static int quartz;
118
119 #ifdef CONFIG_DSCC4_PCI_RST
120 static DEFINE_MUTEX(dscc4_mutex);
121 static u32 dscc4_pci_config_store[16];
122 #endif
123
124 #define DRV_NAME "dscc4"
125
126 #undef DSCC4_POLLING
127
128 /* Module parameters */
129
130 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
131 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controller");
132 MODULE_LICENSE("GPL");
133 module_param(debug, int, 0);
134 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
135 module_param(quartz, int, 0);
136 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
137
138 /* Structures */
139
140 struct thingie {
141 int define;
142 u32 bits;
143 };
144
145 struct TxFD {
146 __le32 state;
147 __le32 next;
148 __le32 data;
149 __le32 complete;
150 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
151 /* FWIW, datasheet calls that "dummy" and says that card
152 * never looks at it; neither does the driver */
153 };
154
155 struct RxFD {
156 __le32 state1;
157 __le32 next;
158 __le32 data;
159 __le32 state2;
160 __le32 end;
161 };
162
163 #define DUMMY_SKB_SIZE 64
164 #define TX_LOW 8
165 #define TX_RING_SIZE 32
166 #define RX_RING_SIZE 32
167 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
168 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
169 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
170 #define TX_TIMEOUT (HZ/10)
171 #define DSCC4_HZ_MAX 33000000
172 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
173 #define dev_per_card 4
174 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
175
176 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
177 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
178
179 /*
180 * Given the operating range of Linux HDLC, the 2 defines below could be
181 * made simpler. However they are a fine reminder for the limitations of
182 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
183 */
184 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
185 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
186 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
187 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
188
189 struct dscc4_pci_priv {
190 __le32 *iqcfg;
191 int cfg_cur;
192 spinlock_t lock;
193 struct pci_dev *pdev;
194
195 struct dscc4_dev_priv *root;
196 dma_addr_t iqcfg_dma;
197 u32 xtal_hz;
198 };
199
200 struct dscc4_dev_priv {
201 struct sk_buff *rx_skbuff[RX_RING_SIZE];
202 struct sk_buff *tx_skbuff[TX_RING_SIZE];
203
204 struct RxFD *rx_fd;
205 struct TxFD *tx_fd;
206 __le32 *iqrx;
207 __le32 *iqtx;
208
209 /* FIXME: check all the volatile are required */
210 volatile u32 tx_current;
211 u32 rx_current;
212 u32 iqtx_current;
213 u32 iqrx_current;
214
215 volatile u32 tx_dirty;
216 volatile u32 ltda;
217 u32 rx_dirty;
218 u32 lrda;
219
220 dma_addr_t tx_fd_dma;
221 dma_addr_t rx_fd_dma;
222 dma_addr_t iqtx_dma;
223 dma_addr_t iqrx_dma;
224
225 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
226
227 struct timer_list timer;
228
229 struct dscc4_pci_priv *pci_priv;
230 spinlock_t lock;
231
232 int dev_id;
233 volatile u32 flags;
234 u32 timer_help;
235
236 unsigned short encoding;
237 unsigned short parity;
238 struct net_device *dev;
239 sync_serial_settings settings;
240 void __iomem *base_addr;
241 u32 __pad __attribute__ ((aligned (4)));
242 };
243
244 /* GLOBAL registers definitions */
245 #define GCMDR 0x00
246 #define GSTAR 0x04
247 #define GMODE 0x08
248 #define IQLENR0 0x0C
249 #define IQLENR1 0x10
250 #define IQRX0 0x14
251 #define IQTX0 0x24
252 #define IQCFG 0x3c
253 #define FIFOCR1 0x44
254 #define FIFOCR2 0x48
255 #define FIFOCR3 0x4c
256 #define FIFOCR4 0x34
257 #define CH0CFG 0x50
258 #define CH0BRDA 0x54
259 #define CH0BTDA 0x58
260 #define CH0FRDA 0x98
261 #define CH0FTDA 0xb0
262 #define CH0LRDA 0xc8
263 #define CH0LTDA 0xe0
264
265 /* SCC registers definitions */
266 #define SCC_START 0x0100
267 #define SCC_OFFSET 0x80
268 #define CMDR 0x00
269 #define STAR 0x04
270 #define CCR0 0x08
271 #define CCR1 0x0c
272 #define CCR2 0x10
273 #define BRR 0x2C
274 #define RLCR 0x40
275 #define IMR 0x54
276 #define ISR 0x58
277
278 #define GPDIR 0x0400
279 #define GPDATA 0x0404
280 #define GPIM 0x0408
281
282 /* Bit masks */
283 #define EncodingMask 0x00700000
284 #define CrcMask 0x00000003
285
286 #define IntRxScc0 0x10000000
287 #define IntTxScc0 0x01000000
288
289 #define TxPollCmd 0x00000400
290 #define RxActivate 0x08000000
291 #define MTFi 0x04000000
292 #define Rdr 0x00400000
293 #define Rdt 0x00200000
294 #define Idr 0x00100000
295 #define Idt 0x00080000
296 #define TxSccRes 0x01000000
297 #define RxSccRes 0x00010000
298 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
299 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
300
301 #define Ccr0ClockMask 0x0000003f
302 #define Ccr1LoopMask 0x00000200
303 #define IsrMask 0x000fffff
304 #define BrrExpMask 0x00000f00
305 #define BrrMultMask 0x0000003f
306 #define EncodingMask 0x00700000
307 #define Hold cpu_to_le32(0x40000000)
308 #define SccBusy 0x10000000
309 #define PowerUp 0x80000000
310 #define Vis 0x00001000
311 #define FrameOk (FrameVfr | FrameCrc)
312 #define FrameVfr 0x80
313 #define FrameRdo 0x40
314 #define FrameCrc 0x20
315 #define FrameRab 0x10
316 #define FrameAborted cpu_to_le32(0x00000200)
317 #define FrameEnd cpu_to_le32(0x80000000)
318 #define DataComplete cpu_to_le32(0x40000000)
319 #define LengthCheck 0x00008000
320 #define SccEvt 0x02000000
321 #define NoAck 0x00000200
322 #define Action 0x00000001
323 #define HiDesc cpu_to_le32(0x20000000)
324
325 /* SCC events */
326 #define RxEvt 0xf0000000
327 #define TxEvt 0x0f000000
328 #define Alls 0x00040000
329 #define Xdu 0x00010000
330 #define Cts 0x00004000
331 #define Xmr 0x00002000
332 #define Xpr 0x00001000
333 #define Rdo 0x00000080
334 #define Rfs 0x00000040
335 #define Cd 0x00000004
336 #define Rfo 0x00000002
337 #define Flex 0x00000001
338
339 /* DMA core events */
340 #define Cfg 0x00200000
341 #define Hi 0x00040000
342 #define Fi 0x00020000
343 #define Err 0x00010000
344 #define Arf 0x00000002
345 #define ArAck 0x00000001
346
347 /* State flags */
348 #define Ready 0x00000000
349 #define NeedIDR 0x00000001
350 #define NeedIDT 0x00000002
351 #define RdoSet 0x00000004
352 #define FakeReset 0x00000008
353
354 /* Don't mask RDO. Ever. */
355 #ifdef DSCC4_POLLING
356 #define EventsMask 0xfffeef7f
357 #else
358 #define EventsMask 0xfffa8f7a
359 #endif
360
361 /* Functions prototypes */
362 static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
363 static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
364 static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
365 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
366 static int dscc4_open(struct net_device *);
367 static netdev_tx_t dscc4_start_xmit(struct sk_buff *,
368 struct net_device *);
369 static int dscc4_close(struct net_device *);
370 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
371 static int dscc4_init_ring(struct net_device *);
372 static void dscc4_release_ring(struct dscc4_dev_priv *);
373 static void dscc4_timer(unsigned long);
374 static void dscc4_tx_timeout(struct net_device *);
375 static irqreturn_t dscc4_irq(int irq, void *dev_id);
376 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
377 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
378 #ifdef DSCC4_POLLING
379 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
380 #endif
381
dscc4_priv(struct net_device * dev)382 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
383 {
384 return dev_to_hdlc(dev)->priv;
385 }
386
dscc4_to_dev(struct dscc4_dev_priv * p)387 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
388 {
389 return p->dev;
390 }
391
scc_patchl(u32 mask,u32 value,struct dscc4_dev_priv * dpriv,struct net_device * dev,int offset)392 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
393 struct net_device *dev, int offset)
394 {
395 u32 state;
396
397 /* Cf scc_writel for concern regarding thread-safety */
398 state = dpriv->scc_regs[offset >> 2];
399 state &= ~mask;
400 state |= value;
401 dpriv->scc_regs[offset >> 2] = state;
402 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
403 }
404
scc_writel(u32 bits,struct dscc4_dev_priv * dpriv,struct net_device * dev,int offset)405 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
406 struct net_device *dev, int offset)
407 {
408 /*
409 * Thread-UNsafe.
410 * As of 2002/02/16, there are no thread racing for access.
411 */
412 dpriv->scc_regs[offset >> 2] = bits;
413 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
414 }
415
scc_readl(struct dscc4_dev_priv * dpriv,int offset)416 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
417 {
418 return dpriv->scc_regs[offset >> 2];
419 }
420
scc_readl_star(struct dscc4_dev_priv * dpriv,struct net_device * dev)421 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
422 {
423 /* Cf errata DS5 p.4 */
424 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
425 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
426 }
427
dscc4_do_tx(struct dscc4_dev_priv * dpriv,struct net_device * dev)428 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
429 struct net_device *dev)
430 {
431 dpriv->ltda = dpriv->tx_fd_dma +
432 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
433 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
434 /* Flush posted writes *NOW* */
435 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
436 }
437
dscc4_rx_update(struct dscc4_dev_priv * dpriv,struct net_device * dev)438 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
439 struct net_device *dev)
440 {
441 dpriv->lrda = dpriv->rx_fd_dma +
442 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
443 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
444 }
445
dscc4_tx_done(struct dscc4_dev_priv * dpriv)446 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
447 {
448 return dpriv->tx_current == dpriv->tx_dirty;
449 }
450
dscc4_tx_quiescent(struct dscc4_dev_priv * dpriv,struct net_device * dev)451 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
452 struct net_device *dev)
453 {
454 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
455 }
456
state_check(u32 state,struct dscc4_dev_priv * dpriv,struct net_device * dev,const char * msg)457 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
458 struct net_device *dev, const char *msg)
459 {
460 int ret = 0;
461
462 if (debug > 1) {
463 if (SOURCE_ID(state) != dpriv->dev_id) {
464 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
465 dev->name, msg, SOURCE_ID(state), state );
466 ret = -1;
467 }
468 if (state & 0x0df80c00) {
469 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
470 dev->name, msg, state);
471 ret = -1;
472 }
473 }
474 return ret;
475 }
476
dscc4_tx_print(struct net_device * dev,struct dscc4_dev_priv * dpriv,char * msg)477 static void dscc4_tx_print(struct net_device *dev,
478 struct dscc4_dev_priv *dpriv,
479 char *msg)
480 {
481 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
482 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
483 }
484
dscc4_release_ring(struct dscc4_dev_priv * dpriv)485 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
486 {
487 struct pci_dev *pdev = dpriv->pci_priv->pdev;
488 struct TxFD *tx_fd = dpriv->tx_fd;
489 struct RxFD *rx_fd = dpriv->rx_fd;
490 struct sk_buff **skbuff;
491 int i;
492
493 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
494 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
495
496 skbuff = dpriv->tx_skbuff;
497 for (i = 0; i < TX_RING_SIZE; i++) {
498 if (*skbuff) {
499 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
500 (*skbuff)->len, PCI_DMA_TODEVICE);
501 dev_kfree_skb(*skbuff);
502 }
503 skbuff++;
504 tx_fd++;
505 }
506
507 skbuff = dpriv->rx_skbuff;
508 for (i = 0; i < RX_RING_SIZE; i++) {
509 if (*skbuff) {
510 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
511 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
512 dev_kfree_skb(*skbuff);
513 }
514 skbuff++;
515 rx_fd++;
516 }
517 }
518
try_get_rx_skb(struct dscc4_dev_priv * dpriv,struct net_device * dev)519 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
520 struct net_device *dev)
521 {
522 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
523 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
524 const int len = RX_MAX(HDLC_MAX_MRU);
525 struct sk_buff *skb;
526 int ret = 0;
527
528 skb = dev_alloc_skb(len);
529 dpriv->rx_skbuff[dirty] = skb;
530 if (skb) {
531 skb->protocol = hdlc_type_trans(skb, dev);
532 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
533 skb->data, len, PCI_DMA_FROMDEVICE));
534 } else {
535 rx_fd->data = 0;
536 ret = -1;
537 }
538 return ret;
539 }
540
541 /*
542 * IRQ/thread/whatever safe
543 */
dscc4_wait_ack_cec(struct dscc4_dev_priv * dpriv,struct net_device * dev,char * msg)544 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
545 struct net_device *dev, char *msg)
546 {
547 s8 i = 0;
548
549 do {
550 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
551 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
552 msg, i);
553 goto done;
554 }
555 schedule_timeout_uninterruptible(10);
556 rmb();
557 } while (++i > 0);
558 netdev_err(dev, "%s timeout\n", msg);
559 done:
560 return (i >= 0) ? i : -EAGAIN;
561 }
562
dscc4_do_action(struct net_device * dev,char * msg)563 static int dscc4_do_action(struct net_device *dev, char *msg)
564 {
565 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
566 s16 i = 0;
567
568 writel(Action, ioaddr + GCMDR);
569 ioaddr += GSTAR;
570 do {
571 u32 state = readl(ioaddr);
572
573 if (state & ArAck) {
574 netdev_dbg(dev, "%s ack\n", msg);
575 writel(ArAck, ioaddr);
576 goto done;
577 } else if (state & Arf) {
578 netdev_err(dev, "%s failed\n", msg);
579 writel(Arf, ioaddr);
580 i = -1;
581 goto done;
582 }
583 rmb();
584 } while (++i > 0);
585 netdev_err(dev, "%s timeout\n", msg);
586 done:
587 return i;
588 }
589
dscc4_xpr_ack(struct dscc4_dev_priv * dpriv)590 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
591 {
592 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
593 s8 i = 0;
594
595 do {
596 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
597 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
598 break;
599 smp_rmb();
600 schedule_timeout_uninterruptible(10);
601 } while (++i > 0);
602
603 return (i >= 0 ) ? i : -EAGAIN;
604 }
605
606 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
607 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
608 {
609 unsigned long flags;
610
611 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
612 /* Cf errata DS5 p.6 */
613 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
614 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
615 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
616 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
617 writel(Action, dpriv->base_addr + GCMDR);
618 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
619 }
620
621 #endif
622
623 #if 0
624 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
625 {
626 u16 i = 0;
627
628 /* Cf errata DS5 p.7 */
629 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
630 scc_writel(0x00050000, dpriv, dev, CCR2);
631 /*
632 * Must be longer than the time required to fill the fifo.
633 */
634 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
635 udelay(1);
636 wmb();
637 }
638
639 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
640 if (dscc4_do_action(dev, "Rdt") < 0)
641 netdev_err(dev, "Tx reset failed\n");
642 }
643 #endif
644
645 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
dscc4_rx_skb(struct dscc4_dev_priv * dpriv,struct net_device * dev)646 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
647 struct net_device *dev)
648 {
649 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
650 struct pci_dev *pdev = dpriv->pci_priv->pdev;
651 struct sk_buff *skb;
652 int pkt_len;
653
654 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
655 if (!skb) {
656 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
657 goto refill;
658 }
659 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
660 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
661 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
662 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
663 dev->stats.rx_packets++;
664 dev->stats.rx_bytes += pkt_len;
665 skb_put(skb, pkt_len);
666 if (netif_running(dev))
667 skb->protocol = hdlc_type_trans(skb, dev);
668 netif_rx(skb);
669 } else {
670 if (skb->data[pkt_len] & FrameRdo)
671 dev->stats.rx_fifo_errors++;
672 else if (!(skb->data[pkt_len] & FrameCrc))
673 dev->stats.rx_crc_errors++;
674 else if ((skb->data[pkt_len] & (FrameVfr | FrameRab)) !=
675 (FrameVfr | FrameRab))
676 dev->stats.rx_length_errors++;
677 dev->stats.rx_errors++;
678 dev_kfree_skb_irq(skb);
679 }
680 refill:
681 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
682 if (try_get_rx_skb(dpriv, dev) < 0)
683 break;
684 dpriv->rx_dirty++;
685 }
686 dscc4_rx_update(dpriv, dev);
687 rx_fd->state2 = 0x00000000;
688 rx_fd->end = cpu_to_le32(0xbabeface);
689 }
690
dscc4_free1(struct pci_dev * pdev)691 static void dscc4_free1(struct pci_dev *pdev)
692 {
693 struct dscc4_pci_priv *ppriv;
694 struct dscc4_dev_priv *root;
695 int i;
696
697 ppriv = pci_get_drvdata(pdev);
698 root = ppriv->root;
699
700 for (i = 0; i < dev_per_card; i++)
701 unregister_hdlc_device(dscc4_to_dev(root + i));
702
703 pci_set_drvdata(pdev, NULL);
704
705 for (i = 0; i < dev_per_card; i++)
706 free_netdev(root[i].dev);
707 kfree(root);
708 kfree(ppriv);
709 }
710
dscc4_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)711 static int __devinit dscc4_init_one(struct pci_dev *pdev,
712 const struct pci_device_id *ent)
713 {
714 struct dscc4_pci_priv *priv;
715 struct dscc4_dev_priv *dpriv;
716 void __iomem *ioaddr;
717 int i, rc;
718
719 printk(KERN_DEBUG "%s", version);
720
721 rc = pci_enable_device(pdev);
722 if (rc < 0)
723 goto out;
724
725 rc = pci_request_region(pdev, 0, "registers");
726 if (rc < 0) {
727 pr_err("can't reserve MMIO region (regs)\n");
728 goto err_disable_0;
729 }
730 rc = pci_request_region(pdev, 1, "LBI interface");
731 if (rc < 0) {
732 pr_err("can't reserve MMIO region (lbi)\n");
733 goto err_free_mmio_region_1;
734 }
735
736 ioaddr = pci_ioremap_bar(pdev, 0);
737 if (!ioaddr) {
738 pr_err("cannot remap MMIO region %llx @ %llx\n",
739 (unsigned long long)pci_resource_len(pdev, 0),
740 (unsigned long long)pci_resource_start(pdev, 0));
741 rc = -EIO;
742 goto err_free_mmio_regions_2;
743 }
744 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
745 (unsigned long long)pci_resource_start(pdev, 0),
746 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
747
748 /* Cf errata DS5 p.2 */
749 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
750 pci_set_master(pdev);
751
752 rc = dscc4_found1(pdev, ioaddr);
753 if (rc < 0)
754 goto err_iounmap_3;
755
756 priv = pci_get_drvdata(pdev);
757
758 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
759 if (rc < 0) {
760 pr_warn("IRQ %d busy\n", pdev->irq);
761 goto err_release_4;
762 }
763
764 /* power up/little endian/dma core controlled via lrda/ltda */
765 writel(0x00000001, ioaddr + GMODE);
766 /* Shared interrupt queue */
767 {
768 u32 bits;
769
770 bits = (IRQ_RING_SIZE >> 5) - 1;
771 bits |= bits << 4;
772 bits |= bits << 8;
773 bits |= bits << 16;
774 writel(bits, ioaddr + IQLENR0);
775 }
776 /* Global interrupt queue */
777 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
778 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
779 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
780 if (!priv->iqcfg)
781 goto err_free_irq_5;
782 writel(priv->iqcfg_dma, ioaddr + IQCFG);
783
784 rc = -ENOMEM;
785
786 /*
787 * SCC 0-3 private rx/tx irq structures
788 * IQRX/TXi needs to be set soon. Learned it the hard way...
789 */
790 for (i = 0; i < dev_per_card; i++) {
791 dpriv = priv->root + i;
792 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
793 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
794 if (!dpriv->iqtx)
795 goto err_free_iqtx_6;
796 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
797 }
798 for (i = 0; i < dev_per_card; i++) {
799 dpriv = priv->root + i;
800 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
801 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
802 if (!dpriv->iqrx)
803 goto err_free_iqrx_7;
804 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
805 }
806
807 /* Cf application hint. Beware of hard-lock condition on threshold. */
808 writel(0x42104000, ioaddr + FIFOCR1);
809 //writel(0x9ce69800, ioaddr + FIFOCR2);
810 writel(0xdef6d800, ioaddr + FIFOCR2);
811 //writel(0x11111111, ioaddr + FIFOCR4);
812 writel(0x18181818, ioaddr + FIFOCR4);
813 // FIXME: should depend on the chipset revision
814 writel(0x0000000e, ioaddr + FIFOCR3);
815
816 writel(0xff200001, ioaddr + GCMDR);
817
818 rc = 0;
819 out:
820 return rc;
821
822 err_free_iqrx_7:
823 while (--i >= 0) {
824 dpriv = priv->root + i;
825 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
826 dpriv->iqrx, dpriv->iqrx_dma);
827 }
828 i = dev_per_card;
829 err_free_iqtx_6:
830 while (--i >= 0) {
831 dpriv = priv->root + i;
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
833 dpriv->iqtx, dpriv->iqtx_dma);
834 }
835 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
836 priv->iqcfg_dma);
837 err_free_irq_5:
838 free_irq(pdev->irq, priv->root);
839 err_release_4:
840 dscc4_free1(pdev);
841 err_iounmap_3:
842 iounmap (ioaddr);
843 err_free_mmio_regions_2:
844 pci_release_region(pdev, 1);
845 err_free_mmio_region_1:
846 pci_release_region(pdev, 0);
847 err_disable_0:
848 pci_disable_device(pdev);
849 goto out;
850 };
851
852 /*
853 * Let's hope the default values are decent enough to protect my
854 * feet from the user's gun - Ueimor
855 */
dscc4_init_registers(struct dscc4_dev_priv * dpriv,struct net_device * dev)856 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
857 struct net_device *dev)
858 {
859 /* No interrupts, SCC core disabled. Let's relax */
860 scc_writel(0x00000000, dpriv, dev, CCR0);
861
862 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
863
864 /*
865 * No address recognition/crc-CCITT/cts enabled
866 * Shared flags transmission disabled - cf errata DS5 p.11
867 * Carrier detect disabled - cf errata p.14
868 * FIXME: carrier detection/polarity may be handled more gracefully.
869 */
870 scc_writel(0x02408000, dpriv, dev, CCR1);
871
872 /* crc not forwarded - Cf errata DS5 p.11 */
873 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
874 // crc forwarded
875 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
876 }
877
dscc4_set_quartz(struct dscc4_dev_priv * dpriv,int hz)878 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
879 {
880 int ret = 0;
881
882 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
883 ret = -EOPNOTSUPP;
884 else
885 dpriv->pci_priv->xtal_hz = hz;
886
887 return ret;
888 }
889
890 static const struct net_device_ops dscc4_ops = {
891 .ndo_open = dscc4_open,
892 .ndo_stop = dscc4_close,
893 .ndo_change_mtu = hdlc_change_mtu,
894 .ndo_start_xmit = hdlc_start_xmit,
895 .ndo_do_ioctl = dscc4_ioctl,
896 .ndo_tx_timeout = dscc4_tx_timeout,
897 };
898
dscc4_found1(struct pci_dev * pdev,void __iomem * ioaddr)899 static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
900 {
901 struct dscc4_pci_priv *ppriv;
902 struct dscc4_dev_priv *root;
903 int i, ret = -ENOMEM;
904
905 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
906 if (!root) {
907 pr_err("can't allocate data\n");
908 goto err_out;
909 }
910
911 for (i = 0; i < dev_per_card; i++) {
912 root[i].dev = alloc_hdlcdev(root + i);
913 if (!root[i].dev)
914 goto err_free_dev;
915 }
916
917 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
918 if (!ppriv) {
919 pr_err("can't allocate private data\n");
920 goto err_free_dev;
921 }
922
923 ppriv->root = root;
924 spin_lock_init(&ppriv->lock);
925
926 for (i = 0; i < dev_per_card; i++) {
927 struct dscc4_dev_priv *dpriv = root + i;
928 struct net_device *d = dscc4_to_dev(dpriv);
929 hdlc_device *hdlc = dev_to_hdlc(d);
930
931 d->base_addr = (unsigned long)ioaddr;
932 d->irq = pdev->irq;
933 d->netdev_ops = &dscc4_ops;
934 d->watchdog_timeo = TX_TIMEOUT;
935 SET_NETDEV_DEV(d, &pdev->dev);
936
937 dpriv->dev_id = i;
938 dpriv->pci_priv = ppriv;
939 dpriv->base_addr = ioaddr;
940 spin_lock_init(&dpriv->lock);
941
942 hdlc->xmit = dscc4_start_xmit;
943 hdlc->attach = dscc4_hdlc_attach;
944
945 dscc4_init_registers(dpriv, d);
946 dpriv->parity = PARITY_CRC16_PR0_CCITT;
947 dpriv->encoding = ENCODING_NRZ;
948
949 ret = dscc4_init_ring(d);
950 if (ret < 0)
951 goto err_unregister;
952
953 ret = register_hdlc_device(d);
954 if (ret < 0) {
955 pr_err("unable to register\n");
956 dscc4_release_ring(dpriv);
957 goto err_unregister;
958 }
959 }
960
961 ret = dscc4_set_quartz(root, quartz);
962 if (ret < 0)
963 goto err_unregister;
964
965 pci_set_drvdata(pdev, ppriv);
966 return ret;
967
968 err_unregister:
969 while (i-- > 0) {
970 dscc4_release_ring(root + i);
971 unregister_hdlc_device(dscc4_to_dev(root + i));
972 }
973 kfree(ppriv);
974 i = dev_per_card;
975 err_free_dev:
976 while (i-- > 0)
977 free_netdev(root[i].dev);
978 kfree(root);
979 err_out:
980 return ret;
981 };
982
983 /* FIXME: get rid of the unneeded code */
dscc4_timer(unsigned long data)984 static void dscc4_timer(unsigned long data)
985 {
986 struct net_device *dev = (struct net_device *)data;
987 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
988 // struct dscc4_pci_priv *ppriv;
989
990 goto done;
991 done:
992 dpriv->timer.expires = jiffies + TX_TIMEOUT;
993 add_timer(&dpriv->timer);
994 }
995
dscc4_tx_timeout(struct net_device * dev)996 static void dscc4_tx_timeout(struct net_device *dev)
997 {
998 /* FIXME: something is missing there */
999 }
1000
dscc4_loopback_check(struct dscc4_dev_priv * dpriv)1001 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
1002 {
1003 sync_serial_settings *settings = &dpriv->settings;
1004
1005 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1006 struct net_device *dev = dscc4_to_dev(dpriv);
1007
1008 netdev_info(dev, "loopback requires clock\n");
1009 return -1;
1010 }
1011 return 0;
1012 }
1013
1014 #ifdef CONFIG_DSCC4_PCI_RST
1015 /*
1016 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1017 * so as to provide a safe way to reset the asic while not the whole machine
1018 * rebooting.
1019 *
1020 * This code doesn't need to be efficient. Keep It Simple
1021 */
dscc4_pci_reset(struct pci_dev * pdev,void __iomem * ioaddr)1022 static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1023 {
1024 int i;
1025
1026 mutex_lock(&dscc4_mutex);
1027 for (i = 0; i < 16; i++)
1028 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1029
1030 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1031 writel(0x001c0000, ioaddr + GMODE);
1032 /* Configure GPIO port as output */
1033 writel(0x0000ffff, ioaddr + GPDIR);
1034 /* Disable interruption */
1035 writel(0x0000ffff, ioaddr + GPIM);
1036
1037 writel(0x0000ffff, ioaddr + GPDATA);
1038 writel(0x00000000, ioaddr + GPDATA);
1039
1040 /* Flush posted writes */
1041 readl(ioaddr + GSTAR);
1042
1043 schedule_timeout_uninterruptible(10);
1044
1045 for (i = 0; i < 16; i++)
1046 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1047 mutex_unlock(&dscc4_mutex);
1048 }
1049 #else
1050 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1051 #endif /* CONFIG_DSCC4_PCI_RST */
1052
dscc4_open(struct net_device * dev)1053 static int dscc4_open(struct net_device *dev)
1054 {
1055 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1056 struct dscc4_pci_priv *ppriv;
1057 int ret = -EAGAIN;
1058
1059 if ((dscc4_loopback_check(dpriv) < 0))
1060 goto err;
1061
1062 if ((ret = hdlc_open(dev)))
1063 goto err;
1064
1065 ppriv = dpriv->pci_priv;
1066
1067 /*
1068 * Due to various bugs, there is no way to reliably reset a
1069 * specific port (manufacturer's dependent special PCI #RST wiring
1070 * apart: it affects all ports). Thus the device goes in the best
1071 * silent mode possible at dscc4_close() time and simply claims to
1072 * be up if it's opened again. It still isn't possible to change
1073 * the HDLC configuration without rebooting but at least the ports
1074 * can be up/down ifconfig'ed without killing the host.
1075 */
1076 if (dpriv->flags & FakeReset) {
1077 dpriv->flags &= ~FakeReset;
1078 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1079 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1080 scc_writel(EventsMask, dpriv, dev, IMR);
1081 netdev_info(dev, "up again\n");
1082 goto done;
1083 }
1084
1085 /* IDT+IDR during XPR */
1086 dpriv->flags = NeedIDR | NeedIDT;
1087
1088 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1089
1090 /*
1091 * The following is a bit paranoid...
1092 *
1093 * NB: the datasheet "...CEC will stay active if the SCC is in
1094 * power-down mode or..." and CCR2.RAC = 1 are two different
1095 * situations.
1096 */
1097 if (scc_readl_star(dpriv, dev) & SccBusy) {
1098 netdev_err(dev, "busy - try later\n");
1099 ret = -EAGAIN;
1100 goto err_out;
1101 } else
1102 netdev_info(dev, "available - good\n");
1103
1104 scc_writel(EventsMask, dpriv, dev, IMR);
1105
1106 /* Posted write is flushed in the wait_ack loop */
1107 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1108
1109 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1110 goto err_disable_scc_events;
1111
1112 /*
1113 * I would expect XPR near CE completion (before ? after ?).
1114 * At worst, this code won't see a late XPR and people
1115 * will have to re-issue an ifconfig (this is harmless).
1116 * WARNING, a really missing XPR usually means a hardware
1117 * reset is needed. Suggestions anyone ?
1118 */
1119 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1120 pr_err("XPR timeout\n");
1121 goto err_disable_scc_events;
1122 }
1123
1124 if (debug > 2)
1125 dscc4_tx_print(dev, dpriv, "Open");
1126
1127 done:
1128 netif_start_queue(dev);
1129
1130 init_timer(&dpriv->timer);
1131 dpriv->timer.expires = jiffies + 10*HZ;
1132 dpriv->timer.data = (unsigned long)dev;
1133 dpriv->timer.function = dscc4_timer;
1134 add_timer(&dpriv->timer);
1135 netif_carrier_on(dev);
1136
1137 return 0;
1138
1139 err_disable_scc_events:
1140 scc_writel(0xffffffff, dpriv, dev, IMR);
1141 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1142 err_out:
1143 hdlc_close(dev);
1144 err:
1145 return ret;
1146 }
1147
1148 #ifdef DSCC4_POLLING
dscc4_tx_poll(struct dscc4_dev_priv * dpriv,struct net_device * dev)1149 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1150 {
1151 /* FIXME: it's gonna be easy (TM), for sure */
1152 }
1153 #endif /* DSCC4_POLLING */
1154
dscc4_start_xmit(struct sk_buff * skb,struct net_device * dev)1155 static netdev_tx_t dscc4_start_xmit(struct sk_buff *skb,
1156 struct net_device *dev)
1157 {
1158 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1159 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1160 struct TxFD *tx_fd;
1161 int next;
1162
1163 next = dpriv->tx_current%TX_RING_SIZE;
1164 dpriv->tx_skbuff[next] = skb;
1165 tx_fd = dpriv->tx_fd + next;
1166 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1167 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1168 PCI_DMA_TODEVICE));
1169 tx_fd->complete = 0x00000000;
1170 tx_fd->jiffies = jiffies;
1171 mb();
1172
1173 #ifdef DSCC4_POLLING
1174 spin_lock(&dpriv->lock);
1175 while (dscc4_tx_poll(dpriv, dev));
1176 spin_unlock(&dpriv->lock);
1177 #endif
1178
1179 if (debug > 2)
1180 dscc4_tx_print(dev, dpriv, "Xmit");
1181 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1182 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1183 netif_stop_queue(dev);
1184
1185 if (dscc4_tx_quiescent(dpriv, dev))
1186 dscc4_do_tx(dpriv, dev);
1187
1188 return NETDEV_TX_OK;
1189 }
1190
dscc4_close(struct net_device * dev)1191 static int dscc4_close(struct net_device *dev)
1192 {
1193 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1194
1195 del_timer_sync(&dpriv->timer);
1196 netif_stop_queue(dev);
1197
1198 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1199 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1200 scc_writel(0xffffffff, dpriv, dev, IMR);
1201
1202 dpriv->flags |= FakeReset;
1203
1204 hdlc_close(dev);
1205
1206 return 0;
1207 }
1208
dscc4_check_clock_ability(int port)1209 static inline int dscc4_check_clock_ability(int port)
1210 {
1211 int ret = 0;
1212
1213 #ifdef CONFIG_DSCC4_PCISYNC
1214 if (port >= 2)
1215 ret = -1;
1216 #endif
1217 return ret;
1218 }
1219
1220 /*
1221 * DS1 p.137: "There are a total of 13 different clocking modes..."
1222 * ^^
1223 * Design choices:
1224 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1225 * Clock mode 3b _should_ work but the testing seems to make this point
1226 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1227 * This is supposed to provide least surprise "DTE like" behavior.
1228 * - if line rate is specified, clocks are assumed to be locally generated.
1229 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1230 * between these it automagically done according on the required frequency
1231 * scaling. Of course some rounding may take place.
1232 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1233 * appropriate external clocking device for testing.
1234 * - no time-slot/clock mode 5: shameless laziness.
1235 *
1236 * The clock signals wiring can be (is ?) manufacturer dependent. Good luck.
1237 *
1238 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1239 * won't pass the init sequence. For example, straight back-to-back DTE without
1240 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1241 * called.
1242 *
1243 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1244 * DS0 for example)
1245 *
1246 * Clock mode related bits of CCR0:
1247 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1248 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1249 * | | +-------- High Speed: say 0
1250 * | | | +-+-+-- Clock Mode: 0..7
1251 * | | | | | |
1252 * -+-+-+-+-+-+-+-+
1253 * x|x|5|4|3|2|1|0| lower bits
1254 *
1255 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1256 * +-+-+-+------------------ M (0..15)
1257 * | | | | +-+-+-+-+-+-- N (0..63)
1258 * 0 0 0 0 | | | | 0 0 | | | | | |
1259 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1260 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1261 *
1262 */
dscc4_set_clock(struct net_device * dev,u32 * bps,u32 * state)1263 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1264 {
1265 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1266 int ret = -1;
1267 u32 brr;
1268
1269 *state &= ~Ccr0ClockMask;
1270 if (*bps) { /* Clock generated - required for DCE */
1271 u32 n = 0, m = 0, divider;
1272 int xtal;
1273
1274 xtal = dpriv->pci_priv->xtal_hz;
1275 if (!xtal)
1276 goto done;
1277 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1278 goto done;
1279 divider = xtal / *bps;
1280 if (divider > BRR_DIVIDER_MAX) {
1281 divider >>= 4;
1282 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1283 } else
1284 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1285 if (divider >> 22) {
1286 n = 63;
1287 m = 15;
1288 } else if (divider) {
1289 /* Extraction of the 6 highest weighted bits */
1290 m = 0;
1291 while (0xffffffc0 & divider) {
1292 m++;
1293 divider >>= 1;
1294 }
1295 n = divider;
1296 }
1297 brr = (m << 8) | n;
1298 divider = n << m;
1299 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1300 divider <<= 4;
1301 *bps = xtal / divider;
1302 } else {
1303 /*
1304 * External clock - DTE
1305 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1306 * Nothing more to be done
1307 */
1308 brr = 0;
1309 }
1310 scc_writel(brr, dpriv, dev, BRR);
1311 ret = 0;
1312 done:
1313 return ret;
1314 }
1315
dscc4_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)1316 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1317 {
1318 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1319 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1320 const size_t size = sizeof(dpriv->settings);
1321 int ret = 0;
1322
1323 if (dev->flags & IFF_UP)
1324 return -EBUSY;
1325
1326 if (cmd != SIOCWANDEV)
1327 return -EOPNOTSUPP;
1328
1329 switch(ifr->ifr_settings.type) {
1330 case IF_GET_IFACE:
1331 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1332 if (ifr->ifr_settings.size < size) {
1333 ifr->ifr_settings.size = size; /* data size wanted */
1334 return -ENOBUFS;
1335 }
1336 if (copy_to_user(line, &dpriv->settings, size))
1337 return -EFAULT;
1338 break;
1339
1340 case IF_IFACE_SYNC_SERIAL:
1341 if (!capable(CAP_NET_ADMIN))
1342 return -EPERM;
1343
1344 if (dpriv->flags & FakeReset) {
1345 netdev_info(dev, "please reset the device before this command\n");
1346 return -EPERM;
1347 }
1348 if (copy_from_user(&dpriv->settings, line, size))
1349 return -EFAULT;
1350 ret = dscc4_set_iface(dpriv, dev);
1351 break;
1352
1353 default:
1354 ret = hdlc_ioctl(dev, ifr, cmd);
1355 break;
1356 }
1357
1358 return ret;
1359 }
1360
dscc4_match(const struct thingie * p,int value)1361 static int dscc4_match(const struct thingie *p, int value)
1362 {
1363 int i;
1364
1365 for (i = 0; p[i].define != -1; i++) {
1366 if (value == p[i].define)
1367 break;
1368 }
1369 if (p[i].define == -1)
1370 return -1;
1371 else
1372 return i;
1373 }
1374
dscc4_clock_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1375 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1376 struct net_device *dev)
1377 {
1378 sync_serial_settings *settings = &dpriv->settings;
1379 int ret = -EOPNOTSUPP;
1380 u32 bps, state;
1381
1382 bps = settings->clock_rate;
1383 state = scc_readl(dpriv, CCR0);
1384 if (dscc4_set_clock(dev, &bps, &state) < 0)
1385 goto done;
1386 if (bps) { /* DCE */
1387 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1388 if (settings->clock_rate != bps) {
1389 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1390 dev->name, settings->clock_rate, bps);
1391 settings->clock_rate = bps;
1392 }
1393 } else { /* DTE */
1394 state |= PowerUp | Vis;
1395 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1396 }
1397 scc_writel(state, dpriv, dev, CCR0);
1398 ret = 0;
1399 done:
1400 return ret;
1401 }
1402
dscc4_encoding_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1403 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1404 struct net_device *dev)
1405 {
1406 static const struct thingie encoding[] = {
1407 { ENCODING_NRZ, 0x00000000 },
1408 { ENCODING_NRZI, 0x00200000 },
1409 { ENCODING_FM_MARK, 0x00400000 },
1410 { ENCODING_FM_SPACE, 0x00500000 },
1411 { ENCODING_MANCHESTER, 0x00600000 },
1412 { -1, 0}
1413 };
1414 int i, ret = 0;
1415
1416 i = dscc4_match(encoding, dpriv->encoding);
1417 if (i >= 0)
1418 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1419 else
1420 ret = -EOPNOTSUPP;
1421 return ret;
1422 }
1423
dscc4_loopback_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1424 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1425 struct net_device *dev)
1426 {
1427 sync_serial_settings *settings = &dpriv->settings;
1428 u32 state;
1429
1430 state = scc_readl(dpriv, CCR1);
1431 if (settings->loopback) {
1432 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1433 state |= 0x00000100;
1434 } else {
1435 printk(KERN_DEBUG "%s: normal\n", dev->name);
1436 state &= ~0x00000100;
1437 }
1438 scc_writel(state, dpriv, dev, CCR1);
1439 return 0;
1440 }
1441
dscc4_crc_setting(struct dscc4_dev_priv * dpriv,struct net_device * dev)1442 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1443 struct net_device *dev)
1444 {
1445 static const struct thingie crc[] = {
1446 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1447 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1448 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1449 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1450 };
1451 int i, ret = 0;
1452
1453 i = dscc4_match(crc, dpriv->parity);
1454 if (i >= 0)
1455 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1456 else
1457 ret = -EOPNOTSUPP;
1458 return ret;
1459 }
1460
dscc4_set_iface(struct dscc4_dev_priv * dpriv,struct net_device * dev)1461 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1462 {
1463 struct {
1464 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1465 } *p, do_setting[] = {
1466 { dscc4_encoding_setting },
1467 { dscc4_clock_setting },
1468 { dscc4_loopback_setting },
1469 { dscc4_crc_setting },
1470 { NULL }
1471 };
1472 int ret = 0;
1473
1474 for (p = do_setting; p->action; p++) {
1475 if ((ret = p->action(dpriv, dev)) < 0)
1476 break;
1477 }
1478 return ret;
1479 }
1480
dscc4_irq(int irq,void * token)1481 static irqreturn_t dscc4_irq(int irq, void *token)
1482 {
1483 struct dscc4_dev_priv *root = token;
1484 struct dscc4_pci_priv *priv;
1485 struct net_device *dev;
1486 void __iomem *ioaddr;
1487 u32 state;
1488 unsigned long flags;
1489 int i, handled = 1;
1490
1491 priv = root->pci_priv;
1492 dev = dscc4_to_dev(root);
1493
1494 spin_lock_irqsave(&priv->lock, flags);
1495
1496 ioaddr = root->base_addr;
1497
1498 state = readl(ioaddr + GSTAR);
1499 if (!state) {
1500 handled = 0;
1501 goto out;
1502 }
1503 if (debug > 3)
1504 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1505 writel(state, ioaddr + GSTAR);
1506
1507 if (state & Arf) {
1508 netdev_err(dev, "failure (Arf). Harass the maintainer\n");
1509 goto out;
1510 }
1511 state &= ~ArAck;
1512 if (state & Cfg) {
1513 if (debug > 0)
1514 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1515 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1516 netdev_err(dev, "CFG failed\n");
1517 if (!(state &= ~Cfg))
1518 goto out;
1519 }
1520 if (state & RxEvt) {
1521 i = dev_per_card - 1;
1522 do {
1523 dscc4_rx_irq(priv, root + i);
1524 } while (--i >= 0);
1525 state &= ~RxEvt;
1526 }
1527 if (state & TxEvt) {
1528 i = dev_per_card - 1;
1529 do {
1530 dscc4_tx_irq(priv, root + i);
1531 } while (--i >= 0);
1532 state &= ~TxEvt;
1533 }
1534 out:
1535 spin_unlock_irqrestore(&priv->lock, flags);
1536 return IRQ_RETVAL(handled);
1537 }
1538
dscc4_tx_irq(struct dscc4_pci_priv * ppriv,struct dscc4_dev_priv * dpriv)1539 static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1540 struct dscc4_dev_priv *dpriv)
1541 {
1542 struct net_device *dev = dscc4_to_dev(dpriv);
1543 u32 state;
1544 int cur, loop = 0;
1545
1546 try:
1547 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1548 state = le32_to_cpu(dpriv->iqtx[cur]);
1549 if (!state) {
1550 if (debug > 4)
1551 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1552 state);
1553 if ((debug > 1) && (loop > 1))
1554 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1555 if (loop && netif_queue_stopped(dev))
1556 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1557 netif_wake_queue(dev);
1558
1559 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1560 !dscc4_tx_done(dpriv))
1561 dscc4_do_tx(dpriv, dev);
1562 return;
1563 }
1564 loop++;
1565 dpriv->iqtx[cur] = 0;
1566 dpriv->iqtx_current++;
1567
1568 if (state_check(state, dpriv, dev, "Tx") < 0)
1569 return;
1570
1571 if (state & SccEvt) {
1572 if (state & Alls) {
1573 struct sk_buff *skb;
1574 struct TxFD *tx_fd;
1575
1576 if (debug > 2)
1577 dscc4_tx_print(dev, dpriv, "Alls");
1578 /*
1579 * DataComplete can't be trusted for Tx completion.
1580 * Cf errata DS5 p.8
1581 */
1582 cur = dpriv->tx_dirty%TX_RING_SIZE;
1583 tx_fd = dpriv->tx_fd + cur;
1584 skb = dpriv->tx_skbuff[cur];
1585 if (skb) {
1586 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1587 skb->len, PCI_DMA_TODEVICE);
1588 if (tx_fd->state & FrameEnd) {
1589 dev->stats.tx_packets++;
1590 dev->stats.tx_bytes += skb->len;
1591 }
1592 dev_kfree_skb_irq(skb);
1593 dpriv->tx_skbuff[cur] = NULL;
1594 ++dpriv->tx_dirty;
1595 } else {
1596 if (debug > 1)
1597 netdev_err(dev, "Tx: NULL skb %d\n",
1598 cur);
1599 }
1600 /*
1601 * If the driver ends sending crap on the wire, it
1602 * will be way easier to diagnose than the (not so)
1603 * random freeze induced by null sized tx frames.
1604 */
1605 tx_fd->data = tx_fd->next;
1606 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1607 tx_fd->complete = 0x00000000;
1608 tx_fd->jiffies = 0;
1609
1610 if (!(state &= ~Alls))
1611 goto try;
1612 }
1613 /*
1614 * Transmit Data Underrun
1615 */
1616 if (state & Xdu) {
1617 netdev_err(dev, "Tx Data Underrun. Ask maintainer\n");
1618 dpriv->flags = NeedIDT;
1619 /* Tx reset */
1620 writel(MTFi | Rdt,
1621 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1622 writel(Action, dpriv->base_addr + GCMDR);
1623 return;
1624 }
1625 if (state & Cts) {
1626 netdev_info(dev, "CTS transition\n");
1627 if (!(state &= ~Cts)) /* DEBUG */
1628 goto try;
1629 }
1630 if (state & Xmr) {
1631 /* Frame needs to be sent again - FIXME */
1632 netdev_err(dev, "Tx ReTx. Ask maintainer\n");
1633 if (!(state &= ~Xmr)) /* DEBUG */
1634 goto try;
1635 }
1636 if (state & Xpr) {
1637 void __iomem *scc_addr;
1638 unsigned long ring;
1639 int i;
1640
1641 /*
1642 * - the busy condition happens (sometimes);
1643 * - it doesn't seem to make the handler unreliable.
1644 */
1645 for (i = 1; i; i <<= 1) {
1646 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1647 break;
1648 }
1649 if (!i)
1650 netdev_info(dev, "busy in irq\n");
1651
1652 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1653 /* Keep this order: IDT before IDR */
1654 if (dpriv->flags & NeedIDT) {
1655 if (debug > 2)
1656 dscc4_tx_print(dev, dpriv, "Xpr");
1657 ring = dpriv->tx_fd_dma +
1658 (dpriv->tx_dirty%TX_RING_SIZE)*
1659 sizeof(struct TxFD);
1660 writel(ring, scc_addr + CH0BTDA);
1661 dscc4_do_tx(dpriv, dev);
1662 writel(MTFi | Idt, scc_addr + CH0CFG);
1663 if (dscc4_do_action(dev, "IDT") < 0)
1664 goto err_xpr;
1665 dpriv->flags &= ~NeedIDT;
1666 }
1667 if (dpriv->flags & NeedIDR) {
1668 ring = dpriv->rx_fd_dma +
1669 (dpriv->rx_current%RX_RING_SIZE)*
1670 sizeof(struct RxFD);
1671 writel(ring, scc_addr + CH0BRDA);
1672 dscc4_rx_update(dpriv, dev);
1673 writel(MTFi | Idr, scc_addr + CH0CFG);
1674 if (dscc4_do_action(dev, "IDR") < 0)
1675 goto err_xpr;
1676 dpriv->flags &= ~NeedIDR;
1677 smp_wmb();
1678 /* Activate receiver and misc */
1679 scc_writel(0x08050008, dpriv, dev, CCR2);
1680 }
1681 err_xpr:
1682 if (!(state &= ~Xpr))
1683 goto try;
1684 }
1685 if (state & Cd) {
1686 if (debug > 0)
1687 netdev_info(dev, "CD transition\n");
1688 if (!(state &= ~Cd)) /* DEBUG */
1689 goto try;
1690 }
1691 } else { /* ! SccEvt */
1692 if (state & Hi) {
1693 #ifdef DSCC4_POLLING
1694 while (!dscc4_tx_poll(dpriv, dev));
1695 #endif
1696 netdev_info(dev, "Tx Hi\n");
1697 state &= ~Hi;
1698 }
1699 if (state & Err) {
1700 netdev_info(dev, "Tx ERR\n");
1701 dev->stats.tx_errors++;
1702 state &= ~Err;
1703 }
1704 }
1705 goto try;
1706 }
1707
dscc4_rx_irq(struct dscc4_pci_priv * priv,struct dscc4_dev_priv * dpriv)1708 static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1709 struct dscc4_dev_priv *dpriv)
1710 {
1711 struct net_device *dev = dscc4_to_dev(dpriv);
1712 u32 state;
1713 int cur;
1714
1715 try:
1716 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1717 state = le32_to_cpu(dpriv->iqrx[cur]);
1718 if (!state)
1719 return;
1720 dpriv->iqrx[cur] = 0;
1721 dpriv->iqrx_current++;
1722
1723 if (state_check(state, dpriv, dev, "Rx") < 0)
1724 return;
1725
1726 if (!(state & SccEvt)){
1727 struct RxFD *rx_fd;
1728
1729 if (debug > 4)
1730 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1731 state);
1732 state &= 0x00ffffff;
1733 if (state & Err) { /* Hold or reset */
1734 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1735 cur = dpriv->rx_current%RX_RING_SIZE;
1736 rx_fd = dpriv->rx_fd + cur;
1737 /*
1738 * Presume we're not facing a DMAC receiver reset.
1739 * As We use the rx size-filtering feature of the
1740 * DSCC4, the beginning of a new frame is waiting in
1741 * the rx fifo. I bet a Receive Data Overflow will
1742 * happen most of time but let's try and avoid it.
1743 * Btw (as for RDO) if one experiences ERR whereas
1744 * the system looks rather idle, there may be a
1745 * problem with latency. In this case, increasing
1746 * RX_RING_SIZE may help.
1747 */
1748 //while (dpriv->rx_needs_refill) {
1749 while (!(rx_fd->state1 & Hold)) {
1750 rx_fd++;
1751 cur++;
1752 if (!(cur = cur%RX_RING_SIZE))
1753 rx_fd = dpriv->rx_fd;
1754 }
1755 //dpriv->rx_needs_refill--;
1756 try_get_rx_skb(dpriv, dev);
1757 if (!rx_fd->data)
1758 goto try;
1759 rx_fd->state1 &= ~Hold;
1760 rx_fd->state2 = 0x00000000;
1761 rx_fd->end = cpu_to_le32(0xbabeface);
1762 //}
1763 goto try;
1764 }
1765 if (state & Fi) {
1766 dscc4_rx_skb(dpriv, dev);
1767 goto try;
1768 }
1769 if (state & Hi ) { /* HI bit */
1770 netdev_info(dev, "Rx Hi\n");
1771 state &= ~Hi;
1772 goto try;
1773 }
1774 } else { /* SccEvt */
1775 if (debug > 1) {
1776 //FIXME: verifier la presence de tous les evenements
1777 static struct {
1778 u32 mask;
1779 const char *irq_name;
1780 } evts[] = {
1781 { 0x00008000, "TIN"},
1782 { 0x00000020, "RSC"},
1783 { 0x00000010, "PCE"},
1784 { 0x00000008, "PLLA"},
1785 { 0, NULL}
1786 }, *evt;
1787
1788 for (evt = evts; evt->irq_name; evt++) {
1789 if (state & evt->mask) {
1790 printk(KERN_DEBUG "%s: %s\n",
1791 dev->name, evt->irq_name);
1792 if (!(state &= ~evt->mask))
1793 goto try;
1794 }
1795 }
1796 } else {
1797 if (!(state &= ~0x0000c03c))
1798 goto try;
1799 }
1800 if (state & Cts) {
1801 netdev_info(dev, "CTS transition\n");
1802 if (!(state &= ~Cts)) /* DEBUG */
1803 goto try;
1804 }
1805 /*
1806 * Receive Data Overflow (FIXME: fscked)
1807 */
1808 if (state & Rdo) {
1809 struct RxFD *rx_fd;
1810 void __iomem *scc_addr;
1811 int cur;
1812
1813 //if (debug)
1814 // dscc4_rx_dump(dpriv);
1815 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1816
1817 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1818 /*
1819 * This has no effect. Why ?
1820 * ORed with TxSccRes, one sees the CFG ack (for
1821 * the TX part only).
1822 */
1823 scc_writel(RxSccRes, dpriv, dev, CMDR);
1824 dpriv->flags |= RdoSet;
1825
1826 /*
1827 * Let's try and save something in the received data.
1828 * rx_current must be incremented at least once to
1829 * avoid HOLD in the BRDA-to-be-pointed desc.
1830 */
1831 do {
1832 cur = dpriv->rx_current++%RX_RING_SIZE;
1833 rx_fd = dpriv->rx_fd + cur;
1834 if (!(rx_fd->state2 & DataComplete))
1835 break;
1836 if (rx_fd->state2 & FrameAborted) {
1837 dev->stats.rx_over_errors++;
1838 rx_fd->state1 |= Hold;
1839 rx_fd->state2 = 0x00000000;
1840 rx_fd->end = cpu_to_le32(0xbabeface);
1841 } else
1842 dscc4_rx_skb(dpriv, dev);
1843 } while (1);
1844
1845 if (debug > 0) {
1846 if (dpriv->flags & RdoSet)
1847 printk(KERN_DEBUG
1848 "%s: no RDO in Rx data\n", DRV_NAME);
1849 }
1850 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1851 /*
1852 * FIXME: must the reset be this violent ?
1853 */
1854 #warning "FIXME: CH0BRDA"
1855 writel(dpriv->rx_fd_dma +
1856 (dpriv->rx_current%RX_RING_SIZE)*
1857 sizeof(struct RxFD), scc_addr + CH0BRDA);
1858 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1859 if (dscc4_do_action(dev, "RDR") < 0) {
1860 netdev_err(dev, "RDO recovery failed(RDR)\n");
1861 goto rdo_end;
1862 }
1863 writel(MTFi|Idr, scc_addr + CH0CFG);
1864 if (dscc4_do_action(dev, "IDR") < 0) {
1865 netdev_err(dev, "RDO recovery failed(IDR)\n");
1866 goto rdo_end;
1867 }
1868 rdo_end:
1869 #endif
1870 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1871 goto try;
1872 }
1873 if (state & Cd) {
1874 netdev_info(dev, "CD transition\n");
1875 if (!(state &= ~Cd)) /* DEBUG */
1876 goto try;
1877 }
1878 if (state & Flex) {
1879 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1880 if (!(state &= ~Flex))
1881 goto try;
1882 }
1883 }
1884 }
1885
1886 /*
1887 * I had expected the following to work for the first descriptor
1888 * (tx_fd->state = 0xc0000000)
1889 * - Hold=1 (don't try and branch to the next descripto);
1890 * - No=0 (I want an empty data section, i.e. size=0);
1891 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1892 * It failed and locked solid. Thus the introduction of a dummy skb.
1893 * Problem is acknowledged in errata sheet DS5. Joy :o/
1894 */
dscc4_init_dummy_skb(struct dscc4_dev_priv * dpriv)1895 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1896 {
1897 struct sk_buff *skb;
1898
1899 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1900 if (skb) {
1901 int last = dpriv->tx_dirty%TX_RING_SIZE;
1902 struct TxFD *tx_fd = dpriv->tx_fd + last;
1903
1904 skb->len = DUMMY_SKB_SIZE;
1905 skb_copy_to_linear_data(skb, version,
1906 strlen(version) % DUMMY_SKB_SIZE);
1907 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1908 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1909 skb->data, DUMMY_SKB_SIZE,
1910 PCI_DMA_TODEVICE));
1911 dpriv->tx_skbuff[last] = skb;
1912 }
1913 return skb;
1914 }
1915
dscc4_init_ring(struct net_device * dev)1916 static int dscc4_init_ring(struct net_device *dev)
1917 {
1918 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1919 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1920 struct TxFD *tx_fd;
1921 struct RxFD *rx_fd;
1922 void *ring;
1923 int i;
1924
1925 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1926 if (!ring)
1927 goto err_out;
1928 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1929
1930 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1931 if (!ring)
1932 goto err_free_dma_rx;
1933 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1934
1935 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1936 dpriv->tx_dirty = 0xffffffff;
1937 i = dpriv->tx_current = 0;
1938 do {
1939 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1940 tx_fd->complete = 0x00000000;
1941 /* FIXME: NULL should be ok - to be tried */
1942 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1943 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1944 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1945 } while (i < TX_RING_SIZE);
1946
1947 if (!dscc4_init_dummy_skb(dpriv))
1948 goto err_free_dma_tx;
1949
1950 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1951 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1952 do {
1953 /* size set by the host. Multiple of 4 bytes please */
1954 rx_fd->state1 = HiDesc;
1955 rx_fd->state2 = 0x00000000;
1956 rx_fd->end = cpu_to_le32(0xbabeface);
1957 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1958 // FIXME: return value verifiee mais traitement suspect
1959 if (try_get_rx_skb(dpriv, dev) >= 0)
1960 dpriv->rx_dirty++;
1961 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1962 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1963 } while (i < RX_RING_SIZE);
1964
1965 return 0;
1966
1967 err_free_dma_tx:
1968 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1969 err_free_dma_rx:
1970 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1971 err_out:
1972 return -ENOMEM;
1973 }
1974
dscc4_remove_one(struct pci_dev * pdev)1975 static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1976 {
1977 struct dscc4_pci_priv *ppriv;
1978 struct dscc4_dev_priv *root;
1979 void __iomem *ioaddr;
1980 int i;
1981
1982 ppriv = pci_get_drvdata(pdev);
1983 root = ppriv->root;
1984
1985 ioaddr = root->base_addr;
1986
1987 dscc4_pci_reset(pdev, ioaddr);
1988
1989 free_irq(pdev->irq, root);
1990 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1991 ppriv->iqcfg_dma);
1992 for (i = 0; i < dev_per_card; i++) {
1993 struct dscc4_dev_priv *dpriv = root + i;
1994
1995 dscc4_release_ring(dpriv);
1996 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1997 dpriv->iqrx, dpriv->iqrx_dma);
1998 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1999 dpriv->iqtx, dpriv->iqtx_dma);
2000 }
2001
2002 dscc4_free1(pdev);
2003
2004 iounmap(ioaddr);
2005
2006 pci_release_region(pdev, 1);
2007 pci_release_region(pdev, 0);
2008
2009 pci_disable_device(pdev);
2010 }
2011
dscc4_hdlc_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)2012 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2013 unsigned short parity)
2014 {
2015 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2016
2017 if (encoding != ENCODING_NRZ &&
2018 encoding != ENCODING_NRZI &&
2019 encoding != ENCODING_FM_MARK &&
2020 encoding != ENCODING_FM_SPACE &&
2021 encoding != ENCODING_MANCHESTER)
2022 return -EINVAL;
2023
2024 if (parity != PARITY_NONE &&
2025 parity != PARITY_CRC16_PR0_CCITT &&
2026 parity != PARITY_CRC16_PR1_CCITT &&
2027 parity != PARITY_CRC32_PR0_CCITT &&
2028 parity != PARITY_CRC32_PR1_CCITT)
2029 return -EINVAL;
2030
2031 dpriv->encoding = encoding;
2032 dpriv->parity = parity;
2033 return 0;
2034 }
2035
2036 #ifndef MODULE
dscc4_setup(char * str)2037 static int __init dscc4_setup(char *str)
2038 {
2039 int *args[] = { &debug, &quartz, NULL }, **p = args;
2040
2041 while (*p && (get_option(&str, *p) == 2))
2042 p++;
2043 return 1;
2044 }
2045
2046 __setup("dscc4.setup=", dscc4_setup);
2047 #endif
2048
2049 static DEFINE_PCI_DEVICE_TABLE(dscc4_pci_tbl) = {
2050 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2051 PCI_ANY_ID, PCI_ANY_ID, },
2052 { 0,}
2053 };
2054 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2055
2056 static struct pci_driver dscc4_driver = {
2057 .name = DRV_NAME,
2058 .id_table = dscc4_pci_tbl,
2059 .probe = dscc4_init_one,
2060 .remove = __devexit_p(dscc4_remove_one),
2061 };
2062
dscc4_init_module(void)2063 static int __init dscc4_init_module(void)
2064 {
2065 return pci_register_driver(&dscc4_driver);
2066 }
2067
dscc4_cleanup_module(void)2068 static void __exit dscc4_cleanup_module(void)
2069 {
2070 pci_unregister_driver(&dscc4_driver);
2071 }
2072
2073 module_init(dscc4_init_module);
2074 module_exit(dscc4_cleanup_module);
2075