1 /*
2  * Driver for ICPlus PHYs
3  *
4  * Copyright (c) 2007 Freescale Semiconductor, Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  *
11  */
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/errno.h>
15 #include <linux/unistd.h>
16 #include <linux/interrupt.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/netdevice.h>
20 #include <linux/etherdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/spinlock.h>
23 #include <linux/mm.h>
24 #include <linux/module.h>
25 #include <linux/mii.h>
26 #include <linux/ethtool.h>
27 #include <linux/phy.h>
28 
29 #include <asm/io.h>
30 #include <asm/irq.h>
31 #include <asm/uaccess.h>
32 
33 MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
34 MODULE_AUTHOR("Michael Barkowski");
35 MODULE_LICENSE("GPL");
36 
37 /* IP101A/G - IP1001 */
38 #define IP10XX_SPEC_CTRL_STATUS		16	/* Spec. Control Register */
39 #define IP1001_SPEC_CTRL_STATUS_2	20	/* IP1001 Spec. Control Reg 2 */
40 #define IP1001_PHASE_SEL_MASK		3	/* IP1001 RX/TXPHASE_SEL */
41 #define IP1001_APS_ON			11	/* IP1001 APS Mode  bit */
42 #define IP101A_G_APS_ON			2	/* IP101A/G APS Mode bit */
43 
ip175c_config_init(struct phy_device * phydev)44 static int ip175c_config_init(struct phy_device *phydev)
45 {
46 	int err, i;
47 	static int full_reset_performed = 0;
48 
49 	if (full_reset_performed == 0) {
50 
51 		/* master reset */
52 		err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
53 		if (err < 0)
54 			return err;
55 
56 		/* ensure no bus delays overlap reset period */
57 		err = mdiobus_read(phydev->bus, 30, 0);
58 
59 		/* data sheet specifies reset period is 2 msec */
60 		mdelay(2);
61 
62 		/* enable IP175C mode */
63 		err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
64 		if (err < 0)
65 			return err;
66 
67 		/* Set MII0 speed and duplex (in PHY mode) */
68 		err = mdiobus_write(phydev->bus, 29, 22, 0x420);
69 		if (err < 0)
70 			return err;
71 
72 		/* reset switch ports */
73 		for (i = 0; i < 5; i++) {
74 			err = mdiobus_write(phydev->bus, i,
75 					    MII_BMCR, BMCR_RESET);
76 			if (err < 0)
77 				return err;
78 		}
79 
80 		for (i = 0; i < 5; i++)
81 			err = mdiobus_read(phydev->bus, i, MII_BMCR);
82 
83 		mdelay(2);
84 
85 		full_reset_performed = 1;
86 	}
87 
88 	if (phydev->addr != 4) {
89 		phydev->state = PHY_RUNNING;
90 		phydev->speed = SPEED_100;
91 		phydev->duplex = DUPLEX_FULL;
92 		phydev->link = 1;
93 		netif_carrier_on(phydev->attached_dev);
94 	}
95 
96 	return 0;
97 }
98 
ip1xx_reset(struct phy_device * phydev)99 static int ip1xx_reset(struct phy_device *phydev)
100 {
101 	int bmcr;
102 
103 	/* Software Reset PHY */
104 	bmcr = phy_read(phydev, MII_BMCR);
105 	if (bmcr < 0)
106 		return bmcr;
107 	bmcr |= BMCR_RESET;
108 	bmcr = phy_write(phydev, MII_BMCR, bmcr);
109 	if (bmcr < 0)
110 		return bmcr;
111 
112 	do {
113 		bmcr = phy_read(phydev, MII_BMCR);
114 		if (bmcr < 0)
115 			return bmcr;
116 	} while (bmcr & BMCR_RESET);
117 
118 	return 0;
119 }
120 
ip1001_config_init(struct phy_device * phydev)121 static int ip1001_config_init(struct phy_device *phydev)
122 {
123 	int c;
124 
125 	c = ip1xx_reset(phydev);
126 	if (c < 0)
127 		return c;
128 
129 	/* Enable Auto Power Saving mode */
130 	c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
131 	if (c < 0)
132 		return c;
133 	c |= IP1001_APS_ON;
134 	c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
135 	if (c < 0)
136 		return c;
137 
138 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
139 		/* Additional delay (2ns) used to adjust RX clock phase
140 		 * at RGMII interface */
141 		c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
142 		if (c < 0)
143 			return c;
144 
145 		c |= IP1001_PHASE_SEL_MASK;
146 		c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
147 		if (c < 0)
148 			return c;
149 	}
150 
151 	return 0;
152 }
153 
ip101a_g_config_init(struct phy_device * phydev)154 static int ip101a_g_config_init(struct phy_device *phydev)
155 {
156 	int c;
157 
158 	c = ip1xx_reset(phydev);
159 	if (c < 0)
160 		return c;
161 
162 	/* Enable Auto Power Saving mode */
163 	c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
164 	c |= IP101A_G_APS_ON;
165 	return c;
166 }
167 
ip175c_read_status(struct phy_device * phydev)168 static int ip175c_read_status(struct phy_device *phydev)
169 {
170 	if (phydev->addr == 4) /* WAN port */
171 		genphy_read_status(phydev);
172 	else
173 		/* Don't need to read status for switch ports */
174 		phydev->irq = PHY_IGNORE_INTERRUPT;
175 
176 	return 0;
177 }
178 
ip175c_config_aneg(struct phy_device * phydev)179 static int ip175c_config_aneg(struct phy_device *phydev)
180 {
181 	if (phydev->addr == 4) /* WAN port */
182 		genphy_config_aneg(phydev);
183 
184 	return 0;
185 }
186 
187 static struct phy_driver ip175c_driver = {
188 	.phy_id		= 0x02430d80,
189 	.name		= "ICPlus IP175C",
190 	.phy_id_mask	= 0x0ffffff0,
191 	.features	= PHY_BASIC_FEATURES,
192 	.config_init	= &ip175c_config_init,
193 	.config_aneg	= &ip175c_config_aneg,
194 	.read_status	= &ip175c_read_status,
195 	.suspend	= genphy_suspend,
196 	.resume		= genphy_resume,
197 	.driver		= { .owner = THIS_MODULE,},
198 };
199 
200 static struct phy_driver ip1001_driver = {
201 	.phy_id		= 0x02430d90,
202 	.name		= "ICPlus IP1001",
203 	.phy_id_mask	= 0x0ffffff0,
204 	.features	= PHY_GBIT_FEATURES | SUPPORTED_Pause |
205 			  SUPPORTED_Asym_Pause,
206 	.flags		= PHY_HAS_INTERRUPT,
207 	.config_init	= &ip1001_config_init,
208 	.config_aneg	= &genphy_config_aneg,
209 	.read_status	= &genphy_read_status,
210 	.suspend	= genphy_suspend,
211 	.resume		= genphy_resume,
212 	.driver		= { .owner = THIS_MODULE,},
213 };
214 
215 static struct phy_driver ip101a_g_driver = {
216 	.phy_id		= 0x02430c54,
217 	.name		= "ICPlus IP101A/G",
218 	.phy_id_mask	= 0x0ffffff0,
219 	.features	= PHY_BASIC_FEATURES | SUPPORTED_Pause |
220 			  SUPPORTED_Asym_Pause,
221 	.flags		= PHY_HAS_INTERRUPT,
222 	.config_init	= &ip101a_g_config_init,
223 	.config_aneg	= &genphy_config_aneg,
224 	.read_status	= &genphy_read_status,
225 	.suspend	= genphy_suspend,
226 	.resume		= genphy_resume,
227 	.driver		= { .owner = THIS_MODULE,},
228 };
229 
icplus_init(void)230 static int __init icplus_init(void)
231 {
232 	int ret = 0;
233 
234 	ret = phy_driver_register(&ip1001_driver);
235 	if (ret < 0)
236 		return -ENODEV;
237 
238 	ret = phy_driver_register(&ip101a_g_driver);
239 	if (ret < 0)
240 		return -ENODEV;
241 
242 	return phy_driver_register(&ip175c_driver);
243 }
244 
icplus_exit(void)245 static void __exit icplus_exit(void)
246 {
247 	phy_driver_unregister(&ip1001_driver);
248 	phy_driver_unregister(&ip101a_g_driver);
249 	phy_driver_unregister(&ip175c_driver);
250 }
251 
252 module_init(icplus_init);
253 module_exit(icplus_exit);
254 
255 static struct mdio_device_id __maybe_unused icplus_tbl[] = {
256 	{ 0x02430d80, 0x0ffffff0 },
257 	{ 0x02430d90, 0x0ffffff0 },
258 	{ 0x02430c54, 0x0ffffff0 },
259 	{ }
260 };
261 
262 MODULE_DEVICE_TABLE(mdio, icplus_tbl);
263