1 /*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 .
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
24 .
25 . Authors
26 . Dustin McIntire <dustin@sensoria.com>
27 .
28 ---------------------------------------------------------------------------*/
29 #ifndef _SMC911X_H_
30 #define _SMC911X_H_
31
32 #include <linux/smc911x.h>
33 /*
34 * Use the DMA feature on PXA chips
35 */
36 #ifdef CONFIG_ARCH_PXA
37 #define SMC_USE_PXA_DMA 1
38 #define SMC_USE_16BIT 0
39 #define SMC_USE_32BIT 1
40 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
41 #elif defined(CONFIG_SH_MAGIC_PANEL_R2)
42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45 #elif defined(CONFIG_ARCH_OMAP3)
46 #define SMC_USE_16BIT 0
47 #define SMC_USE_32BIT 1
48 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
49 #define SMC_MEM_RESERVED 1
50 #elif defined(CONFIG_ARCH_OMAP2)
51 #define SMC_USE_16BIT 0
52 #define SMC_USE_32BIT 1
53 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
54 #define SMC_MEM_RESERVED 1
55 #else
56 /*
57 * Default configuration
58 */
59
60 #define SMC_DYNAMIC_BUS_CONFIG
61 #endif
62
63 #ifdef SMC_USE_PXA_DMA
64 #define SMC_USE_DMA
65 #endif
66
67 /* store this information for the driver.. */
68 struct smc911x_local {
69 /*
70 * If I have to wait until the DMA is finished and ready to reload a
71 * packet, I will store the skbuff here. Then, the DMA will send it
72 * out and free it.
73 */
74 struct sk_buff *pending_tx_skb;
75
76 /* version/revision of the SMC911x chip */
77 u16 version;
78 u16 revision;
79
80 /* FIFO sizes */
81 int tx_fifo_kb;
82 int tx_fifo_size;
83 int rx_fifo_size;
84 int afc_cfg;
85
86 /* Contains the current active receive/phy mode */
87 int ctl_rfduplx;
88 int ctl_rspeed;
89
90 u32 msg_enable;
91 u32 phy_type;
92 struct mii_if_info mii;
93
94 /* work queue */
95 struct work_struct phy_configure;
96
97 int tx_throttle;
98 spinlock_t lock;
99
100 struct net_device *netdev;
101
102 #ifdef SMC_USE_DMA
103 /* DMA needs the physical address of the chip */
104 u_long physaddr;
105 int rxdma;
106 int txdma;
107 int rxdma_active;
108 int txdma_active;
109 struct sk_buff *current_rx_skb;
110 struct sk_buff *current_tx_skb;
111 struct device *dev;
112 #endif
113 void __iomem *base;
114 #ifdef SMC_DYNAMIC_BUS_CONFIG
115 struct smc911x_platdata cfg;
116 #endif
117 };
118
119 /*
120 * Define the bus width specific IO macros
121 */
122
123 #ifdef SMC_DYNAMIC_BUS_CONFIG
SMC_inl(struct smc911x_local * lp,int reg)124 static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
125 {
126 void __iomem *ioaddr = lp->base + reg;
127
128 if (lp->cfg.flags & SMC911X_USE_32BIT)
129 return readl(ioaddr);
130
131 if (lp->cfg.flags & SMC911X_USE_16BIT)
132 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
133
134 BUG();
135 }
136
SMC_outl(unsigned int value,struct smc911x_local * lp,int reg)137 static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
138 int reg)
139 {
140 void __iomem *ioaddr = lp->base + reg;
141
142 if (lp->cfg.flags & SMC911X_USE_32BIT) {
143 writel(value, ioaddr);
144 return;
145 }
146
147 if (lp->cfg.flags & SMC911X_USE_16BIT) {
148 writew(value & 0xffff, ioaddr);
149 writew(value >> 16, ioaddr + 2);
150 return;
151 }
152
153 BUG();
154 }
155
SMC_insl(struct smc911x_local * lp,int reg,void * addr,unsigned int count)156 static inline void SMC_insl(struct smc911x_local *lp, int reg,
157 void *addr, unsigned int count)
158 {
159 void __iomem *ioaddr = lp->base + reg;
160
161 if (lp->cfg.flags & SMC911X_USE_32BIT) {
162 readsl(ioaddr, addr, count);
163 return;
164 }
165
166 if (lp->cfg.flags & SMC911X_USE_16BIT) {
167 readsw(ioaddr, addr, count * 2);
168 return;
169 }
170
171 BUG();
172 }
173
SMC_outsl(struct smc911x_local * lp,int reg,void * addr,unsigned int count)174 static inline void SMC_outsl(struct smc911x_local *lp, int reg,
175 void *addr, unsigned int count)
176 {
177 void __iomem *ioaddr = lp->base + reg;
178
179 if (lp->cfg.flags & SMC911X_USE_32BIT) {
180 writesl(ioaddr, addr, count);
181 return;
182 }
183
184 if (lp->cfg.flags & SMC911X_USE_16BIT) {
185 writesw(ioaddr, addr, count * 2);
186 return;
187 }
188
189 BUG();
190 }
191 #else
192 #if SMC_USE_16BIT
193 #define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
194 #define SMC_outl(v, lp, r) \
195 do{ \
196 writew(v & 0xFFFF, (lp)->base + (r)); \
197 writew(v >> 16, (lp)->base + (r) + 2); \
198 } while (0)
199 #define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
200 #define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
201
202 #elif SMC_USE_32BIT
203 #define SMC_inl(lp, r) readl((lp)->base + (r))
204 #define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
205 #define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
206 #define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
207
208 #endif /* SMC_USE_16BIT */
209 #endif /* SMC_DYNAMIC_BUS_CONFIG */
210
211
212 #ifdef SMC_USE_PXA_DMA
213
214 #include <mach/dma.h>
215
216 /*
217 * Define the request and free functions
218 * These are unfortunately architecture specific as no generic allocation
219 * mechanism exits
220 */
221 #define SMC_DMA_REQUEST(dev, handler) \
222 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
223
224 #define SMC_DMA_FREE(dev, dma) \
225 pxa_free_dma(dma)
226
227 #define SMC_DMA_ACK_IRQ(dev, dma) \
228 { \
229 if (DCSR(dma) & DCSR_BUSERR) { \
230 printk("%s: DMA %d bus error!\n", dev->name, dma); \
231 } \
232 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
233 }
234
235 /*
236 * Use a DMA for RX and TX packets.
237 */
238 #include <linux/dma-mapping.h>
239
240 static dma_addr_t rx_dmabuf, tx_dmabuf;
241 static int rx_dmalen, tx_dmalen;
242
243 #ifdef SMC_insl
244 #undef SMC_insl
245 #define SMC_insl(lp, r, p, l) \
246 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
247
248 static inline void
smc_pxa_dma_insl(struct smc911x_local * lp,u_long physaddr,int reg,int dma,u_char * buf,int len)249 smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
250 int reg, int dma, u_char *buf, int len)
251 {
252 /* 64 bit alignment is required for memory to memory DMA */
253 if ((long)buf & 4) {
254 *((u32 *)buf) = SMC_inl(lp, reg);
255 buf += 4;
256 len--;
257 }
258
259 len *= 4;
260 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
261 rx_dmalen = len;
262 DCSR(dma) = DCSR_NODESC;
263 DTADR(dma) = rx_dmabuf;
264 DSADR(dma) = physaddr + reg;
265 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
266 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
267 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
268 }
269 #endif
270
271 #ifdef SMC_outsl
272 #undef SMC_outsl
273 #define SMC_outsl(lp, r, p, l) \
274 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
275
276 static inline void
smc_pxa_dma_outsl(struct smc911x_local * lp,u_long physaddr,int reg,int dma,u_char * buf,int len)277 smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
278 int reg, int dma, u_char *buf, int len)
279 {
280 /* 64 bit alignment is required for memory to memory DMA */
281 if ((long)buf & 4) {
282 SMC_outl(*((u32 *)buf), lp, reg);
283 buf += 4;
284 len--;
285 }
286
287 len *= 4;
288 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
289 tx_dmalen = len;
290 DCSR(dma) = DCSR_NODESC;
291 DSADR(dma) = tx_dmabuf;
292 DTADR(dma) = physaddr + reg;
293 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
294 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
295 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
296 }
297 #endif
298 #endif /* SMC_USE_PXA_DMA */
299
300
301 /* Chip Parameters and Register Definitions */
302
303 #define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
304
305 #define SMC911X_IO_EXTENT 0x100
306
307 #define SMC911X_EEPROM_LEN 7
308
309 /* Below are the register offsets and bit definitions
310 * of the Lan911x memory space
311 */
312 #define RX_DATA_FIFO (0x00)
313
314 #define TX_DATA_FIFO (0x20)
315 #define TX_CMD_A_INT_ON_COMP_ (0x80000000)
316 #define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
317 #define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
318 #define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
319 #define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
320 #define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
321 #define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
322 #define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
323 #define TX_CMD_A_BUF_SIZE_ (0x000007FF)
324 #define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
325 #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
326 #define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
327 #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
328
329 #define RX_STATUS_FIFO (0x40)
330 #define RX_STS_PKT_LEN_ (0x3FFF0000)
331 #define RX_STS_ES_ (0x00008000)
332 #define RX_STS_BCST_ (0x00002000)
333 #define RX_STS_LEN_ERR_ (0x00001000)
334 #define RX_STS_RUNT_ERR_ (0x00000800)
335 #define RX_STS_MCAST_ (0x00000400)
336 #define RX_STS_TOO_LONG_ (0x00000080)
337 #define RX_STS_COLL_ (0x00000040)
338 #define RX_STS_ETH_TYPE_ (0x00000020)
339 #define RX_STS_WDOG_TMT_ (0x00000010)
340 #define RX_STS_MII_ERR_ (0x00000008)
341 #define RX_STS_DRIBBLING_ (0x00000004)
342 #define RX_STS_CRC_ERR_ (0x00000002)
343 #define RX_STATUS_FIFO_PEEK (0x44)
344 #define TX_STATUS_FIFO (0x48)
345 #define TX_STS_TAG_ (0xFFFF0000)
346 #define TX_STS_ES_ (0x00008000)
347 #define TX_STS_LOC_ (0x00000800)
348 #define TX_STS_NO_CARR_ (0x00000400)
349 #define TX_STS_LATE_COLL_ (0x00000200)
350 #define TX_STS_MANY_COLL_ (0x00000100)
351 #define TX_STS_COLL_CNT_ (0x00000078)
352 #define TX_STS_MANY_DEFER_ (0x00000004)
353 #define TX_STS_UNDERRUN_ (0x00000002)
354 #define TX_STS_DEFERRED_ (0x00000001)
355 #define TX_STATUS_FIFO_PEEK (0x4C)
356 #define ID_REV (0x50)
357 #define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
358 #define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
359
360 #define INT_CFG (0x54)
361 #define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
362 #define INT_CFG_INT_DEAS_CLR_ (0x00004000)
363 #define INT_CFG_INT_DEAS_STS_ (0x00002000)
364 #define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
365 #define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
366 #define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
367 #define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
368
369 #define INT_STS (0x58)
370 #define INT_STS_SW_INT_ (0x80000000) /* R/WC */
371 #define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
372 #define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
373 #define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
374 #define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
375 #define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
376 #define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
377 #define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
378 #define INT_STS_PHY_INT_ (0x00040000) /* RO */
379 #define INT_STS_PME_INT_ (0x00020000) /* R/WC */
380 #define INT_STS_TXSO_ (0x00010000) /* R/WC */
381 #define INT_STS_RWT_ (0x00008000) /* R/WC */
382 #define INT_STS_RXE_ (0x00004000) /* R/WC */
383 #define INT_STS_TXE_ (0x00002000) /* R/WC */
384 //#define INT_STS_ERX_ (0x00001000) /* R/WC */
385 #define INT_STS_TDFU_ (0x00000800) /* R/WC */
386 #define INT_STS_TDFO_ (0x00000400) /* R/WC */
387 #define INT_STS_TDFA_ (0x00000200) /* R/WC */
388 #define INT_STS_TSFF_ (0x00000100) /* R/WC */
389 #define INT_STS_TSFL_ (0x00000080) /* R/WC */
390 //#define INT_STS_RXDF_ (0x00000040) /* R/WC */
391 #define INT_STS_RDFO_ (0x00000040) /* R/WC */
392 #define INT_STS_RDFL_ (0x00000020) /* R/WC */
393 #define INT_STS_RSFF_ (0x00000010) /* R/WC */
394 #define INT_STS_RSFL_ (0x00000008) /* R/WC */
395 #define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
396 #define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
397 #define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
398
399 #define INT_EN (0x5C)
400 #define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
401 #define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
402 #define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
403 #define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
404 //#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
405 #define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
406 #define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
407 #define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
408 #define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
409 #define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
410 #define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
411 #define INT_EN_RWT_EN_ (0x00008000) /* R/W */
412 #define INT_EN_RXE_EN_ (0x00004000) /* R/W */
413 #define INT_EN_TXE_EN_ (0x00002000) /* R/W */
414 //#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
415 #define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
416 #define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
417 #define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
418 #define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
419 #define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
420 //#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
421 #define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
422 #define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
423 #define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
424 #define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
425 #define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
426 #define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
427 #define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
428
429 #define BYTE_TEST (0x64)
430 #define FIFO_INT (0x68)
431 #define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
432 #define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
433 #define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
434 #define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
435
436 #define RX_CFG (0x6C)
437 #define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
438 #define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
439 #define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
440 #define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
441 #define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
442 #define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
443 #define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
444 //#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
445
446 #define TX_CFG (0x70)
447 //#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
448 //#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
449 #define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
450 #define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
451 #define TX_CFG_TXSAO_ (0x00000004) /* R/W */
452 #define TX_CFG_TX_ON_ (0x00000002) /* R/W */
453 #define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
454
455 #define HW_CFG (0x74)
456 #define HW_CFG_TTM_ (0x00200000) /* R/W */
457 #define HW_CFG_SF_ (0x00100000) /* R/W */
458 #define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
459 #define HW_CFG_TR_ (0x00003000) /* R/W */
460 #define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
461 #define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
462 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
463 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
464 #define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
465 #define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
466 #define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
467 #define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
468 #define HW_CFG_SRST_TO_ (0x00000002) /* RO */
469 #define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
470
471 #define RX_DP_CTRL (0x78)
472 #define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
473 #define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
474
475 #define RX_FIFO_INF (0x7C)
476 #define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
477 #define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
478
479 #define TX_FIFO_INF (0x80)
480 #define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
481 #define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
482
483 #define PMT_CTRL (0x84)
484 #define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
485 #define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
486 #define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
487 #define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
488 #define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
489 #define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
490 #define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
491 #define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
492 #define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
493 #define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
494 #define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
495 #define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
496 #define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
497 #define PMT_CTRL_READY_ (0x00000001) /* RO */
498
499 #define GPIO_CFG (0x88)
500 #define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
501 #define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
502 #define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
503 #define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
504 #define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
505 #define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
506 #define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
507 #define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
508 #define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
509 #define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
510 #define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
511 #define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
512 #define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
513 #define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
514 #define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
515 #define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
516 #define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
517 #define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
518
519 #define GPT_CFG (0x8C)
520 #define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
521 #define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
522
523 #define GPT_CNT (0x90)
524 #define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
525
526 #define ENDIAN (0x98)
527 #define FREE_RUN (0x9C)
528 #define RX_DROP (0xA0)
529 #define MAC_CSR_CMD (0xA4)
530 #define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
531 #define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
532 #define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
533
534 #define MAC_CSR_DATA (0xA8)
535 #define AFC_CFG (0xAC)
536 #define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
537 #define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
538 #define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
539 #define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
540 #define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
541 #define AFC_CFG_FCADD_ (0x00000002) /* R/W */
542 #define AFC_CFG_FCANY_ (0x00000001) /* R/W */
543
544 #define E2P_CMD (0xB0)
545 #define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
546 #define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
547 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
548 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
549 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
550 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
551 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
552 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
553 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
554 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
555 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
556 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
557 #define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
558
559 #define E2P_DATA (0xB4)
560 #define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
561 /* end of LAN register offsets and bit definitions */
562
563 /*
564 ****************************************************************************
565 ****************************************************************************
566 * MAC Control and Status Register (Indirect Address)
567 * Offset (through the MAC_CSR CMD and DATA port)
568 ****************************************************************************
569 ****************************************************************************
570 *
571 */
572 #define MAC_CR (0x01) /* R/W */
573
574 /* MAC_CR - MAC Control Register */
575 #define MAC_CR_RXALL_ (0x80000000)
576 // TODO: delete this bit? It is not described in the data sheet.
577 #define MAC_CR_HBDIS_ (0x10000000)
578 #define MAC_CR_RCVOWN_ (0x00800000)
579 #define MAC_CR_LOOPBK_ (0x00200000)
580 #define MAC_CR_FDPX_ (0x00100000)
581 #define MAC_CR_MCPAS_ (0x00080000)
582 #define MAC_CR_PRMS_ (0x00040000)
583 #define MAC_CR_INVFILT_ (0x00020000)
584 #define MAC_CR_PASSBAD_ (0x00010000)
585 #define MAC_CR_HFILT_ (0x00008000)
586 #define MAC_CR_HPFILT_ (0x00002000)
587 #define MAC_CR_LCOLL_ (0x00001000)
588 #define MAC_CR_BCAST_ (0x00000800)
589 #define MAC_CR_DISRTY_ (0x00000400)
590 #define MAC_CR_PADSTR_ (0x00000100)
591 #define MAC_CR_BOLMT_MASK_ (0x000000C0)
592 #define MAC_CR_DFCHK_ (0x00000020)
593 #define MAC_CR_TXEN_ (0x00000008)
594 #define MAC_CR_RXEN_ (0x00000004)
595
596 #define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
597 #define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
598 #define HASHH (0x04) /* R/W */
599 #define HASHL (0x05) /* R/W */
600
601 #define MII_ACC (0x06) /* R/W */
602 #define MII_ACC_PHY_ADDR_ (0x0000F800)
603 #define MII_ACC_MIIRINDA_ (0x000007C0)
604 #define MII_ACC_MII_WRITE_ (0x00000002)
605 #define MII_ACC_MII_BUSY_ (0x00000001)
606
607 #define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
608
609 #define FLOW (0x08) /* R/W */
610 #define FLOW_FCPT_ (0xFFFF0000)
611 #define FLOW_FCPASS_ (0x00000004)
612 #define FLOW_FCEN_ (0x00000002)
613 #define FLOW_FCBSY_ (0x00000001)
614
615 #define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
616 #define VLAN1_VTI1_ (0x0000ffff)
617
618 #define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
619 #define VLAN2_VTI2_ (0x0000ffff)
620
621 #define WUFF (0x0B) /* WO */
622
623 #define WUCSR (0x0C) /* R/W */
624 #define WUCSR_GUE_ (0x00000200)
625 #define WUCSR_WUFR_ (0x00000040)
626 #define WUCSR_MPR_ (0x00000020)
627 #define WUCSR_WAKE_EN_ (0x00000004)
628 #define WUCSR_MPEN_ (0x00000002)
629
630 /*
631 ****************************************************************************
632 * Chip Specific MII Defines
633 ****************************************************************************
634 *
635 * Phy register offsets and bit definitions
636 *
637 */
638
639 #define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
640 //#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
641 #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
642 //#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
643 //#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
644 //#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
645 //#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
646 //#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
647 //#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
648 //#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
649 #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
650
651 #define PHY_INT_SRC ((u32)29)
652 #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
653 #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
654 #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
655 #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
656 #define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
657 #define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
658 #define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
659
660 #define PHY_INT_MASK ((u32)30)
661 #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
662 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
663 #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
664 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
665 #define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
666 #define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
667 #define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
668
669 #define PHY_SPECIAL ((u32)31)
670 #define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
671 #define PHY_SPECIAL_RES_ ((u16)0x0040)
672 #define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
673 #define PHY_SPECIAL_SPD_ ((u16)0x001C)
674 #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
675 #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
676 #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
677 #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
678
679 #define LAN911X_INTERNAL_PHY_ID (0x0007C000)
680
681 /* Chip ID values */
682 #define CHIP_9115 0x0115
683 #define CHIP_9116 0x0116
684 #define CHIP_9117 0x0117
685 #define CHIP_9118 0x0118
686 #define CHIP_9211 0x9211
687 #define CHIP_9215 0x115A
688 #define CHIP_9217 0x117A
689 #define CHIP_9218 0x118A
690
691 struct chip_id {
692 u16 id;
693 char *name;
694 };
695
696 static const struct chip_id chip_ids[] = {
697 { CHIP_9115, "LAN9115" },
698 { CHIP_9116, "LAN9116" },
699 { CHIP_9117, "LAN9117" },
700 { CHIP_9118, "LAN9118" },
701 { CHIP_9211, "LAN9211" },
702 { CHIP_9215, "LAN9215" },
703 { CHIP_9217, "LAN9217" },
704 { CHIP_9218, "LAN9218" },
705 { 0, NULL },
706 };
707
708 #define IS_REV_A(x) ((x & 0xFFFF)==0)
709
710 /*
711 * Macros to abstract register access according to the data bus
712 * capabilities. Please use those and not the in/out primitives.
713 */
714 /* FIFO read/write macros */
715 #define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
716 #define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
717 #define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
718 #define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
719
720
721 /* I/O mapped register read/write macros */
722 #define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
723 #define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
724 #define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
725 #define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
726 #define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
727 #define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
728 #define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
729 #define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
730 #define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
731 #define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
732 #define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
733 #define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
734 #define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
735 #define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
736 #define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
737 #define SMC_SET_FIFO_TDA(lp, x) \
738 do { \
739 unsigned long __flags; \
740 int __mask; \
741 local_irq_save(__flags); \
742 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
743 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
744 local_irq_restore(__flags); \
745 } while (0)
746 #define SMC_SET_FIFO_TSL(lp, x) \
747 do { \
748 unsigned long __flags; \
749 int __mask; \
750 local_irq_save(__flags); \
751 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
752 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
753 local_irq_restore(__flags); \
754 } while (0)
755 #define SMC_SET_FIFO_RSA(lp, x) \
756 do { \
757 unsigned long __flags; \
758 int __mask; \
759 local_irq_save(__flags); \
760 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
761 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
762 local_irq_restore(__flags); \
763 } while (0)
764 #define SMC_SET_FIFO_RSL(lp, x) \
765 do { \
766 unsigned long __flags; \
767 int __mask; \
768 local_irq_save(__flags); \
769 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
770 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
771 local_irq_restore(__flags); \
772 } while (0)
773 #define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
774 #define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
775 #define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
776 #define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
777 #define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
778 #define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
779 #define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
780 #define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
781 #define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
782 #define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
783 #define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
784 #define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
785 #define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
786 #define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
787 #define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
788 #define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
789 #define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
790 #define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
791 #define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
792 #define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
793 #define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
794 #define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
795 #define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
796 #define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
797 #define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
798 #define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
799 #define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
800 #define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
801 #define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
802 #define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
803
804 /* MAC register read/write macros */
805 #define SMC_GET_MAC_CSR(lp,a,v) \
806 do { \
807 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
808 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
809 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
810 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
811 v = SMC_GET_MAC_DATA((lp)); \
812 } while (0)
813 #define SMC_SET_MAC_CSR(lp,a,v) \
814 do { \
815 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
816 SMC_SET_MAC_DATA((lp), v); \
817 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
818 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
819 } while (0)
820 #define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
821 #define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
822 #define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
823 #define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
824 #define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
825 #define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
826 #define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
827 #define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
828 #define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
829 #define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
830 #define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
831 #define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
832 #define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
833 #define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
834 #define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
835 #define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
836 #define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
837 #define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
838 #define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
839 #define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
840 #define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
841 #define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
842 #define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
843
844 /* PHY register read/write macros */
845 #define SMC_GET_MII(lp,a,phy,v) \
846 do { \
847 u32 __v; \
848 do { \
849 SMC_GET_MII_ACC((lp), __v); \
850 } while ( __v & MII_ACC_MII_BUSY_ ); \
851 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
852 MII_ACC_MII_BUSY_); \
853 do { \
854 SMC_GET_MII_ACC( (lp), __v); \
855 } while ( __v & MII_ACC_MII_BUSY_ ); \
856 SMC_GET_MII_DATA((lp), v); \
857 } while (0)
858 #define SMC_SET_MII(lp,a,phy,v) \
859 do { \
860 u32 __v; \
861 do { \
862 SMC_GET_MII_ACC((lp), __v); \
863 } while ( __v & MII_ACC_MII_BUSY_ ); \
864 SMC_SET_MII_DATA((lp), v); \
865 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
866 MII_ACC_MII_BUSY_ | \
867 MII_ACC_MII_WRITE_ ); \
868 do { \
869 SMC_GET_MII_ACC((lp), __v); \
870 } while ( __v & MII_ACC_MII_BUSY_ ); \
871 } while (0)
872 #define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
873 #define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
874 #define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
875 #define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
876 #define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
877 #define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
878 #define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
879 #define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
880 #define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
881 #define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
882 #define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
883 #define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
884 #define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
885 #define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
886 #define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
887 #define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
888
889
890
891 /* Misc read/write macros */
892
893 #ifndef SMC_GET_MAC_ADDR
894 #define SMC_GET_MAC_ADDR(lp, addr) \
895 do { \
896 unsigned int __v; \
897 \
898 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
899 addr[0] = __v; addr[1] = __v >> 8; \
900 addr[2] = __v >> 16; addr[3] = __v >> 24; \
901 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
902 addr[4] = __v; addr[5] = __v >> 8; \
903 } while (0)
904 #endif
905
906 #define SMC_SET_MAC_ADDR(lp, addr) \
907 do { \
908 SMC_SET_MAC_CSR((lp), ADDRL, \
909 addr[0] | \
910 (addr[1] << 8) | \
911 (addr[2] << 16) | \
912 (addr[3] << 24)); \
913 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
914 } while (0)
915
916
917 #define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
918 do { \
919 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
920 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
921 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
922 } while (0)
923
924 #endif /* _SMC911X_H_ */
925