1 /*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/resource.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/io.h>
32 #include <linux/slab.h>
33 #include <linux/mtd/fsmc.h>
34 #include <linux/amba/bus.h>
35 #include <mtd/mtd-abi.h>
36
37 static struct nand_ecclayout fsmc_ecc1_layout = {
38 .eccbytes = 24,
39 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
41 .oobfree = {
42 {.offset = 8, .length = 8},
43 {.offset = 24, .length = 8},
44 {.offset = 40, .length = 8},
45 {.offset = 56, .length = 8},
46 {.offset = 72, .length = 8},
47 {.offset = 88, .length = 8},
48 {.offset = 104, .length = 8},
49 {.offset = 120, .length = 8}
50 }
51 };
52
53 static struct nand_ecclayout fsmc_ecc4_lp_layout = {
54 .eccbytes = 104,
55 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
56 9, 10, 11, 12, 13, 14,
57 18, 19, 20, 21, 22, 23, 24,
58 25, 26, 27, 28, 29, 30,
59 34, 35, 36, 37, 38, 39, 40,
60 41, 42, 43, 44, 45, 46,
61 50, 51, 52, 53, 54, 55, 56,
62 57, 58, 59, 60, 61, 62,
63 66, 67, 68, 69, 70, 71, 72,
64 73, 74, 75, 76, 77, 78,
65 82, 83, 84, 85, 86, 87, 88,
66 89, 90, 91, 92, 93, 94,
67 98, 99, 100, 101, 102, 103, 104,
68 105, 106, 107, 108, 109, 110,
69 114, 115, 116, 117, 118, 119, 120,
70 121, 122, 123, 124, 125, 126
71 },
72 .oobfree = {
73 {.offset = 15, .length = 3},
74 {.offset = 31, .length = 3},
75 {.offset = 47, .length = 3},
76 {.offset = 63, .length = 3},
77 {.offset = 79, .length = 3},
78 {.offset = 95, .length = 3},
79 {.offset = 111, .length = 3},
80 {.offset = 127, .length = 1}
81 }
82 };
83
84 /*
85 * ECC placement definitions in oobfree type format.
86 * There are 13 bytes of ecc for every 512 byte block and it has to be read
87 * consecutively and immediately after the 512 byte data block for hardware to
88 * generate the error bit offsets in 512 byte data.
89 * Managing the ecc bytes in the following way makes it easier for software to
90 * read ecc bytes consecutive to data bytes. This way is similar to
91 * oobfree structure maintained already in generic nand driver
92 */
93 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
94 .eccplace = {
95 {.offset = 2, .length = 13},
96 {.offset = 18, .length = 13},
97 {.offset = 34, .length = 13},
98 {.offset = 50, .length = 13},
99 {.offset = 66, .length = 13},
100 {.offset = 82, .length = 13},
101 {.offset = 98, .length = 13},
102 {.offset = 114, .length = 13}
103 }
104 };
105
106 static struct nand_ecclayout fsmc_ecc4_sp_layout = {
107 .eccbytes = 13,
108 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
109 9, 10, 11, 12, 13, 14
110 },
111 .oobfree = {
112 {.offset = 15, .length = 1},
113 }
114 };
115
116 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
117 .eccplace = {
118 {.offset = 0, .length = 4},
119 {.offset = 6, .length = 9}
120 }
121 };
122
123 /*
124 * Default partition tables to be used if the partition information not
125 * provided through platform data.
126 *
127 * Default partition layout for small page(= 512 bytes) devices
128 * Size for "Root file system" is updated in driver based on actual device size
129 */
130 static struct mtd_partition partition_info_16KB_blk[] = {
131 {
132 .name = "X-loader",
133 .offset = 0,
134 .size = 4*0x4000,
135 },
136 {
137 .name = "U-Boot",
138 .offset = 0x10000,
139 .size = 20*0x4000,
140 },
141 {
142 .name = "Kernel",
143 .offset = 0x60000,
144 .size = 256*0x4000,
145 },
146 {
147 .name = "Root File System",
148 .offset = 0x460000,
149 .size = MTDPART_SIZ_FULL,
150 },
151 };
152
153 /*
154 * Default partition layout for large page(> 512 bytes) devices
155 * Size for "Root file system" is updated in driver based on actual device size
156 */
157 static struct mtd_partition partition_info_128KB_blk[] = {
158 {
159 .name = "X-loader",
160 .offset = 0,
161 .size = 4*0x20000,
162 },
163 {
164 .name = "U-Boot",
165 .offset = 0x80000,
166 .size = 12*0x20000,
167 },
168 {
169 .name = "Kernel",
170 .offset = 0x200000,
171 .size = 48*0x20000,
172 },
173 {
174 .name = "Root File System",
175 .offset = 0x800000,
176 .size = MTDPART_SIZ_FULL,
177 },
178 };
179
180
181 /**
182 * struct fsmc_nand_data - structure for FSMC NAND device state
183 *
184 * @pid: Part ID on the AMBA PrimeCell format
185 * @mtd: MTD info for a NAND flash.
186 * @nand: Chip related info for a NAND flash.
187 *
188 * @ecc_place: ECC placing locations in oobfree type format.
189 * @bank: Bank number for probed device.
190 * @clk: Clock structure for FSMC.
191 *
192 * @data_va: NAND port for Data.
193 * @cmd_va: NAND port for Command.
194 * @addr_va: NAND port for Address.
195 * @regs_va: FSMC regs base address.
196 */
197 struct fsmc_nand_data {
198 u32 pid;
199 struct mtd_info mtd;
200 struct nand_chip nand;
201
202 struct fsmc_eccplace *ecc_place;
203 unsigned int bank;
204 struct clk *clk;
205
206 struct resource *resregs;
207 struct resource *rescmd;
208 struct resource *resaddr;
209 struct resource *resdata;
210
211 void __iomem *data_va;
212 void __iomem *cmd_va;
213 void __iomem *addr_va;
214 void __iomem *regs_va;
215
216 void (*select_chip)(uint32_t bank, uint32_t busw);
217 };
218
219 /* Assert CS signal based on chipnr */
fsmc_select_chip(struct mtd_info * mtd,int chipnr)220 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
221 {
222 struct nand_chip *chip = mtd->priv;
223 struct fsmc_nand_data *host;
224
225 host = container_of(mtd, struct fsmc_nand_data, mtd);
226
227 switch (chipnr) {
228 case -1:
229 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
230 break;
231 case 0:
232 case 1:
233 case 2:
234 case 3:
235 if (host->select_chip)
236 host->select_chip(chipnr,
237 chip->options & NAND_BUSWIDTH_16);
238 break;
239
240 default:
241 BUG();
242 }
243 }
244
245 /*
246 * fsmc_cmd_ctrl - For facilitaing Hardware access
247 * This routine allows hardware specific access to control-lines(ALE,CLE)
248 */
fsmc_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)249 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
250 {
251 struct nand_chip *this = mtd->priv;
252 struct fsmc_nand_data *host = container_of(mtd,
253 struct fsmc_nand_data, mtd);
254 struct fsmc_regs *regs = host->regs_va;
255 unsigned int bank = host->bank;
256
257 if (ctrl & NAND_CTRL_CHANGE) {
258 if (ctrl & NAND_CLE) {
259 this->IO_ADDR_R = (void __iomem *)host->cmd_va;
260 this->IO_ADDR_W = (void __iomem *)host->cmd_va;
261 } else if (ctrl & NAND_ALE) {
262 this->IO_ADDR_R = (void __iomem *)host->addr_va;
263 this->IO_ADDR_W = (void __iomem *)host->addr_va;
264 } else {
265 this->IO_ADDR_R = (void __iomem *)host->data_va;
266 this->IO_ADDR_W = (void __iomem *)host->data_va;
267 }
268
269 if (ctrl & NAND_NCE) {
270 writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE,
271 ®s->bank_regs[bank].pc);
272 } else {
273 writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE,
274 ®s->bank_regs[bank].pc);
275 }
276 }
277
278 mb();
279
280 if (cmd != NAND_CMD_NONE)
281 writeb(cmd, this->IO_ADDR_W);
282 }
283
284 /*
285 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
286 *
287 * This routine initializes timing parameters related to NAND memory access in
288 * FSMC registers
289 */
fsmc_nand_setup(struct fsmc_regs * regs,uint32_t bank,uint32_t busw)290 static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
291 uint32_t busw)
292 {
293 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
294
295 if (busw)
296 writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc);
297 else
298 writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc);
299
300 writel(readl(®s->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
301 ®s->bank_regs[bank].pc);
302 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
303 ®s->bank_regs[bank].comm);
304 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
305 ®s->bank_regs[bank].attrib);
306 }
307
308 /*
309 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
310 */
fsmc_enable_hwecc(struct mtd_info * mtd,int mode)311 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
312 {
313 struct fsmc_nand_data *host = container_of(mtd,
314 struct fsmc_nand_data, mtd);
315 struct fsmc_regs *regs = host->regs_va;
316 uint32_t bank = host->bank;
317
318 writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
319 ®s->bank_regs[bank].pc);
320 writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN,
321 ®s->bank_regs[bank].pc);
322 writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN,
323 ®s->bank_regs[bank].pc);
324 }
325
326 /*
327 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
328 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
329 * max of 8-bits)
330 */
fsmc_read_hwecc_ecc4(struct mtd_info * mtd,const uint8_t * data,uint8_t * ecc)331 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
332 uint8_t *ecc)
333 {
334 struct fsmc_nand_data *host = container_of(mtd,
335 struct fsmc_nand_data, mtd);
336 struct fsmc_regs *regs = host->regs_va;
337 uint32_t bank = host->bank;
338 uint32_t ecc_tmp;
339 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
340
341 do {
342 if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY)
343 break;
344 else
345 cond_resched();
346 } while (!time_after_eq(jiffies, deadline));
347
348 ecc_tmp = readl(®s->bank_regs[bank].ecc1);
349 ecc[0] = (uint8_t) (ecc_tmp >> 0);
350 ecc[1] = (uint8_t) (ecc_tmp >> 8);
351 ecc[2] = (uint8_t) (ecc_tmp >> 16);
352 ecc[3] = (uint8_t) (ecc_tmp >> 24);
353
354 ecc_tmp = readl(®s->bank_regs[bank].ecc2);
355 ecc[4] = (uint8_t) (ecc_tmp >> 0);
356 ecc[5] = (uint8_t) (ecc_tmp >> 8);
357 ecc[6] = (uint8_t) (ecc_tmp >> 16);
358 ecc[7] = (uint8_t) (ecc_tmp >> 24);
359
360 ecc_tmp = readl(®s->bank_regs[bank].ecc3);
361 ecc[8] = (uint8_t) (ecc_tmp >> 0);
362 ecc[9] = (uint8_t) (ecc_tmp >> 8);
363 ecc[10] = (uint8_t) (ecc_tmp >> 16);
364 ecc[11] = (uint8_t) (ecc_tmp >> 24);
365
366 ecc_tmp = readl(®s->bank_regs[bank].sts);
367 ecc[12] = (uint8_t) (ecc_tmp >> 16);
368
369 return 0;
370 }
371
372 /*
373 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
374 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
375 * max of 1-bit)
376 */
fsmc_read_hwecc_ecc1(struct mtd_info * mtd,const uint8_t * data,uint8_t * ecc)377 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
378 uint8_t *ecc)
379 {
380 struct fsmc_nand_data *host = container_of(mtd,
381 struct fsmc_nand_data, mtd);
382 struct fsmc_regs *regs = host->regs_va;
383 uint32_t bank = host->bank;
384 uint32_t ecc_tmp;
385
386 ecc_tmp = readl(®s->bank_regs[bank].ecc1);
387 ecc[0] = (uint8_t) (ecc_tmp >> 0);
388 ecc[1] = (uint8_t) (ecc_tmp >> 8);
389 ecc[2] = (uint8_t) (ecc_tmp >> 16);
390
391 return 0;
392 }
393
394 /*
395 * fsmc_read_page_hwecc
396 * @mtd: mtd info structure
397 * @chip: nand chip info structure
398 * @buf: buffer to store read data
399 * @page: page number to read
400 *
401 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
402 * performed in a strict sequence as follows:
403 * data(512 byte) -> ecc(13 byte)
404 * After this read, fsmc hardware generates and reports error data bits(up to a
405 * max of 8 bits)
406 */
fsmc_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int page)407 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
408 uint8_t *buf, int page)
409 {
410 struct fsmc_nand_data *host = container_of(mtd,
411 struct fsmc_nand_data, mtd);
412 struct fsmc_eccplace *ecc_place = host->ecc_place;
413 int i, j, s, stat, eccsize = chip->ecc.size;
414 int eccbytes = chip->ecc.bytes;
415 int eccsteps = chip->ecc.steps;
416 uint8_t *p = buf;
417 uint8_t *ecc_calc = chip->buffers->ecccalc;
418 uint8_t *ecc_code = chip->buffers->ecccode;
419 int off, len, group = 0;
420 /*
421 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
422 * end up reading 14 bytes (7 words) from oob. The local array is
423 * to maintain word alignment
424 */
425 uint16_t ecc_oob[7];
426 uint8_t *oob = (uint8_t *)&ecc_oob[0];
427
428 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
429
430 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
431 chip->ecc.hwctl(mtd, NAND_ECC_READ);
432 chip->read_buf(mtd, p, eccsize);
433
434 for (j = 0; j < eccbytes;) {
435 off = ecc_place->eccplace[group].offset;
436 len = ecc_place->eccplace[group].length;
437 group++;
438
439 /*
440 * length is intentionally kept a higher multiple of 2
441 * to read at least 13 bytes even in case of 16 bit NAND
442 * devices
443 */
444 len = roundup(len, 2);
445 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
446 chip->read_buf(mtd, oob + j, len);
447 j += len;
448 }
449
450 memcpy(&ecc_code[i], oob, 13);
451 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
452
453 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
454 if (stat < 0)
455 mtd->ecc_stats.failed++;
456 else
457 mtd->ecc_stats.corrected += stat;
458 }
459
460 return 0;
461 }
462
463 /*
464 * fsmc_correct_data
465 * @mtd: mtd info structure
466 * @dat: buffer of read data
467 * @read_ecc: ecc read from device spare area
468 * @calc_ecc: ecc calculated from read data
469 *
470 * calc_ecc is a 104 bit information containing maximum of 8 error
471 * offset informations of 13 bits each in 512 bytes of read data.
472 */
fsmc_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * read_ecc,uint8_t * calc_ecc)473 static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
474 uint8_t *read_ecc, uint8_t *calc_ecc)
475 {
476 struct fsmc_nand_data *host = container_of(mtd,
477 struct fsmc_nand_data, mtd);
478 struct fsmc_regs *regs = host->regs_va;
479 unsigned int bank = host->bank;
480 uint16_t err_idx[8];
481 uint64_t ecc_data[2];
482 uint32_t num_err, i;
483
484 /* The calculated ecc is actually the correction index in data */
485 memcpy(ecc_data, calc_ecc, 13);
486
487 /*
488 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
489 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
490 *
491 * calc_ecc is a 104 bit information containing maximum of 8 error
492 * offset informations of 13 bits each. calc_ecc is copied into a
493 * uint64_t array and error offset indexes are populated in err_idx
494 * array
495 */
496 for (i = 0; i < 8; i++) {
497 if (i == 4) {
498 err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
499 ecc_data[1] >>= 1;
500 continue;
501 }
502 err_idx[i] = (ecc_data[i/4] & 0x1FFF);
503 ecc_data[i/4] >>= 13;
504 }
505
506 num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF;
507
508 if (num_err == 0xF)
509 return -EBADMSG;
510
511 i = 0;
512 while (num_err--) {
513 change_bit(0, (unsigned long *)&err_idx[i]);
514 change_bit(1, (unsigned long *)&err_idx[i]);
515
516 if (err_idx[i] <= 512 * 8) {
517 change_bit(err_idx[i], (unsigned long *)dat);
518 i++;
519 }
520 }
521 return i;
522 }
523
524 /*
525 * fsmc_nand_probe - Probe function
526 * @pdev: platform device structure
527 */
fsmc_nand_probe(struct platform_device * pdev)528 static int __init fsmc_nand_probe(struct platform_device *pdev)
529 {
530 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
531 struct fsmc_nand_data *host;
532 struct mtd_info *mtd;
533 struct nand_chip *nand;
534 struct fsmc_regs *regs;
535 struct resource *res;
536 int ret = 0;
537 u32 pid;
538 int i;
539
540 if (!pdata) {
541 dev_err(&pdev->dev, "platform data is NULL\n");
542 return -EINVAL;
543 }
544
545 /* Allocate memory for the device structure (and zero it) */
546 host = kzalloc(sizeof(*host), GFP_KERNEL);
547 if (!host) {
548 dev_err(&pdev->dev, "failed to allocate device structure\n");
549 return -ENOMEM;
550 }
551
552 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
553 if (!res) {
554 ret = -EIO;
555 goto err_probe1;
556 }
557
558 host->resdata = request_mem_region(res->start, resource_size(res),
559 pdev->name);
560 if (!host->resdata) {
561 ret = -EIO;
562 goto err_probe1;
563 }
564
565 host->data_va = ioremap(res->start, resource_size(res));
566 if (!host->data_va) {
567 ret = -EIO;
568 goto err_probe1;
569 }
570
571 host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
572 resource_size(res), pdev->name);
573 if (!host->resaddr) {
574 ret = -EIO;
575 goto err_probe1;
576 }
577
578 host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
579 if (!host->addr_va) {
580 ret = -EIO;
581 goto err_probe1;
582 }
583
584 host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
585 resource_size(res), pdev->name);
586 if (!host->rescmd) {
587 ret = -EIO;
588 goto err_probe1;
589 }
590
591 host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
592 if (!host->cmd_va) {
593 ret = -EIO;
594 goto err_probe1;
595 }
596
597 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
598 if (!res) {
599 ret = -EIO;
600 goto err_probe1;
601 }
602
603 host->resregs = request_mem_region(res->start, resource_size(res),
604 pdev->name);
605 if (!host->resregs) {
606 ret = -EIO;
607 goto err_probe1;
608 }
609
610 host->regs_va = ioremap(res->start, resource_size(res));
611 if (!host->regs_va) {
612 ret = -EIO;
613 goto err_probe1;
614 }
615
616 host->clk = clk_get(&pdev->dev, NULL);
617 if (IS_ERR(host->clk)) {
618 dev_err(&pdev->dev, "failed to fetch block clock\n");
619 ret = PTR_ERR(host->clk);
620 host->clk = NULL;
621 goto err_probe1;
622 }
623
624 ret = clk_enable(host->clk);
625 if (ret)
626 goto err_probe1;
627
628 /*
629 * This device ID is actually a common AMBA ID as used on the
630 * AMBA PrimeCell bus. However it is not a PrimeCell.
631 */
632 for (pid = 0, i = 0; i < 4; i++)
633 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
634 host->pid = pid;
635 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
636 "revision %02x, config %02x\n",
637 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
638 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
639
640 host->bank = pdata->bank;
641 host->select_chip = pdata->select_bank;
642 regs = host->regs_va;
643
644 /* Link all private pointers */
645 mtd = &host->mtd;
646 nand = &host->nand;
647 mtd->priv = nand;
648 nand->priv = host;
649
650 host->mtd.owner = THIS_MODULE;
651 nand->IO_ADDR_R = host->data_va;
652 nand->IO_ADDR_W = host->data_va;
653 nand->cmd_ctrl = fsmc_cmd_ctrl;
654 nand->chip_delay = 30;
655
656 nand->ecc.mode = NAND_ECC_HW;
657 nand->ecc.hwctl = fsmc_enable_hwecc;
658 nand->ecc.size = 512;
659 nand->options = pdata->options;
660 nand->select_chip = fsmc_select_chip;
661
662 if (pdata->width == FSMC_NAND_BW16)
663 nand->options |= NAND_BUSWIDTH_16;
664
665 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
666
667 if (AMBA_REV_BITS(host->pid) >= 8) {
668 nand->ecc.read_page = fsmc_read_page_hwecc;
669 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
670 nand->ecc.correct = fsmc_correct_data;
671 nand->ecc.bytes = 13;
672 } else {
673 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
674 nand->ecc.correct = nand_correct_data;
675 nand->ecc.bytes = 3;
676 }
677
678 /*
679 * Scan to find existence of the device
680 */
681 if (nand_scan_ident(&host->mtd, 1, NULL)) {
682 ret = -ENXIO;
683 dev_err(&pdev->dev, "No NAND Device found!\n");
684 goto err_probe;
685 }
686
687 if (AMBA_REV_BITS(host->pid) >= 8) {
688 if (host->mtd.writesize == 512) {
689 nand->ecc.layout = &fsmc_ecc4_sp_layout;
690 host->ecc_place = &fsmc_ecc4_sp_place;
691 } else {
692 nand->ecc.layout = &fsmc_ecc4_lp_layout;
693 host->ecc_place = &fsmc_ecc4_lp_place;
694 }
695 } else {
696 nand->ecc.layout = &fsmc_ecc1_layout;
697 }
698
699 /* Second stage of scan to fill MTD data-structures */
700 if (nand_scan_tail(&host->mtd)) {
701 ret = -ENXIO;
702 goto err_probe;
703 }
704
705 /*
706 * The partition information can is accessed by (in the same precedence)
707 *
708 * command line through Bootloader,
709 * platform data,
710 * default partition information present in driver.
711 */
712 /*
713 * Check for partition info passed
714 */
715 host->mtd.name = "nand";
716 ret = mtd_device_parse_register(&host->mtd, NULL, 0,
717 host->mtd.size <= 0x04000000 ?
718 partition_info_16KB_blk :
719 partition_info_128KB_blk,
720 host->mtd.size <= 0x04000000 ?
721 ARRAY_SIZE(partition_info_16KB_blk) :
722 ARRAY_SIZE(partition_info_128KB_blk));
723 if (ret)
724 goto err_probe;
725
726 platform_set_drvdata(pdev, host);
727 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
728 return 0;
729
730 err_probe:
731 clk_disable(host->clk);
732 err_probe1:
733 if (host->clk)
734 clk_put(host->clk);
735 if (host->regs_va)
736 iounmap(host->regs_va);
737 if (host->resregs)
738 release_mem_region(host->resregs->start,
739 resource_size(host->resregs));
740 if (host->cmd_va)
741 iounmap(host->cmd_va);
742 if (host->rescmd)
743 release_mem_region(host->rescmd->start,
744 resource_size(host->rescmd));
745 if (host->addr_va)
746 iounmap(host->addr_va);
747 if (host->resaddr)
748 release_mem_region(host->resaddr->start,
749 resource_size(host->resaddr));
750 if (host->data_va)
751 iounmap(host->data_va);
752 if (host->resdata)
753 release_mem_region(host->resdata->start,
754 resource_size(host->resdata));
755
756 kfree(host);
757 return ret;
758 }
759
760 /*
761 * Clean up routine
762 */
fsmc_nand_remove(struct platform_device * pdev)763 static int fsmc_nand_remove(struct platform_device *pdev)
764 {
765 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
766
767 platform_set_drvdata(pdev, NULL);
768
769 if (host) {
770 nand_release(&host->mtd);
771 clk_disable(host->clk);
772 clk_put(host->clk);
773
774 iounmap(host->regs_va);
775 release_mem_region(host->resregs->start,
776 resource_size(host->resregs));
777 iounmap(host->cmd_va);
778 release_mem_region(host->rescmd->start,
779 resource_size(host->rescmd));
780 iounmap(host->addr_va);
781 release_mem_region(host->resaddr->start,
782 resource_size(host->resaddr));
783 iounmap(host->data_va);
784 release_mem_region(host->resdata->start,
785 resource_size(host->resdata));
786
787 kfree(host);
788 }
789 return 0;
790 }
791
792 #ifdef CONFIG_PM
fsmc_nand_suspend(struct device * dev)793 static int fsmc_nand_suspend(struct device *dev)
794 {
795 struct fsmc_nand_data *host = dev_get_drvdata(dev);
796 if (host)
797 clk_disable(host->clk);
798 return 0;
799 }
800
fsmc_nand_resume(struct device * dev)801 static int fsmc_nand_resume(struct device *dev)
802 {
803 struct fsmc_nand_data *host = dev_get_drvdata(dev);
804 if (host)
805 clk_enable(host->clk);
806 return 0;
807 }
808
809 static const struct dev_pm_ops fsmc_nand_pm_ops = {
810 .suspend = fsmc_nand_suspend,
811 .resume = fsmc_nand_resume,
812 };
813 #endif
814
815 static struct platform_driver fsmc_nand_driver = {
816 .remove = fsmc_nand_remove,
817 .driver = {
818 .owner = THIS_MODULE,
819 .name = "fsmc-nand",
820 #ifdef CONFIG_PM
821 .pm = &fsmc_nand_pm_ops,
822 #endif
823 },
824 };
825
fsmc_nand_init(void)826 static int __init fsmc_nand_init(void)
827 {
828 return platform_driver_probe(&fsmc_nand_driver,
829 fsmc_nand_probe);
830 }
831 module_init(fsmc_nand_init);
832
fsmc_nand_exit(void)833 static void __exit fsmc_nand_exit(void)
834 {
835 platform_driver_unregister(&fsmc_nand_driver);
836 }
837 module_exit(fsmc_nand_exit);
838
839 MODULE_LICENSE("GPL");
840 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
841 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
842