1 /*
2 * Copyright (C) 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 *
23 */
24
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
33
34 #include <linux/dmaengine.h>
35 #include <linux/gpio.h>
36 #include <linux/io.h>
37
38 #include <mach/board.h>
39 #include <mach/cpu.h>
40
41 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
42 #define hard_ecc 1
43 #else
44 #define hard_ecc 0
45 #endif
46
47 #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
48 #define no_ecc 1
49 #else
50 #define no_ecc 0
51 #endif
52
53 static int use_dma = 1;
54 module_param(use_dma, int, 0);
55
56 static int on_flash_bbt = 0;
57 module_param(on_flash_bbt, int, 0);
58
59 /* Register access macros */
60 #define ecc_readl(add, reg) \
61 __raw_readl(add + ATMEL_ECC_##reg)
62 #define ecc_writel(add, reg, value) \
63 __raw_writel((value), add + ATMEL_ECC_##reg)
64
65 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
66
67 /* oob layout for large page size
68 * bad block info is on bytes 0 and 1
69 * the bytes have to be consecutives to avoid
70 * several NAND_CMD_RNDOUT during read
71 */
72 static struct nand_ecclayout atmel_oobinfo_large = {
73 .eccbytes = 4,
74 .eccpos = {60, 61, 62, 63},
75 .oobfree = {
76 {2, 58}
77 },
78 };
79
80 /* oob layout for small page size
81 * bad block info is on bytes 4 and 5
82 * the bytes have to be consecutives to avoid
83 * several NAND_CMD_RNDOUT during read
84 */
85 static struct nand_ecclayout atmel_oobinfo_small = {
86 .eccbytes = 4,
87 .eccpos = {0, 1, 2, 3},
88 .oobfree = {
89 {6, 10}
90 },
91 };
92
93 struct atmel_nand_host {
94 struct nand_chip nand_chip;
95 struct mtd_info mtd;
96 void __iomem *io_base;
97 dma_addr_t io_phys;
98 struct atmel_nand_data *board;
99 struct device *dev;
100 void __iomem *ecc;
101
102 struct completion comp;
103 struct dma_chan *dma_chan;
104 };
105
cpu_has_dma(void)106 static int cpu_has_dma(void)
107 {
108 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
109 }
110
111 /*
112 * Enable NAND.
113 */
atmel_nand_enable(struct atmel_nand_host * host)114 static void atmel_nand_enable(struct atmel_nand_host *host)
115 {
116 if (gpio_is_valid(host->board->enable_pin))
117 gpio_set_value(host->board->enable_pin, 0);
118 }
119
120 /*
121 * Disable NAND.
122 */
atmel_nand_disable(struct atmel_nand_host * host)123 static void atmel_nand_disable(struct atmel_nand_host *host)
124 {
125 if (gpio_is_valid(host->board->enable_pin))
126 gpio_set_value(host->board->enable_pin, 1);
127 }
128
129 /*
130 * Hardware specific access to control-lines
131 */
atmel_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)132 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
133 {
134 struct nand_chip *nand_chip = mtd->priv;
135 struct atmel_nand_host *host = nand_chip->priv;
136
137 if (ctrl & NAND_CTRL_CHANGE) {
138 if (ctrl & NAND_NCE)
139 atmel_nand_enable(host);
140 else
141 atmel_nand_disable(host);
142 }
143 if (cmd == NAND_CMD_NONE)
144 return;
145
146 if (ctrl & NAND_CLE)
147 writeb(cmd, host->io_base + (1 << host->board->cle));
148 else
149 writeb(cmd, host->io_base + (1 << host->board->ale));
150 }
151
152 /*
153 * Read the Device Ready pin.
154 */
atmel_nand_device_ready(struct mtd_info * mtd)155 static int atmel_nand_device_ready(struct mtd_info *mtd)
156 {
157 struct nand_chip *nand_chip = mtd->priv;
158 struct atmel_nand_host *host = nand_chip->priv;
159
160 return gpio_get_value(host->board->rdy_pin) ^
161 !!host->board->rdy_pin_active_low;
162 }
163
164 /*
165 * Minimal-overhead PIO for data access.
166 */
atmel_read_buf8(struct mtd_info * mtd,u8 * buf,int len)167 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
168 {
169 struct nand_chip *nand_chip = mtd->priv;
170
171 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
172 }
173
atmel_read_buf16(struct mtd_info * mtd,u8 * buf,int len)174 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
175 {
176 struct nand_chip *nand_chip = mtd->priv;
177
178 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
179 }
180
atmel_write_buf8(struct mtd_info * mtd,const u8 * buf,int len)181 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
182 {
183 struct nand_chip *nand_chip = mtd->priv;
184
185 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
186 }
187
atmel_write_buf16(struct mtd_info * mtd,const u8 * buf,int len)188 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
189 {
190 struct nand_chip *nand_chip = mtd->priv;
191
192 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
193 }
194
dma_complete_func(void * completion)195 static void dma_complete_func(void *completion)
196 {
197 complete(completion);
198 }
199
atmel_nand_dma_op(struct mtd_info * mtd,void * buf,int len,int is_read)200 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
201 int is_read)
202 {
203 struct dma_device *dma_dev;
204 enum dma_ctrl_flags flags;
205 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
206 struct dma_async_tx_descriptor *tx = NULL;
207 dma_cookie_t cookie;
208 struct nand_chip *chip = mtd->priv;
209 struct atmel_nand_host *host = chip->priv;
210 void *p = buf;
211 int err = -EIO;
212 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
213
214 if (buf >= high_memory)
215 goto err_buf;
216
217 dma_dev = host->dma_chan->device;
218
219 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
220 DMA_COMPL_SKIP_DEST_UNMAP;
221
222 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
223 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
224 dev_err(host->dev, "Failed to dma_map_single\n");
225 goto err_buf;
226 }
227
228 if (is_read) {
229 dma_src_addr = host->io_phys;
230 dma_dst_addr = phys_addr;
231 } else {
232 dma_src_addr = phys_addr;
233 dma_dst_addr = host->io_phys;
234 }
235
236 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
237 dma_src_addr, len, flags);
238 if (!tx) {
239 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
240 goto err_dma;
241 }
242
243 init_completion(&host->comp);
244 tx->callback = dma_complete_func;
245 tx->callback_param = &host->comp;
246
247 cookie = tx->tx_submit(tx);
248 if (dma_submit_error(cookie)) {
249 dev_err(host->dev, "Failed to do DMA tx_submit\n");
250 goto err_dma;
251 }
252
253 dma_async_issue_pending(host->dma_chan);
254 wait_for_completion(&host->comp);
255
256 err = 0;
257
258 err_dma:
259 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
260 err_buf:
261 if (err != 0)
262 dev_warn(host->dev, "Fall back to CPU I/O\n");
263 return err;
264 }
265
atmel_read_buf(struct mtd_info * mtd,u8 * buf,int len)266 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
267 {
268 struct nand_chip *chip = mtd->priv;
269 struct atmel_nand_host *host = chip->priv;
270
271 if (use_dma && len > mtd->oobsize)
272 /* only use DMA for bigger than oob size: better performances */
273 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
274 return;
275
276 if (host->board->bus_width_16)
277 atmel_read_buf16(mtd, buf, len);
278 else
279 atmel_read_buf8(mtd, buf, len);
280 }
281
atmel_write_buf(struct mtd_info * mtd,const u8 * buf,int len)282 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
283 {
284 struct nand_chip *chip = mtd->priv;
285 struct atmel_nand_host *host = chip->priv;
286
287 if (use_dma && len > mtd->oobsize)
288 /* only use DMA for bigger than oob size: better performances */
289 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
290 return;
291
292 if (host->board->bus_width_16)
293 atmel_write_buf16(mtd, buf, len);
294 else
295 atmel_write_buf8(mtd, buf, len);
296 }
297
298 /*
299 * Calculate HW ECC
300 *
301 * function called after a write
302 *
303 * mtd: MTD block structure
304 * dat: raw data (unused)
305 * ecc_code: buffer for ECC
306 */
atmel_nand_calculate(struct mtd_info * mtd,const u_char * dat,unsigned char * ecc_code)307 static int atmel_nand_calculate(struct mtd_info *mtd,
308 const u_char *dat, unsigned char *ecc_code)
309 {
310 struct nand_chip *nand_chip = mtd->priv;
311 struct atmel_nand_host *host = nand_chip->priv;
312 unsigned int ecc_value;
313
314 /* get the first 2 ECC bytes */
315 ecc_value = ecc_readl(host->ecc, PR);
316
317 ecc_code[0] = ecc_value & 0xFF;
318 ecc_code[1] = (ecc_value >> 8) & 0xFF;
319
320 /* get the last 2 ECC bytes */
321 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
322
323 ecc_code[2] = ecc_value & 0xFF;
324 ecc_code[3] = (ecc_value >> 8) & 0xFF;
325
326 return 0;
327 }
328
329 /*
330 * HW ECC read page function
331 *
332 * mtd: mtd info structure
333 * chip: nand chip info structure
334 * buf: buffer to store read data
335 */
atmel_nand_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int page)336 static int atmel_nand_read_page(struct mtd_info *mtd,
337 struct nand_chip *chip, uint8_t *buf, int page)
338 {
339 int eccsize = chip->ecc.size;
340 int eccbytes = chip->ecc.bytes;
341 uint32_t *eccpos = chip->ecc.layout->eccpos;
342 uint8_t *p = buf;
343 uint8_t *oob = chip->oob_poi;
344 uint8_t *ecc_pos;
345 int stat;
346
347 /*
348 * Errata: ALE is incorrectly wired up to the ECC controller
349 * on the AP7000, so it will include the address cycles in the
350 * ECC calculation.
351 *
352 * Workaround: Reset the parity registers before reading the
353 * actual data.
354 */
355 if (cpu_is_at32ap7000()) {
356 struct atmel_nand_host *host = chip->priv;
357 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
358 }
359
360 /* read the page */
361 chip->read_buf(mtd, p, eccsize);
362
363 /* move to ECC position if needed */
364 if (eccpos[0] != 0) {
365 /* This only works on large pages
366 * because the ECC controller waits for
367 * NAND_CMD_RNDOUTSTART after the
368 * NAND_CMD_RNDOUT.
369 * anyway, for small pages, the eccpos[0] == 0
370 */
371 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
372 mtd->writesize + eccpos[0], -1);
373 }
374
375 /* the ECC controller needs to read the ECC just after the data */
376 ecc_pos = oob + eccpos[0];
377 chip->read_buf(mtd, ecc_pos, eccbytes);
378
379 /* check if there's an error */
380 stat = chip->ecc.correct(mtd, p, oob, NULL);
381
382 if (stat < 0)
383 mtd->ecc_stats.failed++;
384 else
385 mtd->ecc_stats.corrected += stat;
386
387 /* get back to oob start (end of page) */
388 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
389
390 /* read the oob */
391 chip->read_buf(mtd, oob, mtd->oobsize);
392
393 return 0;
394 }
395
396 /*
397 * HW ECC Correction
398 *
399 * function called after a read
400 *
401 * mtd: MTD block structure
402 * dat: raw data read from the chip
403 * read_ecc: ECC from the chip (unused)
404 * isnull: unused
405 *
406 * Detect and correct a 1 bit error for a page
407 */
atmel_nand_correct(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * isnull)408 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
409 u_char *read_ecc, u_char *isnull)
410 {
411 struct nand_chip *nand_chip = mtd->priv;
412 struct atmel_nand_host *host = nand_chip->priv;
413 unsigned int ecc_status;
414 unsigned int ecc_word, ecc_bit;
415
416 /* get the status from the Status Register */
417 ecc_status = ecc_readl(host->ecc, SR);
418
419 /* if there's no error */
420 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
421 return 0;
422
423 /* get error bit offset (4 bits) */
424 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
425 /* get word address (12 bits) */
426 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
427 ecc_word >>= 4;
428
429 /* if there are multiple errors */
430 if (ecc_status & ATMEL_ECC_MULERR) {
431 /* check if it is a freshly erased block
432 * (filled with 0xff) */
433 if ((ecc_bit == ATMEL_ECC_BITADDR)
434 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
435 /* the block has just been erased, return OK */
436 return 0;
437 }
438 /* it doesn't seems to be a freshly
439 * erased block.
440 * We can't correct so many errors */
441 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
442 " Unable to correct.\n");
443 return -EIO;
444 }
445
446 /* if there's a single bit error : we can correct it */
447 if (ecc_status & ATMEL_ECC_ECCERR) {
448 /* there's nothing much to do here.
449 * the bit error is on the ECC itself.
450 */
451 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
452 " Nothing to correct\n");
453 return 0;
454 }
455
456 dev_dbg(host->dev, "atmel_nand : one bit error on data."
457 " (word offset in the page :"
458 " 0x%x bit offset : 0x%x)\n",
459 ecc_word, ecc_bit);
460 /* correct the error */
461 if (nand_chip->options & NAND_BUSWIDTH_16) {
462 /* 16 bits words */
463 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
464 } else {
465 /* 8 bits words */
466 dat[ecc_word] ^= (1 << ecc_bit);
467 }
468 dev_dbg(host->dev, "atmel_nand : error corrected\n");
469 return 1;
470 }
471
472 /*
473 * Enable HW ECC : unused on most chips
474 */
atmel_nand_hwctl(struct mtd_info * mtd,int mode)475 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
476 {
477 if (cpu_is_at32ap7000()) {
478 struct nand_chip *nand_chip = mtd->priv;
479 struct atmel_nand_host *host = nand_chip->priv;
480 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
481 }
482 }
483
484 /*
485 * Probe for the NAND device.
486 */
atmel_nand_probe(struct platform_device * pdev)487 static int __init atmel_nand_probe(struct platform_device *pdev)
488 {
489 struct atmel_nand_host *host;
490 struct mtd_info *mtd;
491 struct nand_chip *nand_chip;
492 struct resource *regs;
493 struct resource *mem;
494 int res;
495
496 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 if (!mem) {
498 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
499 return -ENXIO;
500 }
501
502 /* Allocate memory for the device structure (and zero it) */
503 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
504 if (!host) {
505 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
506 return -ENOMEM;
507 }
508
509 host->io_phys = (dma_addr_t)mem->start;
510
511 host->io_base = ioremap(mem->start, resource_size(mem));
512 if (host->io_base == NULL) {
513 printk(KERN_ERR "atmel_nand: ioremap failed\n");
514 res = -EIO;
515 goto err_nand_ioremap;
516 }
517
518 mtd = &host->mtd;
519 nand_chip = &host->nand_chip;
520 host->board = pdev->dev.platform_data;
521 host->dev = &pdev->dev;
522
523 nand_chip->priv = host; /* link the private data structures */
524 mtd->priv = nand_chip;
525 mtd->owner = THIS_MODULE;
526
527 /* Set address of NAND IO lines */
528 nand_chip->IO_ADDR_R = host->io_base;
529 nand_chip->IO_ADDR_W = host->io_base;
530 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
531
532 if (gpio_is_valid(host->board->rdy_pin))
533 nand_chip->dev_ready = atmel_nand_device_ready;
534
535 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
536 if (!regs && hard_ecc) {
537 printk(KERN_ERR "atmel_nand: can't get I/O resource "
538 "regs\nFalling back on software ECC\n");
539 }
540
541 nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
542 if (no_ecc)
543 nand_chip->ecc.mode = NAND_ECC_NONE;
544 if (hard_ecc && regs) {
545 host->ecc = ioremap(regs->start, resource_size(regs));
546 if (host->ecc == NULL) {
547 printk(KERN_ERR "atmel_nand: ioremap failed\n");
548 res = -EIO;
549 goto err_ecc_ioremap;
550 }
551 nand_chip->ecc.mode = NAND_ECC_HW;
552 nand_chip->ecc.calculate = atmel_nand_calculate;
553 nand_chip->ecc.correct = atmel_nand_correct;
554 nand_chip->ecc.hwctl = atmel_nand_hwctl;
555 nand_chip->ecc.read_page = atmel_nand_read_page;
556 nand_chip->ecc.bytes = 4;
557 }
558
559 nand_chip->chip_delay = 20; /* 20us command delay time */
560
561 if (host->board->bus_width_16) /* 16-bit bus width */
562 nand_chip->options |= NAND_BUSWIDTH_16;
563
564 nand_chip->read_buf = atmel_read_buf;
565 nand_chip->write_buf = atmel_write_buf;
566
567 platform_set_drvdata(pdev, host);
568 atmel_nand_enable(host);
569
570 if (gpio_is_valid(host->board->det_pin)) {
571 if (gpio_get_value(host->board->det_pin)) {
572 printk(KERN_INFO "No SmartMedia card inserted.\n");
573 res = -ENXIO;
574 goto err_no_card;
575 }
576 }
577
578 if (on_flash_bbt) {
579 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
580 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
581 }
582
583 if (!cpu_has_dma())
584 use_dma = 0;
585
586 if (use_dma) {
587 dma_cap_mask_t mask;
588
589 dma_cap_zero(mask);
590 dma_cap_set(DMA_MEMCPY, mask);
591 host->dma_chan = dma_request_channel(mask, NULL, NULL);
592 if (!host->dma_chan) {
593 dev_err(host->dev, "Failed to request DMA channel\n");
594 use_dma = 0;
595 }
596 }
597 if (use_dma)
598 dev_info(host->dev, "Using %s for DMA transfers.\n",
599 dma_chan_name(host->dma_chan));
600 else
601 dev_info(host->dev, "No DMA support for NAND access.\n");
602
603 /* first scan to find the device and get the page size */
604 if (nand_scan_ident(mtd, 1, NULL)) {
605 res = -ENXIO;
606 goto err_scan_ident;
607 }
608
609 if (nand_chip->ecc.mode == NAND_ECC_HW) {
610 /* ECC is calculated for the whole page (1 step) */
611 nand_chip->ecc.size = mtd->writesize;
612
613 /* set ECC page size and oob layout */
614 switch (mtd->writesize) {
615 case 512:
616 nand_chip->ecc.layout = &atmel_oobinfo_small;
617 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
618 break;
619 case 1024:
620 nand_chip->ecc.layout = &atmel_oobinfo_large;
621 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
622 break;
623 case 2048:
624 nand_chip->ecc.layout = &atmel_oobinfo_large;
625 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
626 break;
627 case 4096:
628 nand_chip->ecc.layout = &atmel_oobinfo_large;
629 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
630 break;
631 default:
632 /* page size not handled by HW ECC */
633 /* switching back to soft ECC */
634 nand_chip->ecc.mode = NAND_ECC_SOFT;
635 nand_chip->ecc.calculate = NULL;
636 nand_chip->ecc.correct = NULL;
637 nand_chip->ecc.hwctl = NULL;
638 nand_chip->ecc.read_page = NULL;
639 nand_chip->ecc.postpad = 0;
640 nand_chip->ecc.prepad = 0;
641 nand_chip->ecc.bytes = 0;
642 break;
643 }
644 }
645
646 /* second phase scan */
647 if (nand_scan_tail(mtd)) {
648 res = -ENXIO;
649 goto err_scan_tail;
650 }
651
652 mtd->name = "atmel_nand";
653 res = mtd_device_parse_register(mtd, NULL, 0,
654 host->board->parts, host->board->num_parts);
655 if (!res)
656 return res;
657
658 err_scan_tail:
659 err_scan_ident:
660 err_no_card:
661 atmel_nand_disable(host);
662 platform_set_drvdata(pdev, NULL);
663 if (host->dma_chan)
664 dma_release_channel(host->dma_chan);
665 if (host->ecc)
666 iounmap(host->ecc);
667 err_ecc_ioremap:
668 iounmap(host->io_base);
669 err_nand_ioremap:
670 kfree(host);
671 return res;
672 }
673
674 /*
675 * Remove a NAND device.
676 */
atmel_nand_remove(struct platform_device * pdev)677 static int __exit atmel_nand_remove(struct platform_device *pdev)
678 {
679 struct atmel_nand_host *host = platform_get_drvdata(pdev);
680 struct mtd_info *mtd = &host->mtd;
681
682 nand_release(mtd);
683
684 atmel_nand_disable(host);
685
686 if (host->ecc)
687 iounmap(host->ecc);
688
689 if (host->dma_chan)
690 dma_release_channel(host->dma_chan);
691
692 iounmap(host->io_base);
693 kfree(host);
694
695 return 0;
696 }
697
698 static struct platform_driver atmel_nand_driver = {
699 .remove = __exit_p(atmel_nand_remove),
700 .driver = {
701 .name = "atmel_nand",
702 .owner = THIS_MODULE,
703 },
704 };
705
atmel_nand_init(void)706 static int __init atmel_nand_init(void)
707 {
708 return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
709 }
710
711
atmel_nand_exit(void)712 static void __exit atmel_nand_exit(void)
713 {
714 platform_driver_unregister(&atmel_nand_driver);
715 }
716
717
718 module_init(atmel_nand_init);
719 module_exit(atmel_nand_exit);
720
721 MODULE_LICENSE("GPL");
722 MODULE_AUTHOR("Rick Bronson");
723 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
724 MODULE_ALIAS("platform:atmel_nand");
725