1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
47 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
48 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
49 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
50
51 /* Used for SST flashes only. */
52 #define OPCODE_BP 0x02 /* Byte program */
53 #define OPCODE_WRDI 0x04 /* Write disable */
54 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
55
56 /* Used for Macronix flashes only. */
57 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
58 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
59
60 /* Used for Spansion flashes only. */
61 #define OPCODE_BRWR 0x17 /* Bank register write */
62
63 /* Status Register bits. */
64 #define SR_WIP 1 /* Write in progress */
65 #define SR_WEL 2 /* Write enable latch */
66 /* meaning of other SR_* bits may differ between vendors */
67 #define SR_BP0 4 /* Block protect 0 */
68 #define SR_BP1 8 /* Block protect 1 */
69 #define SR_BP2 0x10 /* Block protect 2 */
70 #define SR_SRWD 0x80 /* SR write protect */
71
72 /* Define max times to check status register before we give up. */
73 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
74 #define MAX_CMD_SIZE 5
75
76 #ifdef CONFIG_M25PXX_USE_FAST_READ
77 #define OPCODE_READ OPCODE_FAST_READ
78 #define FAST_READ_DUMMY_BYTE 1
79 #else
80 #define OPCODE_READ OPCODE_NORM_READ
81 #define FAST_READ_DUMMY_BYTE 0
82 #endif
83
84 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
85
86 /****************************************************************************/
87
88 struct m25p {
89 struct spi_device *spi;
90 struct mutex lock;
91 struct mtd_info mtd;
92 u16 page_size;
93 u16 addr_width;
94 u8 erase_opcode;
95 u8 *command;
96 };
97
mtd_to_m25p(struct mtd_info * mtd)98 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
99 {
100 return container_of(mtd, struct m25p, mtd);
101 }
102
103 /****************************************************************************/
104
105 /*
106 * Internal helper functions
107 */
108
109 /*
110 * Read the status register, returning its value in the location
111 * Return the status register value.
112 * Returns negative if error occurred.
113 */
read_sr(struct m25p * flash)114 static int read_sr(struct m25p *flash)
115 {
116 ssize_t retval;
117 u8 code = OPCODE_RDSR;
118 u8 val;
119
120 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
121
122 if (retval < 0) {
123 dev_err(&flash->spi->dev, "error %d reading SR\n",
124 (int) retval);
125 return retval;
126 }
127
128 return val;
129 }
130
131 /*
132 * Write status register 1 byte
133 * Returns negative if error occurred.
134 */
write_sr(struct m25p * flash,u8 val)135 static int write_sr(struct m25p *flash, u8 val)
136 {
137 flash->command[0] = OPCODE_WRSR;
138 flash->command[1] = val;
139
140 return spi_write(flash->spi, flash->command, 2);
141 }
142
143 /*
144 * Set write enable latch with Write Enable command.
145 * Returns negative if error occurred.
146 */
write_enable(struct m25p * flash)147 static inline int write_enable(struct m25p *flash)
148 {
149 u8 code = OPCODE_WREN;
150
151 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
152 }
153
154 /*
155 * Send write disble instruction to the chip.
156 */
write_disable(struct m25p * flash)157 static inline int write_disable(struct m25p *flash)
158 {
159 u8 code = OPCODE_WRDI;
160
161 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
162 }
163
164 /*
165 * Enable/disable 4-byte addressing mode.
166 */
set_4byte(struct m25p * flash,u32 jedec_id,int enable)167 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
168 {
169 switch (JEDEC_MFR(jedec_id)) {
170 case CFI_MFR_MACRONIX:
171 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
172 return spi_write(flash->spi, flash->command, 1);
173 default:
174 /* Spansion style */
175 flash->command[0] = OPCODE_BRWR;
176 flash->command[1] = enable << 7;
177 return spi_write(flash->spi, flash->command, 2);
178 }
179 }
180
181 /*
182 * Service routine to read status register until ready, or timeout occurs.
183 * Returns non-zero if error.
184 */
wait_till_ready(struct m25p * flash)185 static int wait_till_ready(struct m25p *flash)
186 {
187 unsigned long deadline;
188 int sr;
189
190 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
191
192 do {
193 if ((sr = read_sr(flash)) < 0)
194 break;
195 else if (!(sr & SR_WIP))
196 return 0;
197
198 cond_resched();
199
200 } while (!time_after_eq(jiffies, deadline));
201
202 return 1;
203 }
204
205 /*
206 * Erase the whole flash memory
207 *
208 * Returns 0 if successful, non-zero otherwise.
209 */
erase_chip(struct m25p * flash)210 static int erase_chip(struct m25p *flash)
211 {
212 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
213 (long long)(flash->mtd.size >> 10));
214
215 /* Wait until finished previous write command. */
216 if (wait_till_ready(flash))
217 return 1;
218
219 /* Send write enable, then erase commands. */
220 write_enable(flash);
221
222 /* Set up command buffer. */
223 flash->command[0] = OPCODE_CHIP_ERASE;
224
225 spi_write(flash->spi, flash->command, 1);
226
227 return 0;
228 }
229
m25p_addr2cmd(struct m25p * flash,unsigned int addr,u8 * cmd)230 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
231 {
232 /* opcode is in cmd[0] */
233 cmd[1] = addr >> (flash->addr_width * 8 - 8);
234 cmd[2] = addr >> (flash->addr_width * 8 - 16);
235 cmd[3] = addr >> (flash->addr_width * 8 - 24);
236 cmd[4] = addr >> (flash->addr_width * 8 - 32);
237 }
238
m25p_cmdsz(struct m25p * flash)239 static int m25p_cmdsz(struct m25p *flash)
240 {
241 return 1 + flash->addr_width;
242 }
243
244 /*
245 * Erase one sector of flash memory at offset ``offset'' which is any
246 * address within the sector which should be erased.
247 *
248 * Returns 0 if successful, non-zero otherwise.
249 */
erase_sector(struct m25p * flash,u32 offset)250 static int erase_sector(struct m25p *flash, u32 offset)
251 {
252 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
253 __func__, flash->mtd.erasesize / 1024, offset);
254
255 /* Wait until finished previous write command. */
256 if (wait_till_ready(flash))
257 return 1;
258
259 /* Send write enable, then erase commands. */
260 write_enable(flash);
261
262 /* Set up command buffer. */
263 flash->command[0] = flash->erase_opcode;
264 m25p_addr2cmd(flash, offset, flash->command);
265
266 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
267
268 return 0;
269 }
270
271 /****************************************************************************/
272
273 /*
274 * MTD implementation
275 */
276
277 /*
278 * Erase an address range on the flash chip. The address range may extend
279 * one or more erase sectors. Return an error is there is a problem erasing.
280 */
m25p80_erase(struct mtd_info * mtd,struct erase_info * instr)281 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
282 {
283 struct m25p *flash = mtd_to_m25p(mtd);
284 u32 addr,len;
285 uint32_t rem;
286
287 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
288 __func__, (long long)instr->addr,
289 (long long)instr->len);
290
291 /* sanity checks */
292 if (instr->addr + instr->len > flash->mtd.size)
293 return -EINVAL;
294 div_u64_rem(instr->len, mtd->erasesize, &rem);
295 if (rem)
296 return -EINVAL;
297
298 addr = instr->addr;
299 len = instr->len;
300
301 mutex_lock(&flash->lock);
302
303 /* whole-chip erase? */
304 if (len == flash->mtd.size) {
305 if (erase_chip(flash)) {
306 instr->state = MTD_ERASE_FAILED;
307 mutex_unlock(&flash->lock);
308 return -EIO;
309 }
310
311 /* REVISIT in some cases we could speed up erasing large regions
312 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
313 * to use "small sector erase", but that's not always optimal.
314 */
315
316 /* "sector"-at-a-time erase */
317 } else {
318 while (len) {
319 if (erase_sector(flash, addr)) {
320 instr->state = MTD_ERASE_FAILED;
321 mutex_unlock(&flash->lock);
322 return -EIO;
323 }
324
325 addr += mtd->erasesize;
326 len -= mtd->erasesize;
327 }
328 }
329
330 mutex_unlock(&flash->lock);
331
332 instr->state = MTD_ERASE_DONE;
333 mtd_erase_callback(instr);
334
335 return 0;
336 }
337
338 /*
339 * Read an address range from the flash chip. The address range
340 * may be any size provided it is within the physical boundaries.
341 */
m25p80_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)342 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
343 size_t *retlen, u_char *buf)
344 {
345 struct m25p *flash = mtd_to_m25p(mtd);
346 struct spi_transfer t[2];
347 struct spi_message m;
348
349 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
350 __func__, (u32)from, len);
351
352 /* sanity checks */
353 if (!len)
354 return 0;
355
356 if (from + len > flash->mtd.size)
357 return -EINVAL;
358
359 spi_message_init(&m);
360 memset(t, 0, (sizeof t));
361
362 /* NOTE:
363 * OPCODE_FAST_READ (if available) is faster.
364 * Should add 1 byte DUMMY_BYTE.
365 */
366 t[0].tx_buf = flash->command;
367 t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
368 spi_message_add_tail(&t[0], &m);
369
370 t[1].rx_buf = buf;
371 t[1].len = len;
372 spi_message_add_tail(&t[1], &m);
373
374 /* Byte count starts at zero. */
375 *retlen = 0;
376
377 mutex_lock(&flash->lock);
378
379 /* Wait till previous write/erase is done. */
380 if (wait_till_ready(flash)) {
381 /* REVISIT status return?? */
382 mutex_unlock(&flash->lock);
383 return 1;
384 }
385
386 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
387 * clocks; and at this writing, every chip this driver handles
388 * supports that opcode.
389 */
390
391 /* Set up the write data buffer. */
392 flash->command[0] = OPCODE_READ;
393 m25p_addr2cmd(flash, from, flash->command);
394
395 spi_sync(flash->spi, &m);
396
397 *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
398
399 mutex_unlock(&flash->lock);
400
401 return 0;
402 }
403
404 /*
405 * Write an address range to the flash chip. Data must be written in
406 * FLASH_PAGESIZE chunks. The address range may be any size provided
407 * it is within the physical boundaries.
408 */
m25p80_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)409 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
410 size_t *retlen, const u_char *buf)
411 {
412 struct m25p *flash = mtd_to_m25p(mtd);
413 u32 page_offset, page_size;
414 struct spi_transfer t[2];
415 struct spi_message m;
416
417 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
418 __func__, (u32)to, len);
419
420 *retlen = 0;
421
422 /* sanity checks */
423 if (!len)
424 return(0);
425
426 if (to + len > flash->mtd.size)
427 return -EINVAL;
428
429 spi_message_init(&m);
430 memset(t, 0, (sizeof t));
431
432 t[0].tx_buf = flash->command;
433 t[0].len = m25p_cmdsz(flash);
434 spi_message_add_tail(&t[0], &m);
435
436 t[1].tx_buf = buf;
437 spi_message_add_tail(&t[1], &m);
438
439 mutex_lock(&flash->lock);
440
441 /* Wait until finished previous write command. */
442 if (wait_till_ready(flash)) {
443 mutex_unlock(&flash->lock);
444 return 1;
445 }
446
447 write_enable(flash);
448
449 /* Set up the opcode in the write buffer. */
450 flash->command[0] = OPCODE_PP;
451 m25p_addr2cmd(flash, to, flash->command);
452
453 page_offset = to & (flash->page_size - 1);
454
455 /* do all the bytes fit onto one page? */
456 if (page_offset + len <= flash->page_size) {
457 t[1].len = len;
458
459 spi_sync(flash->spi, &m);
460
461 *retlen = m.actual_length - m25p_cmdsz(flash);
462 } else {
463 u32 i;
464
465 /* the size of data remaining on the first page */
466 page_size = flash->page_size - page_offset;
467
468 t[1].len = page_size;
469 spi_sync(flash->spi, &m);
470
471 *retlen = m.actual_length - m25p_cmdsz(flash);
472
473 /* write everything in flash->page_size chunks */
474 for (i = page_size; i < len; i += page_size) {
475 page_size = len - i;
476 if (page_size > flash->page_size)
477 page_size = flash->page_size;
478
479 /* write the next page to flash */
480 m25p_addr2cmd(flash, to + i, flash->command);
481
482 t[1].tx_buf = buf + i;
483 t[1].len = page_size;
484
485 wait_till_ready(flash);
486
487 write_enable(flash);
488
489 spi_sync(flash->spi, &m);
490
491 *retlen += m.actual_length - m25p_cmdsz(flash);
492 }
493 }
494
495 mutex_unlock(&flash->lock);
496
497 return 0;
498 }
499
sst_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)500 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
501 size_t *retlen, const u_char *buf)
502 {
503 struct m25p *flash = mtd_to_m25p(mtd);
504 struct spi_transfer t[2];
505 struct spi_message m;
506 size_t actual;
507 int cmd_sz, ret;
508
509 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
510 __func__, (u32)to, len);
511
512 *retlen = 0;
513
514 /* sanity checks */
515 if (!len)
516 return 0;
517
518 if (to + len > flash->mtd.size)
519 return -EINVAL;
520
521 spi_message_init(&m);
522 memset(t, 0, (sizeof t));
523
524 t[0].tx_buf = flash->command;
525 t[0].len = m25p_cmdsz(flash);
526 spi_message_add_tail(&t[0], &m);
527
528 t[1].tx_buf = buf;
529 spi_message_add_tail(&t[1], &m);
530
531 mutex_lock(&flash->lock);
532
533 /* Wait until finished previous write command. */
534 ret = wait_till_ready(flash);
535 if (ret)
536 goto time_out;
537
538 write_enable(flash);
539
540 actual = to % 2;
541 /* Start write from odd address. */
542 if (actual) {
543 flash->command[0] = OPCODE_BP;
544 m25p_addr2cmd(flash, to, flash->command);
545
546 /* write one byte. */
547 t[1].len = 1;
548 spi_sync(flash->spi, &m);
549 ret = wait_till_ready(flash);
550 if (ret)
551 goto time_out;
552 *retlen += m.actual_length - m25p_cmdsz(flash);
553 }
554 to += actual;
555
556 flash->command[0] = OPCODE_AAI_WP;
557 m25p_addr2cmd(flash, to, flash->command);
558
559 /* Write out most of the data here. */
560 cmd_sz = m25p_cmdsz(flash);
561 for (; actual < len - 1; actual += 2) {
562 t[0].len = cmd_sz;
563 /* write two bytes. */
564 t[1].len = 2;
565 t[1].tx_buf = buf + actual;
566
567 spi_sync(flash->spi, &m);
568 ret = wait_till_ready(flash);
569 if (ret)
570 goto time_out;
571 *retlen += m.actual_length - cmd_sz;
572 cmd_sz = 1;
573 to += 2;
574 }
575 write_disable(flash);
576 ret = wait_till_ready(flash);
577 if (ret)
578 goto time_out;
579
580 /* Write out trailing byte if it exists. */
581 if (actual != len) {
582 write_enable(flash);
583 flash->command[0] = OPCODE_BP;
584 m25p_addr2cmd(flash, to, flash->command);
585 t[0].len = m25p_cmdsz(flash);
586 t[1].len = 1;
587 t[1].tx_buf = buf + actual;
588
589 spi_sync(flash->spi, &m);
590 ret = wait_till_ready(flash);
591 if (ret)
592 goto time_out;
593 *retlen += m.actual_length - m25p_cmdsz(flash);
594 write_disable(flash);
595 }
596
597 time_out:
598 mutex_unlock(&flash->lock);
599 return ret;
600 }
601
602 /****************************************************************************/
603
604 /*
605 * SPI device driver setup and teardown
606 */
607
608 struct flash_info {
609 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
610 * a high byte of zero plus three data bytes: the manufacturer id,
611 * then a two byte device id.
612 */
613 u32 jedec_id;
614 u16 ext_id;
615
616 /* The size listed here is what works with OPCODE_SE, which isn't
617 * necessarily called a "sector" by the vendor.
618 */
619 unsigned sector_size;
620 u16 n_sectors;
621
622 u16 page_size;
623 u16 addr_width;
624
625 u16 flags;
626 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
627 #define M25P_NO_ERASE 0x02 /* No erase command needed */
628 };
629
630 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
631 ((kernel_ulong_t)&(struct flash_info) { \
632 .jedec_id = (_jedec_id), \
633 .ext_id = (_ext_id), \
634 .sector_size = (_sector_size), \
635 .n_sectors = (_n_sectors), \
636 .page_size = 256, \
637 .flags = (_flags), \
638 })
639
640 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
641 ((kernel_ulong_t)&(struct flash_info) { \
642 .sector_size = (_sector_size), \
643 .n_sectors = (_n_sectors), \
644 .page_size = (_page_size), \
645 .addr_width = (_addr_width), \
646 .flags = M25P_NO_ERASE, \
647 })
648
649 /* NOTE: double check command sets and memory organization when you add
650 * more flash chips. This current list focusses on newer chips, which
651 * have been converging on command sets which including JEDEC ID.
652 */
653 static const struct spi_device_id m25p_ids[] = {
654 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
655 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
656 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
657
658 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
659 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
660 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
661
662 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
663 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
664 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
665 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
666
667 /* EON -- en25xxx */
668 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
669 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
670 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
671 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
672
673 /* Intel/Numonyx -- xxxs33b */
674 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
675 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
676 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
677
678 /* Macronix */
679 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
680 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
681 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
682 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
683 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
684 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
685 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
686 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
687 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
688
689 /* Spansion -- single (large) sector size only, at least
690 * for the chips listed here (without boot sectors).
691 */
692 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
693 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
694 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
695 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
696 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
697 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
698 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
699 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
700 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
701 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
702 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
703 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
704 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
705 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
706 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
707 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
708
709 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
710 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
711 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
712 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
713 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
714 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
715 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
716 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
717 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
718
719 /* ST Microelectronics -- newer production may have feature updates */
720 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
721 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
722 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
723 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
724 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
725 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
726 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
727 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
728 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
729
730 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
731 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
732 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
733 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
734 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
735 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
736 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
737 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
738 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
739
740 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
741 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
742 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
743
744 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
745 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
746
747 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
748 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
749 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
750 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
751
752 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
753 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
754 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
755 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
756 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
757 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
758 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
759 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
760 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
761 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
762
763 /* Catalyst / On Semiconductor -- non-JEDEC */
764 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
765 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
766 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
767 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
768 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
769 { },
770 };
771 MODULE_DEVICE_TABLE(spi, m25p_ids);
772
jedec_probe(struct spi_device * spi)773 static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
774 {
775 int tmp;
776 u8 code = OPCODE_RDID;
777 u8 id[5];
778 u32 jedec;
779 u16 ext_jedec;
780 struct flash_info *info;
781
782 /* JEDEC also defines an optional "extended device information"
783 * string for after vendor-specific data, after the three bytes
784 * we use here. Supporting some chips might require using it.
785 */
786 tmp = spi_write_then_read(spi, &code, 1, id, 5);
787 if (tmp < 0) {
788 pr_debug("%s: error %d reading JEDEC ID\n",
789 dev_name(&spi->dev), tmp);
790 return ERR_PTR(tmp);
791 }
792 jedec = id[0];
793 jedec = jedec << 8;
794 jedec |= id[1];
795 jedec = jedec << 8;
796 jedec |= id[2];
797
798 ext_jedec = id[3] << 8 | id[4];
799
800 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
801 info = (void *)m25p_ids[tmp].driver_data;
802 if (info->jedec_id == jedec) {
803 if (info->ext_id != 0 && info->ext_id != ext_jedec)
804 continue;
805 return &m25p_ids[tmp];
806 }
807 }
808 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
809 return ERR_PTR(-ENODEV);
810 }
811
812
813 /*
814 * board specific setup should have ensured the SPI clock used here
815 * matches what the READ command supports, at least until this driver
816 * understands FAST_READ (for clocks over 25 MHz).
817 */
m25p_probe(struct spi_device * spi)818 static int __devinit m25p_probe(struct spi_device *spi)
819 {
820 const struct spi_device_id *id = spi_get_device_id(spi);
821 struct flash_platform_data *data;
822 struct m25p *flash;
823 struct flash_info *info;
824 unsigned i;
825 struct mtd_part_parser_data ppdata;
826
827 #ifdef CONFIG_MTD_OF_PARTS
828 if (!of_device_is_available(spi->dev.of_node))
829 return -ENODEV;
830 #endif
831
832 /* Platform data helps sort out which chip type we have, as
833 * well as how this board partitions it. If we don't have
834 * a chip ID, try the JEDEC id commands; they'll work for most
835 * newer chips, even if we don't recognize the particular chip.
836 */
837 data = spi->dev.platform_data;
838 if (data && data->type) {
839 const struct spi_device_id *plat_id;
840
841 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
842 plat_id = &m25p_ids[i];
843 if (strcmp(data->type, plat_id->name))
844 continue;
845 break;
846 }
847
848 if (i < ARRAY_SIZE(m25p_ids) - 1)
849 id = plat_id;
850 else
851 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
852 }
853
854 info = (void *)id->driver_data;
855
856 if (info->jedec_id) {
857 const struct spi_device_id *jid;
858
859 jid = jedec_probe(spi);
860 if (IS_ERR(jid)) {
861 return PTR_ERR(jid);
862 } else if (jid != id) {
863 /*
864 * JEDEC knows better, so overwrite platform ID. We
865 * can't trust partitions any longer, but we'll let
866 * mtd apply them anyway, since some partitions may be
867 * marked read-only, and we don't want to lose that
868 * information, even if it's not 100% accurate.
869 */
870 dev_warn(&spi->dev, "found %s, expected %s\n",
871 jid->name, id->name);
872 id = jid;
873 info = (void *)jid->driver_data;
874 }
875 }
876
877 flash = kzalloc(sizeof *flash, GFP_KERNEL);
878 if (!flash)
879 return -ENOMEM;
880 flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
881 if (!flash->command) {
882 kfree(flash);
883 return -ENOMEM;
884 }
885
886 flash->spi = spi;
887 mutex_init(&flash->lock);
888 dev_set_drvdata(&spi->dev, flash);
889
890 /*
891 * Atmel, SST and Intel/Numonyx serial flash tend to power
892 * up with the software protection bits set
893 */
894
895 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
896 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
897 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
898 write_enable(flash);
899 write_sr(flash, 0);
900 }
901
902 if (data && data->name)
903 flash->mtd.name = data->name;
904 else
905 flash->mtd.name = dev_name(&spi->dev);
906
907 flash->mtd.type = MTD_NORFLASH;
908 flash->mtd.writesize = 1;
909 flash->mtd.flags = MTD_CAP_NORFLASH;
910 flash->mtd.size = info->sector_size * info->n_sectors;
911 flash->mtd.erase = m25p80_erase;
912 flash->mtd.read = m25p80_read;
913
914 /* sst flash chips use AAI word program */
915 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
916 flash->mtd.write = sst_write;
917 else
918 flash->mtd.write = m25p80_write;
919
920 /* prefer "small sector" erase if possible */
921 if (info->flags & SECT_4K) {
922 flash->erase_opcode = OPCODE_BE_4K;
923 flash->mtd.erasesize = 4096;
924 } else {
925 flash->erase_opcode = OPCODE_SE;
926 flash->mtd.erasesize = info->sector_size;
927 }
928
929 if (info->flags & M25P_NO_ERASE)
930 flash->mtd.flags |= MTD_NO_ERASE;
931
932 ppdata.of_node = spi->dev.of_node;
933 flash->mtd.dev.parent = &spi->dev;
934 flash->page_size = info->page_size;
935
936 if (info->addr_width)
937 flash->addr_width = info->addr_width;
938 else {
939 /* enable 4-byte addressing if the device exceeds 16MiB */
940 if (flash->mtd.size > 0x1000000) {
941 flash->addr_width = 4;
942 set_4byte(flash, info->jedec_id, 1);
943 } else
944 flash->addr_width = 3;
945 }
946
947 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
948 (long long)flash->mtd.size >> 10);
949
950 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
951 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
952 flash->mtd.name,
953 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
954 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
955 flash->mtd.numeraseregions);
956
957 if (flash->mtd.numeraseregions)
958 for (i = 0; i < flash->mtd.numeraseregions; i++)
959 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
960 ".erasesize = 0x%.8x (%uKiB), "
961 ".numblocks = %d }\n",
962 i, (long long)flash->mtd.eraseregions[i].offset,
963 flash->mtd.eraseregions[i].erasesize,
964 flash->mtd.eraseregions[i].erasesize / 1024,
965 flash->mtd.eraseregions[i].numblocks);
966
967
968 /* partitions should match sector boundaries; and it may be good to
969 * use readonly partitions for writeprotected sectors (BP2..BP0).
970 */
971 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
972 data ? data->parts : NULL,
973 data ? data->nr_parts : 0);
974 }
975
976
m25p_remove(struct spi_device * spi)977 static int __devexit m25p_remove(struct spi_device *spi)
978 {
979 struct m25p *flash = dev_get_drvdata(&spi->dev);
980 int status;
981
982 /* Clean up MTD stuff. */
983 status = mtd_device_unregister(&flash->mtd);
984 if (status == 0) {
985 kfree(flash->command);
986 kfree(flash);
987 }
988 return 0;
989 }
990
991
992 static struct spi_driver m25p80_driver = {
993 .driver = {
994 .name = "m25p80",
995 .owner = THIS_MODULE,
996 },
997 .id_table = m25p_ids,
998 .probe = m25p_probe,
999 .remove = __devexit_p(m25p_remove),
1000
1001 /* REVISIT: many of these chips have deep power-down modes, which
1002 * should clearly be entered on suspend() to minimize power use.
1003 * And also when they're otherwise idle...
1004 */
1005 };
1006
1007
m25p80_init(void)1008 static int __init m25p80_init(void)
1009 {
1010 return spi_register_driver(&m25p80_driver);
1011 }
1012
1013
m25p80_exit(void)1014 static void __exit m25p80_exit(void)
1015 {
1016 spi_unregister_driver(&m25p80_driver);
1017 }
1018
1019
1020 module_init(m25p80_init);
1021 module_exit(m25p80_exit);
1022
1023 MODULE_LICENSE("GPL");
1024 MODULE_AUTHOR("Mike Lavender");
1025 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
1026