1 /*
2 * Freescale eSDHC controller driver.
3 *
4 * Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 *
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 */
15
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/mmc/host.h>
20 #include "sdhci-pltfm.h"
21 #include "sdhci-esdhc.h"
22
esdhc_readw(struct sdhci_host * host,int reg)23 static u16 esdhc_readw(struct sdhci_host *host, int reg)
24 {
25 u16 ret;
26 int base = reg & ~0x3;
27 int shift = (reg & 0x2) * 8;
28
29 if (unlikely(reg == SDHCI_HOST_VERSION))
30 ret = in_be32(host->ioaddr + base) & 0xffff;
31 else
32 ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
33 return ret;
34 }
35
esdhc_readb(struct sdhci_host * host,int reg)36 static u8 esdhc_readb(struct sdhci_host *host, int reg)
37 {
38 int base = reg & ~0x3;
39 int shift = (reg & 0x3) * 8;
40 u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
41
42 /*
43 * "DMA select" locates at offset 0x28 in SD specification, but on
44 * P5020 or P3041, it locates at 0x29.
45 */
46 if (reg == SDHCI_HOST_CONTROL) {
47 u32 dma_bits;
48
49 dma_bits = in_be32(host->ioaddr + reg);
50 /* DMA select is 22,23 bits in Protocol Control Register */
51 dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
52
53 /* fixup the result */
54 ret &= ~SDHCI_CTRL_DMA_MASK;
55 ret |= dma_bits;
56 }
57
58 return ret;
59 }
60
esdhc_writew(struct sdhci_host * host,u16 val,int reg)61 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
62 {
63 if (reg == SDHCI_BLOCK_SIZE) {
64 /*
65 * Two last DMA bits are reserved, and first one is used for
66 * non-standard blksz of 4096 bytes that we don't support
67 * yet. So clear the DMA boundary bits.
68 */
69 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
70 }
71 sdhci_be32bs_writew(host, val, reg);
72 }
73
esdhc_writeb(struct sdhci_host * host,u8 val,int reg)74 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
75 {
76 /*
77 * "DMA select" location is offset 0x28 in SD specification, but on
78 * P5020 or P3041, it's located at 0x29.
79 */
80 if (reg == SDHCI_HOST_CONTROL) {
81 u32 dma_bits;
82
83 /* DMA select is 22,23 bits in Protocol Control Register */
84 dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
85 clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
86 dma_bits);
87 val &= ~SDHCI_CTRL_DMA_MASK;
88 val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
89 }
90
91 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
92 if (reg == SDHCI_HOST_CONTROL)
93 val &= ~ESDHC_HOST_CONTROL_RES;
94 sdhci_be32bs_writeb(host, val, reg);
95 }
96
esdhc_of_enable_dma(struct sdhci_host * host)97 static int esdhc_of_enable_dma(struct sdhci_host *host)
98 {
99 setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
100 return 0;
101 }
102
esdhc_of_get_max_clock(struct sdhci_host * host)103 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
104 {
105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
106
107 return pltfm_host->clock;
108 }
109
esdhc_of_get_min_clock(struct sdhci_host * host)110 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
111 {
112 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
113
114 return pltfm_host->clock / 256 / 16;
115 }
116
117 static struct sdhci_ops sdhci_esdhc_ops = {
118 .read_l = sdhci_be32bs_readl,
119 .read_w = esdhc_readw,
120 .read_b = esdhc_readb,
121 .write_l = sdhci_be32bs_writel,
122 .write_w = esdhc_writew,
123 .write_b = esdhc_writeb,
124 .set_clock = esdhc_set_clock,
125 .enable_dma = esdhc_of_enable_dma,
126 .get_max_clock = esdhc_of_get_max_clock,
127 .get_min_clock = esdhc_of_get_min_clock,
128 };
129
130 static struct sdhci_pltfm_data sdhci_esdhc_pdata = {
131 /* card detection could be handled via GPIO */
132 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
133 | SDHCI_QUIRK_NO_CARD_NO_RESET,
134 .ops = &sdhci_esdhc_ops,
135 };
136
sdhci_esdhc_probe(struct platform_device * pdev)137 static int __devinit sdhci_esdhc_probe(struct platform_device *pdev)
138 {
139 return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
140 }
141
sdhci_esdhc_remove(struct platform_device * pdev)142 static int __devexit sdhci_esdhc_remove(struct platform_device *pdev)
143 {
144 return sdhci_pltfm_unregister(pdev);
145 }
146
147 static const struct of_device_id sdhci_esdhc_of_match[] = {
148 { .compatible = "fsl,mpc8379-esdhc" },
149 { .compatible = "fsl,mpc8536-esdhc" },
150 { .compatible = "fsl,esdhc" },
151 { }
152 };
153 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
154
155 static struct platform_driver sdhci_esdhc_driver = {
156 .driver = {
157 .name = "sdhci-esdhc",
158 .owner = THIS_MODULE,
159 .of_match_table = sdhci_esdhc_of_match,
160 .pm = SDHCI_PLTFM_PMOPS,
161 },
162 .probe = sdhci_esdhc_probe,
163 .remove = __devexit_p(sdhci_esdhc_remove),
164 };
165
166 module_platform_driver(sdhci_esdhc_driver);
167
168 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
169 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
170 "Anton Vorontsov <avorontsov@ru.mvista.com>");
171 MODULE_LICENSE("GPL v2");
172