1 /*
2 * adv7343 - ADV7343 Video Encoder Driver
3 *
4 * The encoder hardware does not support SECAM.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/ctype.h>
21 #include <linux/slab.h>
22 #include <linux/i2c.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/videodev2.h>
27 #include <linux/uaccess.h>
28
29 #include <media/adv7343.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-chip-ident.h>
32 #include <media/v4l2-ctrls.h>
33
34 #include "adv7343_regs.h"
35
36 MODULE_DESCRIPTION("ADV7343 video encoder driver");
37 MODULE_LICENSE("GPL");
38
39 static int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "Debug level 0-1");
42
43 struct adv7343_state {
44 struct v4l2_subdev sd;
45 struct v4l2_ctrl_handler hdl;
46 u8 reg00;
47 u8 reg01;
48 u8 reg02;
49 u8 reg35;
50 u8 reg80;
51 u8 reg82;
52 u32 output;
53 v4l2_std_id std;
54 };
55
to_state(struct v4l2_subdev * sd)56 static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
57 {
58 return container_of(sd, struct adv7343_state, sd);
59 }
60
to_sd(struct v4l2_ctrl * ctrl)61 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
62 {
63 return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
64 }
65
adv7343_write(struct v4l2_subdev * sd,u8 reg,u8 value)66 static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
67 {
68 struct i2c_client *client = v4l2_get_subdevdata(sd);
69
70 return i2c_smbus_write_byte_data(client, reg, value);
71 }
72
73 static const u8 adv7343_init_reg_val[] = {
74 ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
75 ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
76
77 ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
78 ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
79 ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
80 ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
81 ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
82 ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
83 ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
84
85 ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
86 ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
87 ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
88 ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
89 ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
90 ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
91 ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
92 ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
93
94 ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
95 ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
96 ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
97 };
98
99 /*
100 * 2^32
101 * FSC(reg) = FSC (HZ) * --------
102 * 27000000
103 */
104 static const struct adv7343_std_info stdinfo[] = {
105 {
106 /* FSC(Hz) = 3,579,545.45 Hz */
107 SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
108 }, {
109 /* FSC(Hz) = 3,575,611.00 Hz */
110 SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
111 }, {
112 /* FSC(Hz) = 3,582,056.00 */
113 SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
114 }, {
115 /* FSC(Hz) = 4,433,618.75 Hz */
116 SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
117 }, {
118 /* FSC(Hz) = 4,433,618.75 Hz */
119 SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
120 }, {
121 /* FSC(Hz) = 4,433,618.75 Hz */
122 SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
123 }, {
124 /* FSC(Hz) = 4,433,618.75 Hz */
125 SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
126 },
127 };
128
adv7343_setstd(struct v4l2_subdev * sd,v4l2_std_id std)129 static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
130 {
131 struct adv7343_state *state = to_state(sd);
132 struct adv7343_std_info *std_info;
133 int output_idx, num_std;
134 char *fsc_ptr;
135 u8 reg, val;
136 int err = 0;
137 int i = 0;
138
139 output_idx = state->output;
140
141 std_info = (struct adv7343_std_info *)stdinfo;
142 num_std = ARRAY_SIZE(stdinfo);
143
144 for (i = 0; i < num_std; i++) {
145 if (std_info[i].stdid & std)
146 break;
147 }
148
149 if (i == num_std) {
150 v4l2_dbg(1, debug, sd,
151 "Invalid std or std is not supported: %llx\n",
152 (unsigned long long)std);
153 return -EINVAL;
154 }
155
156 /* Set the standard */
157 val = state->reg80 & (~(SD_STD_MASK));
158 val |= std_info[i].standard_val3;
159 err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
160 if (err < 0)
161 goto setstd_exit;
162
163 state->reg80 = val;
164
165 /* Configure the input mode register */
166 val = state->reg01 & (~((u8) INPUT_MODE_MASK));
167 val |= SD_INPUT_MODE;
168 err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
169 if (err < 0)
170 goto setstd_exit;
171
172 state->reg01 = val;
173
174 /* Program the sub carrier frequency registers */
175 fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
176 reg = ADV7343_FSC_REG0;
177 for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
178 err = adv7343_write(sd, reg, *fsc_ptr);
179 if (err < 0)
180 goto setstd_exit;
181 }
182
183 val = state->reg80;
184
185 /* Filter settings */
186 if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
187 val &= 0x03;
188 else if (std & ~V4L2_STD_SECAM)
189 val |= 0x04;
190
191 err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
192 if (err < 0)
193 goto setstd_exit;
194
195 state->reg80 = val;
196
197 setstd_exit:
198 if (err != 0)
199 v4l2_err(sd, "Error setting std, write failed\n");
200
201 return err;
202 }
203
adv7343_setoutput(struct v4l2_subdev * sd,u32 output_type)204 static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
205 {
206 struct adv7343_state *state = to_state(sd);
207 unsigned char val;
208 int err = 0;
209
210 if (output_type > ADV7343_SVIDEO_ID) {
211 v4l2_dbg(1, debug, sd,
212 "Invalid output type or output type not supported:%d\n",
213 output_type);
214 return -EINVAL;
215 }
216
217 /* Enable Appropriate DAC */
218 val = state->reg00 & 0x03;
219
220 if (output_type == ADV7343_COMPOSITE_ID)
221 val |= ADV7343_COMPOSITE_POWER_VALUE;
222 else if (output_type == ADV7343_COMPONENT_ID)
223 val |= ADV7343_COMPONENT_POWER_VALUE;
224 else
225 val |= ADV7343_SVIDEO_POWER_VALUE;
226
227 err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
228 if (err < 0)
229 goto setoutput_exit;
230
231 state->reg00 = val;
232
233 /* Enable YUV output */
234 val = state->reg02 | YUV_OUTPUT_SELECT;
235 err = adv7343_write(sd, ADV7343_MODE_REG0, val);
236 if (err < 0)
237 goto setoutput_exit;
238
239 state->reg02 = val;
240
241 /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
242 val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
243 err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
244 if (err < 0)
245 goto setoutput_exit;
246
247 state->reg82 = val;
248
249 /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
250 * zero */
251 val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
252 err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
253 if (err < 0)
254 goto setoutput_exit;
255
256 state->reg35 = val;
257
258 setoutput_exit:
259 if (err != 0)
260 v4l2_err(sd, "Error setting output, write failed\n");
261
262 return err;
263 }
264
adv7343_log_status(struct v4l2_subdev * sd)265 static int adv7343_log_status(struct v4l2_subdev *sd)
266 {
267 struct adv7343_state *state = to_state(sd);
268
269 v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
270 v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
271 ((state->output == 1) ? "Component" : "S-Video"));
272 return 0;
273 }
274
adv7343_s_ctrl(struct v4l2_ctrl * ctrl)275 static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
276 {
277 struct v4l2_subdev *sd = to_sd(ctrl);
278
279 switch (ctrl->id) {
280 case V4L2_CID_BRIGHTNESS:
281 return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
282 ctrl->val);
283
284 case V4L2_CID_HUE:
285 return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
286
287 case V4L2_CID_GAIN:
288 return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
289 }
290 return -EINVAL;
291 }
292
adv7343_g_chip_ident(struct v4l2_subdev * sd,struct v4l2_dbg_chip_ident * chip)293 static int adv7343_g_chip_ident(struct v4l2_subdev *sd,
294 struct v4l2_dbg_chip_ident *chip)
295 {
296 struct i2c_client *client = v4l2_get_subdevdata(sd);
297
298 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7343, 0);
299 }
300
301 static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
302 .s_ctrl = adv7343_s_ctrl,
303 };
304
305 static const struct v4l2_subdev_core_ops adv7343_core_ops = {
306 .log_status = adv7343_log_status,
307 .g_chip_ident = adv7343_g_chip_ident,
308 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
309 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
310 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
311 .g_ctrl = v4l2_subdev_g_ctrl,
312 .s_ctrl = v4l2_subdev_s_ctrl,
313 .queryctrl = v4l2_subdev_queryctrl,
314 .querymenu = v4l2_subdev_querymenu,
315 };
316
adv7343_s_std_output(struct v4l2_subdev * sd,v4l2_std_id std)317 static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
318 {
319 struct adv7343_state *state = to_state(sd);
320 int err = 0;
321
322 if (state->std == std)
323 return 0;
324
325 err = adv7343_setstd(sd, std);
326 if (!err)
327 state->std = std;
328
329 return err;
330 }
331
adv7343_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)332 static int adv7343_s_routing(struct v4l2_subdev *sd,
333 u32 input, u32 output, u32 config)
334 {
335 struct adv7343_state *state = to_state(sd);
336 int err = 0;
337
338 if (state->output == output)
339 return 0;
340
341 err = adv7343_setoutput(sd, output);
342 if (!err)
343 state->output = output;
344
345 return err;
346 }
347
348 static const struct v4l2_subdev_video_ops adv7343_video_ops = {
349 .s_std_output = adv7343_s_std_output,
350 .s_routing = adv7343_s_routing,
351 };
352
353 static const struct v4l2_subdev_ops adv7343_ops = {
354 .core = &adv7343_core_ops,
355 .video = &adv7343_video_ops,
356 };
357
adv7343_initialize(struct v4l2_subdev * sd)358 static int adv7343_initialize(struct v4l2_subdev *sd)
359 {
360 struct adv7343_state *state = to_state(sd);
361 int err = 0;
362 int i;
363
364 for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
365
366 err = adv7343_write(sd, adv7343_init_reg_val[i],
367 adv7343_init_reg_val[i+1]);
368 if (err) {
369 v4l2_err(sd, "Error initializing\n");
370 return err;
371 }
372 }
373
374 /* Configure for default video standard */
375 err = adv7343_setoutput(sd, state->output);
376 if (err < 0) {
377 v4l2_err(sd, "Error setting output during init\n");
378 return -EINVAL;
379 }
380
381 err = adv7343_setstd(sd, state->std);
382 if (err < 0) {
383 v4l2_err(sd, "Error setting std during init\n");
384 return -EINVAL;
385 }
386
387 return err;
388 }
389
adv7343_probe(struct i2c_client * client,const struct i2c_device_id * id)390 static int adv7343_probe(struct i2c_client *client,
391 const struct i2c_device_id *id)
392 {
393 struct adv7343_state *state;
394 int err;
395
396 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
397 return -ENODEV;
398
399 v4l_info(client, "chip found @ 0x%x (%s)\n",
400 client->addr << 1, client->adapter->name);
401
402 state = kzalloc(sizeof(struct adv7343_state), GFP_KERNEL);
403 if (state == NULL)
404 return -ENOMEM;
405
406 state->reg00 = 0x80;
407 state->reg01 = 0x00;
408 state->reg02 = 0x20;
409 state->reg35 = 0x00;
410 state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
411 state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
412
413 state->output = ADV7343_COMPOSITE_ID;
414 state->std = V4L2_STD_NTSC;
415
416 v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
417
418 v4l2_ctrl_handler_init(&state->hdl, 2);
419 v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
420 V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
421 ADV7343_BRIGHTNESS_MAX, 1,
422 ADV7343_BRIGHTNESS_DEF);
423 v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
424 V4L2_CID_HUE, ADV7343_HUE_MIN,
425 ADV7343_HUE_MAX, 1,
426 ADV7343_HUE_DEF);
427 v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
428 V4L2_CID_GAIN, ADV7343_GAIN_MIN,
429 ADV7343_GAIN_MAX, 1,
430 ADV7343_GAIN_DEF);
431 state->sd.ctrl_handler = &state->hdl;
432 if (state->hdl.error) {
433 int err = state->hdl.error;
434
435 v4l2_ctrl_handler_free(&state->hdl);
436 kfree(state);
437 return err;
438 }
439 v4l2_ctrl_handler_setup(&state->hdl);
440
441 err = adv7343_initialize(&state->sd);
442 if (err) {
443 v4l2_ctrl_handler_free(&state->hdl);
444 kfree(state);
445 }
446 return err;
447 }
448
adv7343_remove(struct i2c_client * client)449 static int adv7343_remove(struct i2c_client *client)
450 {
451 struct v4l2_subdev *sd = i2c_get_clientdata(client);
452 struct adv7343_state *state = to_state(sd);
453
454 v4l2_device_unregister_subdev(sd);
455 v4l2_ctrl_handler_free(&state->hdl);
456 kfree(state);
457
458 return 0;
459 }
460
461 static const struct i2c_device_id adv7343_id[] = {
462 {"adv7343", 0},
463 {},
464 };
465
466 MODULE_DEVICE_TABLE(i2c, adv7343_id);
467
468 static struct i2c_driver adv7343_driver = {
469 .driver = {
470 .owner = THIS_MODULE,
471 .name = "adv7343",
472 },
473 .probe = adv7343_probe,
474 .remove = adv7343_remove,
475 .id_table = adv7343_id,
476 };
477
init_adv7343(void)478 static __init int init_adv7343(void)
479 {
480 return i2c_add_driver(&adv7343_driver);
481 }
482
exit_adv7343(void)483 static __exit void exit_adv7343(void)
484 {
485 i2c_del_driver(&adv7343_driver);
486 }
487
488 module_init(init_adv7343);
489 module_exit(exit_adv7343);
490