1 /*
2 Driver for Philips tda1004xh OFDM Demodulator
3
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22 /*
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27 * or /lib/firmware (depending on configuration of firmware hotplug).
28 */
29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/device.h>
35 #include <linux/jiffies.h>
36 #include <linux/string.h>
37 #include <linux/slab.h>
38
39 #include "dvb_frontend.h"
40 #include "tda1004x.h"
41
42 static int debug;
43 #define dprintk(args...) \
44 do { \
45 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
46 } while (0)
47
48 #define TDA1004X_CHIPID 0x00
49 #define TDA1004X_AUTO 0x01
50 #define TDA1004X_IN_CONF1 0x02
51 #define TDA1004X_IN_CONF2 0x03
52 #define TDA1004X_OUT_CONF1 0x04
53 #define TDA1004X_OUT_CONF2 0x05
54 #define TDA1004X_STATUS_CD 0x06
55 #define TDA1004X_CONFC4 0x07
56 #define TDA1004X_DSSPARE2 0x0C
57 #define TDA10045H_CODE_IN 0x0D
58 #define TDA10045H_FWPAGE 0x0E
59 #define TDA1004X_SCAN_CPT 0x10
60 #define TDA1004X_DSP_CMD 0x11
61 #define TDA1004X_DSP_ARG 0x12
62 #define TDA1004X_DSP_DATA1 0x13
63 #define TDA1004X_DSP_DATA2 0x14
64 #define TDA1004X_CONFADC1 0x15
65 #define TDA1004X_CONFC1 0x16
66 #define TDA10045H_S_AGC 0x1a
67 #define TDA10046H_AGC_TUN_LEVEL 0x1a
68 #define TDA1004X_SNR 0x1c
69 #define TDA1004X_CONF_TS1 0x1e
70 #define TDA1004X_CONF_TS2 0x1f
71 #define TDA1004X_CBER_RESET 0x20
72 #define TDA1004X_CBER_MSB 0x21
73 #define TDA1004X_CBER_LSB 0x22
74 #define TDA1004X_CVBER_LUT 0x23
75 #define TDA1004X_VBER_MSB 0x24
76 #define TDA1004X_VBER_MID 0x25
77 #define TDA1004X_VBER_LSB 0x26
78 #define TDA1004X_UNCOR 0x27
79
80 #define TDA10045H_CONFPLL_P 0x2D
81 #define TDA10045H_CONFPLL_M_MSB 0x2E
82 #define TDA10045H_CONFPLL_M_LSB 0x2F
83 #define TDA10045H_CONFPLL_N 0x30
84
85 #define TDA10046H_CONFPLL1 0x2D
86 #define TDA10046H_CONFPLL2 0x2F
87 #define TDA10046H_CONFPLL3 0x30
88 #define TDA10046H_TIME_WREF1 0x31
89 #define TDA10046H_TIME_WREF2 0x32
90 #define TDA10046H_TIME_WREF3 0x33
91 #define TDA10046H_TIME_WREF4 0x34
92 #define TDA10046H_TIME_WREF5 0x35
93
94 #define TDA10045H_UNSURW_MSB 0x31
95 #define TDA10045H_UNSURW_LSB 0x32
96 #define TDA10045H_WREF_MSB 0x33
97 #define TDA10045H_WREF_MID 0x34
98 #define TDA10045H_WREF_LSB 0x35
99 #define TDA10045H_MUXOUT 0x36
100 #define TDA1004X_CONFADC2 0x37
101
102 #define TDA10045H_IOFFSET 0x38
103
104 #define TDA10046H_CONF_TRISTATE1 0x3B
105 #define TDA10046H_CONF_TRISTATE2 0x3C
106 #define TDA10046H_CONF_POLARITY 0x3D
107 #define TDA10046H_FREQ_OFFSET 0x3E
108 #define TDA10046H_GPIO_OUT_SEL 0x41
109 #define TDA10046H_GPIO_SELECT 0x42
110 #define TDA10046H_AGC_CONF 0x43
111 #define TDA10046H_AGC_THR 0x44
112 #define TDA10046H_AGC_RENORM 0x45
113 #define TDA10046H_AGC_GAINS 0x46
114 #define TDA10046H_AGC_TUN_MIN 0x47
115 #define TDA10046H_AGC_TUN_MAX 0x48
116 #define TDA10046H_AGC_IF_MIN 0x49
117 #define TDA10046H_AGC_IF_MAX 0x4A
118
119 #define TDA10046H_FREQ_PHY2_MSB 0x4D
120 #define TDA10046H_FREQ_PHY2_LSB 0x4E
121
122 #define TDA10046H_CVBER_CTRL 0x4F
123 #define TDA10046H_AGC_IF_LEVEL 0x52
124 #define TDA10046H_CODE_CPT 0x57
125 #define TDA10046H_CODE_IN 0x58
126
127
tda1004x_write_byteI(struct tda1004x_state * state,int reg,int data)128 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
129 {
130 int ret;
131 u8 buf[] = { reg, data };
132 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
133
134 dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
135
136 msg.addr = state->config->demod_address;
137 ret = i2c_transfer(state->i2c, &msg, 1);
138
139 if (ret != 1)
140 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
141 __func__, reg, data, ret);
142
143 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
144 reg, data, ret);
145 return (ret != 1) ? -1 : 0;
146 }
147
tda1004x_read_byte(struct tda1004x_state * state,int reg)148 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
149 {
150 int ret;
151 u8 b0[] = { reg };
152 u8 b1[] = { 0 };
153 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
154 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
155
156 dprintk("%s: reg=0x%x\n", __func__, reg);
157
158 msg[0].addr = state->config->demod_address;
159 msg[1].addr = state->config->demod_address;
160 ret = i2c_transfer(state->i2c, msg, 2);
161
162 if (ret != 2) {
163 dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
164 ret);
165 return -EINVAL;
166 }
167
168 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
169 reg, b1[0], ret);
170 return b1[0];
171 }
172
tda1004x_write_mask(struct tda1004x_state * state,int reg,int mask,int data)173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
174 {
175 int val;
176 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
177 mask, data);
178
179 // read a byte and check
180 val = tda1004x_read_byte(state, reg);
181 if (val < 0)
182 return val;
183
184 // mask if off
185 val = val & ~mask;
186 val |= data & 0xff;
187
188 // write it out again
189 return tda1004x_write_byteI(state, reg, val);
190 }
191
tda1004x_write_buf(struct tda1004x_state * state,int reg,unsigned char * buf,int len)192 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
193 {
194 int i;
195 int result;
196
197 dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
198
199 result = 0;
200 for (i = 0; i < len; i++) {
201 result = tda1004x_write_byteI(state, reg + i, buf[i]);
202 if (result != 0)
203 break;
204 }
205
206 return result;
207 }
208
tda1004x_enable_tuner_i2c(struct tda1004x_state * state)209 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
210 {
211 int result;
212 dprintk("%s\n", __func__);
213
214 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
215 msleep(20);
216 return result;
217 }
218
tda1004x_disable_tuner_i2c(struct tda1004x_state * state)219 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
220 {
221 dprintk("%s\n", __func__);
222
223 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
224 }
225
tda10045h_set_bandwidth(struct tda1004x_state * state,u32 bandwidth)226 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
227 u32 bandwidth)
228 {
229 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
230 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
231 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
232
233 switch (bandwidth) {
234 case 6000000:
235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
236 break;
237
238 case 7000000:
239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
240 break;
241
242 case 8000000:
243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
244 break;
245
246 default:
247 return -EINVAL;
248 }
249
250 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
251
252 return 0;
253 }
254
tda10046h_set_bandwidth(struct tda1004x_state * state,u32 bandwidth)255 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
256 u32 bandwidth)
257 {
258 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
259 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
260 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
261
262 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
263 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
264 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
265 int tda10046_clk53m;
266
267 if ((state->config->if_freq == TDA10046_FREQ_045) ||
268 (state->config->if_freq == TDA10046_FREQ_052))
269 tda10046_clk53m = 0;
270 else
271 tda10046_clk53m = 1;
272 switch (bandwidth) {
273 case 6000000:
274 if (tda10046_clk53m)
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
276 sizeof(bandwidth_6mhz_53M));
277 else
278 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
279 sizeof(bandwidth_6mhz_48M));
280 if (state->config->if_freq == TDA10046_FREQ_045) {
281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
283 }
284 break;
285
286 case 7000000:
287 if (tda10046_clk53m)
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
289 sizeof(bandwidth_7mhz_53M));
290 else
291 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
292 sizeof(bandwidth_7mhz_48M));
293 if (state->config->if_freq == TDA10046_FREQ_045) {
294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
296 }
297 break;
298
299 case 8000000:
300 if (tda10046_clk53m)
301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
302 sizeof(bandwidth_8mhz_53M));
303 else
304 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
305 sizeof(bandwidth_8mhz_48M));
306 if (state->config->if_freq == TDA10046_FREQ_045) {
307 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
309 }
310 break;
311
312 default:
313 return -EINVAL;
314 }
315
316 return 0;
317 }
318
tda1004x_do_upload(struct tda1004x_state * state,const unsigned char * mem,unsigned int len,u8 dspCodeCounterReg,u8 dspCodeInReg)319 static int tda1004x_do_upload(struct tda1004x_state *state,
320 const unsigned char *mem, unsigned int len,
321 u8 dspCodeCounterReg, u8 dspCodeInReg)
322 {
323 u8 buf[65];
324 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
325 int tx_size;
326 int pos = 0;
327
328 /* clear code counter */
329 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
330 fw_msg.addr = state->config->demod_address;
331
332 buf[0] = dspCodeInReg;
333 while (pos != len) {
334 // work out how much to send this time
335 tx_size = len - pos;
336 if (tx_size > 0x10)
337 tx_size = 0x10;
338
339 // send the chunk
340 memcpy(buf + 1, mem + pos, tx_size);
341 fw_msg.len = tx_size + 1;
342 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
343 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
344 return -EIO;
345 }
346 pos += tx_size;
347
348 dprintk("%s: fw_pos=0x%x\n", __func__, pos);
349 }
350 // give the DSP a chance to settle 03/10/05 Hac
351 msleep(100);
352
353 return 0;
354 }
355
tda1004x_check_upload_ok(struct tda1004x_state * state)356 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
357 {
358 u8 data1, data2;
359 unsigned long timeout;
360
361 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
362 timeout = jiffies + 2 * HZ;
363 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
364 if (time_after(jiffies, timeout)) {
365 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
366 break;
367 }
368 msleep(1);
369 }
370 } else
371 msleep(100);
372
373 // check upload was OK
374 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
375 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
376
377 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
378 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
379 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
380 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
381 return -EIO;
382 }
383 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
384 return 0;
385 }
386
tda10045_fwupload(struct dvb_frontend * fe)387 static int tda10045_fwupload(struct dvb_frontend* fe)
388 {
389 struct tda1004x_state* state = fe->demodulator_priv;
390 int ret;
391 const struct firmware *fw;
392
393 /* don't re-upload unless necessary */
394 if (tda1004x_check_upload_ok(state) == 0)
395 return 0;
396
397 /* request the firmware, this will block until someone uploads it */
398 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
399 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
400 if (ret) {
401 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
402 return ret;
403 }
404
405 /* reset chip */
406 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
407 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
408 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
409 msleep(10);
410
411 /* set parameters */
412 tda10045h_set_bandwidth(state, 8000000);
413
414 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
415 release_firmware(fw);
416 if (ret)
417 return ret;
418 printk(KERN_INFO "tda1004x: firmware upload complete\n");
419
420 /* wait for DSP to initialise */
421 /* DSPREADY doesn't seem to work on the TDA10045H */
422 msleep(100);
423
424 return tda1004x_check_upload_ok(state);
425 }
426
tda10046_init_plls(struct dvb_frontend * fe)427 static void tda10046_init_plls(struct dvb_frontend* fe)
428 {
429 struct tda1004x_state* state = fe->demodulator_priv;
430 int tda10046_clk53m;
431
432 if ((state->config->if_freq == TDA10046_FREQ_045) ||
433 (state->config->if_freq == TDA10046_FREQ_052))
434 tda10046_clk53m = 0;
435 else
436 tda10046_clk53m = 1;
437
438 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
439 if(tda10046_clk53m) {
440 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
441 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
442 } else {
443 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
444 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
445 }
446 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
447 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
448 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
449 } else {
450 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
451 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
452 }
453 if(tda10046_clk53m)
454 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
455 else
456 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
457 /* Note clock frequency is handled implicitly */
458 switch (state->config->if_freq) {
459 case TDA10046_FREQ_045:
460 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
461 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
462 break;
463 case TDA10046_FREQ_052:
464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
466 break;
467 case TDA10046_FREQ_3617:
468 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
470 break;
471 case TDA10046_FREQ_3613:
472 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
474 break;
475 }
476 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
477 /* let the PLLs settle */
478 msleep(120);
479 }
480
tda10046_fwupload(struct dvb_frontend * fe)481 static int tda10046_fwupload(struct dvb_frontend* fe)
482 {
483 struct tda1004x_state* state = fe->demodulator_priv;
484 int ret, confc4;
485 const struct firmware *fw;
486
487 /* reset + wake up chip */
488 if (state->config->xtal_freq == TDA10046_XTAL_4M) {
489 confc4 = 0;
490 } else {
491 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
492 confc4 = 0x80;
493 }
494 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
495
496 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
497 /* set GPIO 1 and 3 */
498 if (state->config->gpio_config != TDA10046_GPTRI) {
499 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
500 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
501 }
502 /* let the clocks recover from sleep */
503 msleep(10);
504
505 /* The PLLs need to be reprogrammed after sleep */
506 tda10046_init_plls(fe);
507 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
508
509 /* don't re-upload unless necessary */
510 if (tda1004x_check_upload_ok(state) == 0)
511 return 0;
512
513 /*
514 For i2c normal work, we need to slow down the bus speed.
515 However, the slow down breaks the eeprom firmware load.
516 So, use normal speed for eeprom booting and then restore the
517 i2c speed after that. Tested with MSI TV @nyware A/D board,
518 that comes with firmware version 29 inside their eeprom.
519
520 It should also be noticed that no other I2C transfer should
521 be in course while booting from eeprom, otherwise, tda10046
522 goes into an instable state. So, proper locking are needed
523 at the i2c bus master.
524 */
525 printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
526 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
527 msleep(300);
528 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
529
530 /* Checks if eeprom firmware went without troubles */
531 if (tda1004x_check_upload_ok(state) == 0)
532 return 0;
533
534 /* eeprom firmware didn't work. Load one manually. */
535
536 if (state->config->request_firmware != NULL) {
537 /* request the firmware, this will block until someone uploads it */
538 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
539 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
540 if (ret) {
541 /* remain compatible to old bug: try to load with tda10045 image name */
542 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
543 if (ret) {
544 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
545 return ret;
546 } else {
547 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
548 TDA10046_DEFAULT_FIRMWARE);
549 }
550 }
551 } else {
552 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
553 return -EIO;
554 }
555 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
556 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
557 release_firmware(fw);
558 return tda1004x_check_upload_ok(state);
559 }
560
tda1004x_encode_fec(int fec)561 static int tda1004x_encode_fec(int fec)
562 {
563 // convert known FEC values
564 switch (fec) {
565 case FEC_1_2:
566 return 0;
567 case FEC_2_3:
568 return 1;
569 case FEC_3_4:
570 return 2;
571 case FEC_5_6:
572 return 3;
573 case FEC_7_8:
574 return 4;
575 }
576
577 // unsupported
578 return -EINVAL;
579 }
580
tda1004x_decode_fec(int tdafec)581 static int tda1004x_decode_fec(int tdafec)
582 {
583 // convert known FEC values
584 switch (tdafec) {
585 case 0:
586 return FEC_1_2;
587 case 1:
588 return FEC_2_3;
589 case 2:
590 return FEC_3_4;
591 case 3:
592 return FEC_5_6;
593 case 4:
594 return FEC_7_8;
595 }
596
597 // unsupported
598 return -1;
599 }
600
tda1004x_write(struct dvb_frontend * fe,const u8 buf[],int len)601 static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len)
602 {
603 struct tda1004x_state* state = fe->demodulator_priv;
604
605 if (len != 2)
606 return -EINVAL;
607
608 return tda1004x_write_byteI(state, buf[0], buf[1]);
609 }
610
tda10045_init(struct dvb_frontend * fe)611 static int tda10045_init(struct dvb_frontend* fe)
612 {
613 struct tda1004x_state* state = fe->demodulator_priv;
614
615 dprintk("%s\n", __func__);
616
617 if (tda10045_fwupload(fe)) {
618 printk("tda1004x: firmware upload failed\n");
619 return -EIO;
620 }
621
622 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
623
624 // tda setup
625 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
626 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
627 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
628 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
629 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
630 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
631 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
632 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
633 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
634 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
635 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
636
637 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
638
639 return 0;
640 }
641
tda10046_init(struct dvb_frontend * fe)642 static int tda10046_init(struct dvb_frontend* fe)
643 {
644 struct tda1004x_state* state = fe->demodulator_priv;
645 dprintk("%s\n", __func__);
646
647 if (tda10046_fwupload(fe)) {
648 printk("tda1004x: firmware upload failed\n");
649 return -EIO;
650 }
651
652 // tda setup
653 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
654 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
655 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
656
657 switch (state->config->agc_config) {
658 case TDA10046_AGC_DEFAULT:
659 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
660 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
661 break;
662 case TDA10046_AGC_IFO_AUTO_NEG:
663 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
664 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
665 break;
666 case TDA10046_AGC_IFO_AUTO_POS:
667 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
668 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
669 break;
670 case TDA10046_AGC_TDA827X:
671 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
672 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
673 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
674 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
675 break;
676 }
677 if (state->config->ts_mode == 0) {
678 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
679 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
680 } else {
681 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
682 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
683 state->config->invert_oclk << 4);
684 }
685 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
686 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
687 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
688 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
689 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
690 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
691 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
692 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
693 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
694 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
695 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
696
697 return 0;
698 }
699
tda1004x_set_fe(struct dvb_frontend * fe)700 static int tda1004x_set_fe(struct dvb_frontend *fe)
701 {
702 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
703 struct tda1004x_state* state = fe->demodulator_priv;
704 int tmp;
705 int inversion;
706
707 dprintk("%s\n", __func__);
708
709 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
710 // setup auto offset
711 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
712 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
713 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
714
715 // disable agc_conf[2]
716 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
717 }
718
719 // set frequency
720 if (fe->ops.tuner_ops.set_params) {
721 fe->ops.tuner_ops.set_params(fe);
722 if (fe->ops.i2c_gate_ctrl)
723 fe->ops.i2c_gate_ctrl(fe, 0);
724 }
725
726 // Hardcoded to use auto as much as possible on the TDA10045 as it
727 // is very unreliable if AUTO mode is _not_ used.
728 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
729 fe_params->code_rate_HP = FEC_AUTO;
730 fe_params->guard_interval = GUARD_INTERVAL_AUTO;
731 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
732 }
733
734 // Set standard params.. or put them to auto
735 if ((fe_params->code_rate_HP == FEC_AUTO) ||
736 (fe_params->code_rate_LP == FEC_AUTO) ||
737 (fe_params->modulation == QAM_AUTO) ||
738 (fe_params->hierarchy == HIERARCHY_AUTO)) {
739 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
742 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
743 } else {
744 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
745
746 // set HP FEC
747 tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
748 if (tmp < 0)
749 return tmp;
750 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
751
752 // set LP FEC
753 tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
754 if (tmp < 0)
755 return tmp;
756 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
757
758 /* set modulation */
759 switch (fe_params->modulation) {
760 case QPSK:
761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
762 break;
763
764 case QAM_16:
765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
766 break;
767
768 case QAM_64:
769 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
770 break;
771
772 default:
773 return -EINVAL;
774 }
775
776 // set hierarchy
777 switch (fe_params->hierarchy) {
778 case HIERARCHY_NONE:
779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
780 break;
781
782 case HIERARCHY_1:
783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
784 break;
785
786 case HIERARCHY_2:
787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
788 break;
789
790 case HIERARCHY_4:
791 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
792 break;
793
794 default:
795 return -EINVAL;
796 }
797 }
798
799 // set bandwidth
800 switch (state->demod_type) {
801 case TDA1004X_DEMOD_TDA10045:
802 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
803 break;
804
805 case TDA1004X_DEMOD_TDA10046:
806 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
807 break;
808 }
809
810 // set inversion
811 inversion = fe_params->inversion;
812 if (state->config->invert)
813 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
814 switch (inversion) {
815 case INVERSION_OFF:
816 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
817 break;
818
819 case INVERSION_ON:
820 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
821 break;
822
823 default:
824 return -EINVAL;
825 }
826
827 // set guard interval
828 switch (fe_params->guard_interval) {
829 case GUARD_INTERVAL_1_32:
830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
832 break;
833
834 case GUARD_INTERVAL_1_16:
835 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
836 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
837 break;
838
839 case GUARD_INTERVAL_1_8:
840 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
841 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
842 break;
843
844 case GUARD_INTERVAL_1_4:
845 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
846 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
847 break;
848
849 case GUARD_INTERVAL_AUTO:
850 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
851 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
852 break;
853
854 default:
855 return -EINVAL;
856 }
857
858 // set transmission mode
859 switch (fe_params->transmission_mode) {
860 case TRANSMISSION_MODE_2K:
861 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
862 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
863 break;
864
865 case TRANSMISSION_MODE_8K:
866 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
867 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
868 break;
869
870 case TRANSMISSION_MODE_AUTO:
871 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
872 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
873 break;
874
875 default:
876 return -EINVAL;
877 }
878
879 // start the lock
880 switch (state->demod_type) {
881 case TDA1004X_DEMOD_TDA10045:
882 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
883 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
884 break;
885
886 case TDA1004X_DEMOD_TDA10046:
887 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
888 msleep(1);
889 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
890 break;
891 }
892
893 msleep(10);
894
895 return 0;
896 }
897
tda1004x_get_fe(struct dvb_frontend * fe)898 static int tda1004x_get_fe(struct dvb_frontend *fe)
899 {
900 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
901 struct tda1004x_state* state = fe->demodulator_priv;
902
903 dprintk("%s\n", __func__);
904
905 // inversion status
906 fe_params->inversion = INVERSION_OFF;
907 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
908 fe_params->inversion = INVERSION_ON;
909 if (state->config->invert)
910 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
911
912 // bandwidth
913 switch (state->demod_type) {
914 case TDA1004X_DEMOD_TDA10045:
915 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
916 case 0x14:
917 fe_params->bandwidth_hz = 8000000;
918 break;
919 case 0xdb:
920 fe_params->bandwidth_hz = 7000000;
921 break;
922 case 0x4f:
923 fe_params->bandwidth_hz = 6000000;
924 break;
925 }
926 break;
927 case TDA1004X_DEMOD_TDA10046:
928 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
929 case 0x5c:
930 case 0x54:
931 fe_params->bandwidth_hz = 8000000;
932 break;
933 case 0x6a:
934 case 0x60:
935 fe_params->bandwidth_hz = 7000000;
936 break;
937 case 0x7b:
938 case 0x70:
939 fe_params->bandwidth_hz = 6000000;
940 break;
941 }
942 break;
943 }
944
945 // FEC
946 fe_params->code_rate_HP =
947 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
948 fe_params->code_rate_LP =
949 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
950
951 /* modulation */
952 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
953 case 0:
954 fe_params->modulation = QPSK;
955 break;
956 case 1:
957 fe_params->modulation = QAM_16;
958 break;
959 case 2:
960 fe_params->modulation = QAM_64;
961 break;
962 }
963
964 // transmission mode
965 fe_params->transmission_mode = TRANSMISSION_MODE_2K;
966 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
967 fe_params->transmission_mode = TRANSMISSION_MODE_8K;
968
969 // guard interval
970 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
971 case 0:
972 fe_params->guard_interval = GUARD_INTERVAL_1_32;
973 break;
974 case 1:
975 fe_params->guard_interval = GUARD_INTERVAL_1_16;
976 break;
977 case 2:
978 fe_params->guard_interval = GUARD_INTERVAL_1_8;
979 break;
980 case 3:
981 fe_params->guard_interval = GUARD_INTERVAL_1_4;
982 break;
983 }
984
985 // hierarchy
986 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
987 case 0:
988 fe_params->hierarchy = HIERARCHY_NONE;
989 break;
990 case 1:
991 fe_params->hierarchy = HIERARCHY_1;
992 break;
993 case 2:
994 fe_params->hierarchy = HIERARCHY_2;
995 break;
996 case 3:
997 fe_params->hierarchy = HIERARCHY_4;
998 break;
999 }
1000
1001 return 0;
1002 }
1003
tda1004x_read_status(struct dvb_frontend * fe,fe_status_t * fe_status)1004 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
1005 {
1006 struct tda1004x_state* state = fe->demodulator_priv;
1007 int status;
1008 int cber;
1009 int vber;
1010
1011 dprintk("%s\n", __func__);
1012
1013 // read status
1014 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1015 if (status == -1)
1016 return -EIO;
1017
1018 // decode
1019 *fe_status = 0;
1020 if (status & 4)
1021 *fe_status |= FE_HAS_SIGNAL;
1022 if (status & 2)
1023 *fe_status |= FE_HAS_CARRIER;
1024 if (status & 8)
1025 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1026
1027 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1028 // is getting anything valid
1029 if (!(*fe_status & FE_HAS_VITERBI)) {
1030 // read the CBER
1031 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1032 if (cber == -1)
1033 return -EIO;
1034 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1035 if (status == -1)
1036 return -EIO;
1037 cber |= (status << 8);
1038 // The address 0x20 should be read to cope with a TDA10046 bug
1039 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1040
1041 if (cber != 65535)
1042 *fe_status |= FE_HAS_VITERBI;
1043 }
1044
1045 // if we DO have some valid VITERBI output, but don't already have SYNC
1046 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1047 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1048 // read the VBER
1049 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1050 if (vber == -1)
1051 return -EIO;
1052 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1053 if (status == -1)
1054 return -EIO;
1055 vber |= (status << 8);
1056 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1057 if (status == -1)
1058 return -EIO;
1059 vber |= (status & 0x0f) << 16;
1060 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1061 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1062
1063 // if RS has passed some valid TS packets, then we must be
1064 // getting some SYNC bytes
1065 if (vber < 16632)
1066 *fe_status |= FE_HAS_SYNC;
1067 }
1068
1069 // success
1070 dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
1071 return 0;
1072 }
1073
tda1004x_read_signal_strength(struct dvb_frontend * fe,u16 * signal)1074 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1075 {
1076 struct tda1004x_state* state = fe->demodulator_priv;
1077 int tmp;
1078 int reg = 0;
1079
1080 dprintk("%s\n", __func__);
1081
1082 // determine the register to use
1083 switch (state->demod_type) {
1084 case TDA1004X_DEMOD_TDA10045:
1085 reg = TDA10045H_S_AGC;
1086 break;
1087
1088 case TDA1004X_DEMOD_TDA10046:
1089 reg = TDA10046H_AGC_IF_LEVEL;
1090 break;
1091 }
1092
1093 // read it
1094 tmp = tda1004x_read_byte(state, reg);
1095 if (tmp < 0)
1096 return -EIO;
1097
1098 *signal = (tmp << 8) | tmp;
1099 dprintk("%s: signal=0x%x\n", __func__, *signal);
1100 return 0;
1101 }
1102
tda1004x_read_snr(struct dvb_frontend * fe,u16 * snr)1103 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1104 {
1105 struct tda1004x_state* state = fe->demodulator_priv;
1106 int tmp;
1107
1108 dprintk("%s\n", __func__);
1109
1110 // read it
1111 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1112 if (tmp < 0)
1113 return -EIO;
1114 tmp = 255 - tmp;
1115
1116 *snr = ((tmp << 8) | tmp);
1117 dprintk("%s: snr=0x%x\n", __func__, *snr);
1118 return 0;
1119 }
1120
tda1004x_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)1121 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1122 {
1123 struct tda1004x_state* state = fe->demodulator_priv;
1124 int tmp;
1125 int tmp2;
1126 int counter;
1127
1128 dprintk("%s\n", __func__);
1129
1130 // read the UCBLOCKS and reset
1131 counter = 0;
1132 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1133 if (tmp < 0)
1134 return -EIO;
1135 tmp &= 0x7f;
1136 while (counter++ < 5) {
1137 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1138 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1139 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1140
1141 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1142 if (tmp2 < 0)
1143 return -EIO;
1144 tmp2 &= 0x7f;
1145 if ((tmp2 < tmp) || (tmp2 == 0))
1146 break;
1147 }
1148
1149 if (tmp != 0x7f)
1150 *ucblocks = tmp;
1151 else
1152 *ucblocks = 0xffffffff;
1153
1154 dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
1155 return 0;
1156 }
1157
tda1004x_read_ber(struct dvb_frontend * fe,u32 * ber)1158 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1159 {
1160 struct tda1004x_state* state = fe->demodulator_priv;
1161 int tmp;
1162
1163 dprintk("%s\n", __func__);
1164
1165 // read it in
1166 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1167 if (tmp < 0)
1168 return -EIO;
1169 *ber = tmp << 1;
1170 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1171 if (tmp < 0)
1172 return -EIO;
1173 *ber |= (tmp << 9);
1174 // The address 0x20 should be read to cope with a TDA10046 bug
1175 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1176
1177 dprintk("%s: ber=0x%x\n", __func__, *ber);
1178 return 0;
1179 }
1180
tda1004x_sleep(struct dvb_frontend * fe)1181 static int tda1004x_sleep(struct dvb_frontend* fe)
1182 {
1183 struct tda1004x_state* state = fe->demodulator_priv;
1184 int gpio_conf;
1185
1186 switch (state->demod_type) {
1187 case TDA1004X_DEMOD_TDA10045:
1188 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1189 break;
1190
1191 case TDA1004X_DEMOD_TDA10046:
1192 /* set outputs to tristate */
1193 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1194 /* invert GPIO 1 and 3 if desired*/
1195 gpio_conf = state->config->gpio_config;
1196 if (gpio_conf >= TDA10046_GP00_I)
1197 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1198 (gpio_conf & 0x0f) ^ 0x0a);
1199
1200 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1201 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1202 break;
1203 }
1204
1205 return 0;
1206 }
1207
tda1004x_i2c_gate_ctrl(struct dvb_frontend * fe,int enable)1208 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1209 {
1210 struct tda1004x_state* state = fe->demodulator_priv;
1211
1212 if (enable) {
1213 return tda1004x_enable_tuner_i2c(state);
1214 } else {
1215 return tda1004x_disable_tuner_i2c(state);
1216 }
1217 }
1218
tda1004x_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fesettings)1219 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1220 {
1221 fesettings->min_delay_ms = 800;
1222 /* Drift compensation makes no sense for DVB-T */
1223 fesettings->step_size = 0;
1224 fesettings->max_drift = 0;
1225 return 0;
1226 }
1227
tda1004x_release(struct dvb_frontend * fe)1228 static void tda1004x_release(struct dvb_frontend* fe)
1229 {
1230 struct tda1004x_state *state = fe->demodulator_priv;
1231 kfree(state);
1232 }
1233
1234 static struct dvb_frontend_ops tda10045_ops = {
1235 .delsys = { SYS_DVBT },
1236 .info = {
1237 .name = "Philips TDA10045H DVB-T",
1238 .frequency_min = 51000000,
1239 .frequency_max = 858000000,
1240 .frequency_stepsize = 166667,
1241 .caps =
1242 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1243 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1244 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1245 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1246 },
1247
1248 .release = tda1004x_release,
1249
1250 .init = tda10045_init,
1251 .sleep = tda1004x_sleep,
1252 .write = tda1004x_write,
1253 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1254
1255 .set_frontend = tda1004x_set_fe,
1256 .get_frontend = tda1004x_get_fe,
1257 .get_tune_settings = tda1004x_get_tune_settings,
1258
1259 .read_status = tda1004x_read_status,
1260 .read_ber = tda1004x_read_ber,
1261 .read_signal_strength = tda1004x_read_signal_strength,
1262 .read_snr = tda1004x_read_snr,
1263 .read_ucblocks = tda1004x_read_ucblocks,
1264 };
1265
tda10045_attach(const struct tda1004x_config * config,struct i2c_adapter * i2c)1266 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1267 struct i2c_adapter* i2c)
1268 {
1269 struct tda1004x_state *state;
1270 int id;
1271
1272 /* allocate memory for the internal state */
1273 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1274 if (!state) {
1275 printk(KERN_ERR "Can't alocate memory for tda10045 state\n");
1276 return NULL;
1277 }
1278
1279 /* setup the state */
1280 state->config = config;
1281 state->i2c = i2c;
1282 state->demod_type = TDA1004X_DEMOD_TDA10045;
1283
1284 /* check if the demod is there */
1285 id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1286 if (id < 0) {
1287 printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
1288 kfree(state);
1289 return NULL;
1290 }
1291
1292 if (id != 0x25) {
1293 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1294 kfree(state);
1295 return NULL;
1296 }
1297
1298 /* create dvb_frontend */
1299 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1300 state->frontend.demodulator_priv = state;
1301 return &state->frontend;
1302 }
1303
1304 static struct dvb_frontend_ops tda10046_ops = {
1305 .delsys = { SYS_DVBT },
1306 .info = {
1307 .name = "Philips TDA10046H DVB-T",
1308 .frequency_min = 51000000,
1309 .frequency_max = 858000000,
1310 .frequency_stepsize = 166667,
1311 .caps =
1312 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1313 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1314 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1315 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1316 },
1317
1318 .release = tda1004x_release,
1319
1320 .init = tda10046_init,
1321 .sleep = tda1004x_sleep,
1322 .write = tda1004x_write,
1323 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1324
1325 .set_frontend = tda1004x_set_fe,
1326 .get_frontend = tda1004x_get_fe,
1327 .get_tune_settings = tda1004x_get_tune_settings,
1328
1329 .read_status = tda1004x_read_status,
1330 .read_ber = tda1004x_read_ber,
1331 .read_signal_strength = tda1004x_read_signal_strength,
1332 .read_snr = tda1004x_read_snr,
1333 .read_ucblocks = tda1004x_read_ucblocks,
1334 };
1335
tda10046_attach(const struct tda1004x_config * config,struct i2c_adapter * i2c)1336 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1337 struct i2c_adapter* i2c)
1338 {
1339 struct tda1004x_state *state;
1340 int id;
1341
1342 /* allocate memory for the internal state */
1343 state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1344 if (!state) {
1345 printk(KERN_ERR "Can't alocate memory for tda10046 state\n");
1346 return NULL;
1347 }
1348
1349 /* setup the state */
1350 state->config = config;
1351 state->i2c = i2c;
1352 state->demod_type = TDA1004X_DEMOD_TDA10046;
1353
1354 /* check if the demod is there */
1355 id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1356 if (id < 0) {
1357 printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
1358 kfree(state);
1359 return NULL;
1360 }
1361 if (id != 0x46) {
1362 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1363 kfree(state);
1364 return NULL;
1365 }
1366
1367 /* create dvb_frontend */
1368 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1369 state->frontend.demodulator_priv = state;
1370 return &state->frontend;
1371 }
1372
1373 module_param(debug, int, 0644);
1374 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1375
1376 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1377 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1378 MODULE_LICENSE("GPL");
1379
1380 EXPORT_SYMBOL(tda10045_attach);
1381 EXPORT_SYMBOL(tda10046_attach);
1382