1 /*
2 * Driver for Quantek QT1010 silicon tuner
3 *
4 * Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
5 * Aapo Tahkola <aet@rasterburn.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21 #include "qt1010.h"
22 #include "qt1010_priv.h"
23
24 static int debug;
25 module_param(debug, int, 0644);
26 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
27
28 #define dprintk(args...) \
29 do { \
30 if (debug) printk(KERN_DEBUG "QT1010: " args); \
31 } while (0)
32
33 /* read single register */
qt1010_readreg(struct qt1010_priv * priv,u8 reg,u8 * val)34 static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
35 {
36 struct i2c_msg msg[2] = {
37 { .addr = priv->cfg->i2c_address,
38 .flags = 0, .buf = ®, .len = 1 },
39 { .addr = priv->cfg->i2c_address,
40 .flags = I2C_M_RD, .buf = val, .len = 1 },
41 };
42
43 if (i2c_transfer(priv->i2c, msg, 2) != 2) {
44 printk(KERN_WARNING "qt1010 I2C read failed\n");
45 return -EREMOTEIO;
46 }
47 return 0;
48 }
49
50 /* write single register */
qt1010_writereg(struct qt1010_priv * priv,u8 reg,u8 val)51 static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
52 {
53 u8 buf[2] = { reg, val };
54 struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
55 .flags = 0, .buf = buf, .len = 2 };
56
57 if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
58 printk(KERN_WARNING "qt1010 I2C write failed\n");
59 return -EREMOTEIO;
60 }
61 return 0;
62 }
63
64 /* dump all registers */
qt1010_dump_regs(struct qt1010_priv * priv)65 static void qt1010_dump_regs(struct qt1010_priv *priv)
66 {
67 u8 reg, val;
68
69 for (reg = 0; ; reg++) {
70 if (reg % 16 == 0) {
71 if (reg)
72 printk(KERN_CONT "\n");
73 printk(KERN_DEBUG "%02x:", reg);
74 }
75 if (qt1010_readreg(priv, reg, &val) == 0)
76 printk(KERN_CONT " %02x", val);
77 else
78 printk(KERN_CONT " --");
79 if (reg == 0x2f)
80 break;
81 }
82 printk(KERN_CONT "\n");
83 }
84
qt1010_set_params(struct dvb_frontend * fe)85 static int qt1010_set_params(struct dvb_frontend *fe)
86 {
87 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
88 struct qt1010_priv *priv;
89 int err;
90 u32 freq, div, mod1, mod2;
91 u8 i, tmpval, reg05;
92 qt1010_i2c_oper_t rd[48] = {
93 { QT1010_WR, 0x01, 0x80 },
94 { QT1010_WR, 0x02, 0x3f },
95 { QT1010_WR, 0x05, 0xff }, /* 02 c write */
96 { QT1010_WR, 0x06, 0x44 },
97 { QT1010_WR, 0x07, 0xff }, /* 04 c write */
98 { QT1010_WR, 0x08, 0x08 },
99 { QT1010_WR, 0x09, 0xff }, /* 06 c write */
100 { QT1010_WR, 0x0a, 0xff }, /* 07 c write */
101 { QT1010_WR, 0x0b, 0xff }, /* 08 c write */
102 { QT1010_WR, 0x0c, 0xe1 },
103 { QT1010_WR, 0x1a, 0xff }, /* 10 c write */
104 { QT1010_WR, 0x1b, 0x00 },
105 { QT1010_WR, 0x1c, 0x89 },
106 { QT1010_WR, 0x11, 0xff }, /* 13 c write */
107 { QT1010_WR, 0x12, 0xff }, /* 14 c write */
108 { QT1010_WR, 0x22, 0xff }, /* 15 c write */
109 { QT1010_WR, 0x1e, 0x00 },
110 { QT1010_WR, 0x1e, 0xd0 },
111 { QT1010_RD, 0x22, 0xff }, /* 16 c read */
112 { QT1010_WR, 0x1e, 0x00 },
113 { QT1010_RD, 0x05, 0xff }, /* 20 c read */
114 { QT1010_RD, 0x22, 0xff }, /* 21 c read */
115 { QT1010_WR, 0x23, 0xd0 },
116 { QT1010_WR, 0x1e, 0x00 },
117 { QT1010_WR, 0x1e, 0xe0 },
118 { QT1010_RD, 0x23, 0xff }, /* 25 c read */
119 { QT1010_RD, 0x23, 0xff }, /* 26 c read */
120 { QT1010_WR, 0x1e, 0x00 },
121 { QT1010_WR, 0x24, 0xd0 },
122 { QT1010_WR, 0x1e, 0x00 },
123 { QT1010_WR, 0x1e, 0xf0 },
124 { QT1010_RD, 0x24, 0xff }, /* 31 c read */
125 { QT1010_WR, 0x1e, 0x00 },
126 { QT1010_WR, 0x14, 0x7f },
127 { QT1010_WR, 0x15, 0x7f },
128 { QT1010_WR, 0x05, 0xff }, /* 35 c write */
129 { QT1010_WR, 0x06, 0x00 },
130 { QT1010_WR, 0x15, 0x1f },
131 { QT1010_WR, 0x16, 0xff },
132 { QT1010_WR, 0x18, 0xff },
133 { QT1010_WR, 0x1f, 0xff }, /* 40 c write */
134 { QT1010_WR, 0x20, 0xff }, /* 41 c write */
135 { QT1010_WR, 0x21, 0x53 },
136 { QT1010_WR, 0x25, 0xff }, /* 43 c write */
137 { QT1010_WR, 0x26, 0x15 },
138 { QT1010_WR, 0x00, 0xff }, /* 45 c write */
139 { QT1010_WR, 0x02, 0x00 },
140 { QT1010_WR, 0x01, 0x00 }
141 };
142
143 #define FREQ1 32000000 /* 32 MHz */
144 #define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */
145
146 priv = fe->tuner_priv;
147 freq = c->frequency;
148 div = (freq + QT1010_OFFSET) / QT1010_STEP;
149 freq = (div * QT1010_STEP) - QT1010_OFFSET;
150 mod1 = (freq + QT1010_OFFSET) % FREQ1;
151 mod2 = (freq + QT1010_OFFSET) % FREQ2;
152 priv->frequency = freq;
153
154 if (fe->ops.i2c_gate_ctrl)
155 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
156
157 /* reg 05 base value */
158 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */
159 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
160 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
161 else reg05 = 0x74;
162
163 /* 0x5 */
164 rd[2].val = reg05;
165
166 /* 07 - set frequency: 32 MHz scale */
167 rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
168
169 /* 09 - changes every 8/24 MHz */
170 if (mod1 < 8000000) rd[6].val = 0x1d;
171 else rd[6].val = 0x1c;
172
173 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */
174 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */
175 else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */
176 else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */
177 else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
178 else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
179 else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
180 else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
181 else rd[7].val = 0x0a; /* +28 MHz */
182
183 /* 0b - changes every 2/2 MHz */
184 if (mod2 < 2000000) rd[8].val = 0x45;
185 else rd[8].val = 0x44;
186
187 /* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
188 tmpval = 0x78; /* byte, overflows intentionally */
189 rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
190
191 /* 11 */
192 rd[13].val = 0xfd; /* TODO: correct value calculation */
193
194 /* 12 */
195 rd[14].val = 0x91; /* TODO: correct value calculation */
196
197 /* 22 */
198 if (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
199 else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
200 else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
201 else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
202 else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
203 else rd[15].val = 0xd0;
204
205 /* 05 */
206 rd[35].val = (reg05 & 0xf0);
207
208 /* 1f */
209 if (mod1 < 8000000) tmpval = 0x00;
210 else if (mod1 < 12000000) tmpval = 0x01;
211 else if (mod1 < 16000000) tmpval = 0x02;
212 else if (mod1 < 24000000) tmpval = 0x03;
213 else if (mod1 < 28000000) tmpval = 0x04;
214 else tmpval = 0x05;
215 rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
216
217 /* 20 */
218 if (mod1 < 8000000) tmpval = 0x00;
219 else if (mod1 < 12000000) tmpval = 0x01;
220 else if (mod1 < 20000000) tmpval = 0x02;
221 else if (mod1 < 24000000) tmpval = 0x03;
222 else if (mod1 < 28000000) tmpval = 0x04;
223 else tmpval = 0x05;
224 rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
225
226 /* 25 */
227 rd[43].val = priv->reg25_init_val;
228
229 /* 00 */
230 rd[45].val = 0x92; /* TODO: correct value calculation */
231
232 dprintk("freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \
233 "1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \
234 "20:%02x 25:%02x 00:%02x", \
235 freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, rd[8].val, \
236 rd[10].val, rd[13].val, rd[14].val, rd[15].val, rd[35].val, \
237 rd[40].val, rd[41].val, rd[43].val, rd[45].val);
238
239 for (i = 0; i < ARRAY_SIZE(rd); i++) {
240 if (rd[i].oper == QT1010_WR) {
241 err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
242 } else { /* read is required to proper locking */
243 err = qt1010_readreg(priv, rd[i].reg, &tmpval);
244 }
245 if (err) return err;
246 }
247
248 if (debug)
249 qt1010_dump_regs(priv);
250
251 if (fe->ops.i2c_gate_ctrl)
252 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
253
254 return 0;
255 }
256
qt1010_init_meas1(struct qt1010_priv * priv,u8 oper,u8 reg,u8 reg_init_val,u8 * retval)257 static int qt1010_init_meas1(struct qt1010_priv *priv,
258 u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
259 {
260 u8 i, val1, val2;
261 int err;
262
263 qt1010_i2c_oper_t i2c_data[] = {
264 { QT1010_WR, reg, reg_init_val },
265 { QT1010_WR, 0x1e, 0x00 },
266 { QT1010_WR, 0x1e, oper },
267 { QT1010_RD, reg, 0xff }
268 };
269
270 for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
271 if (i2c_data[i].oper == QT1010_WR) {
272 err = qt1010_writereg(priv, i2c_data[i].reg,
273 i2c_data[i].val);
274 } else {
275 err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
276 }
277 if (err) return err;
278 }
279
280 do {
281 val1 = val2;
282 err = qt1010_readreg(priv, reg, &val2);
283 if (err) return err;
284 dprintk("compare reg:%02x %02x %02x", reg, val1, val2);
285 } while (val1 != val2);
286 *retval = val1;
287
288 return qt1010_writereg(priv, 0x1e, 0x00);
289 }
290
qt1010_init_meas2(struct qt1010_priv * priv,u8 reg_init_val,u8 * retval)291 static u8 qt1010_init_meas2(struct qt1010_priv *priv,
292 u8 reg_init_val, u8 *retval)
293 {
294 u8 i, val;
295 int err;
296 qt1010_i2c_oper_t i2c_data[] = {
297 { QT1010_WR, 0x07, reg_init_val },
298 { QT1010_WR, 0x22, 0xd0 },
299 { QT1010_WR, 0x1e, 0x00 },
300 { QT1010_WR, 0x1e, 0xd0 },
301 { QT1010_RD, 0x22, 0xff },
302 { QT1010_WR, 0x1e, 0x00 },
303 { QT1010_WR, 0x22, 0xff }
304 };
305 for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
306 if (i2c_data[i].oper == QT1010_WR) {
307 err = qt1010_writereg(priv, i2c_data[i].reg,
308 i2c_data[i].val);
309 } else {
310 err = qt1010_readreg(priv, i2c_data[i].reg, &val);
311 }
312 if (err) return err;
313 }
314 *retval = val;
315 return 0;
316 }
317
qt1010_init(struct dvb_frontend * fe)318 static int qt1010_init(struct dvb_frontend *fe)
319 {
320 struct qt1010_priv *priv = fe->tuner_priv;
321 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
322 int err = 0;
323 u8 i, tmpval, *valptr = NULL;
324
325 qt1010_i2c_oper_t i2c_data[] = {
326 { QT1010_WR, 0x01, 0x80 },
327 { QT1010_WR, 0x0d, 0x84 },
328 { QT1010_WR, 0x0e, 0xb7 },
329 { QT1010_WR, 0x2a, 0x23 },
330 { QT1010_WR, 0x2c, 0xdc },
331 { QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
332 { QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
333 { QT1010_WR, 0x2b, 0x70 },
334 { QT1010_WR, 0x2a, 0x23 },
335 { QT1010_M1, 0x26, 0x08 },
336 { QT1010_M1, 0x82, 0xff },
337 { QT1010_WR, 0x05, 0x14 },
338 { QT1010_WR, 0x06, 0x44 },
339 { QT1010_WR, 0x07, 0x28 },
340 { QT1010_WR, 0x08, 0x0b },
341 { QT1010_WR, 0x11, 0xfd },
342 { QT1010_M1, 0x22, 0x0d },
343 { QT1010_M1, 0xd0, 0xff },
344 { QT1010_WR, 0x06, 0x40 },
345 { QT1010_WR, 0x16, 0xf0 },
346 { QT1010_WR, 0x02, 0x38 },
347 { QT1010_WR, 0x03, 0x18 },
348 { QT1010_WR, 0x20, 0xe0 },
349 { QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
350 { QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
351 { QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
352 { QT1010_WR, 0x03, 0x19 },
353 { QT1010_WR, 0x02, 0x3f },
354 { QT1010_WR, 0x21, 0x53 },
355 { QT1010_RD, 0x21, 0xff },
356 { QT1010_WR, 0x11, 0xfd },
357 { QT1010_WR, 0x05, 0x34 },
358 { QT1010_WR, 0x06, 0x44 },
359 { QT1010_WR, 0x08, 0x08 }
360 };
361
362 if (fe->ops.i2c_gate_ctrl)
363 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
364
365 for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
366 switch (i2c_data[i].oper) {
367 case QT1010_WR:
368 err = qt1010_writereg(priv, i2c_data[i].reg,
369 i2c_data[i].val);
370 break;
371 case QT1010_RD:
372 if (i2c_data[i].val == 0x20)
373 valptr = &priv->reg20_init_val;
374 else
375 valptr = &tmpval;
376 err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
377 break;
378 case QT1010_M1:
379 if (i2c_data[i].val == 0x25)
380 valptr = &priv->reg25_init_val;
381 else if (i2c_data[i].val == 0x1f)
382 valptr = &priv->reg1f_init_val;
383 else
384 valptr = &tmpval;
385 err = qt1010_init_meas1(priv, i2c_data[i+1].reg,
386 i2c_data[i].reg,
387 i2c_data[i].val, valptr);
388 i++;
389 break;
390 }
391 if (err) return err;
392 }
393
394 for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
395 if ((err = qt1010_init_meas2(priv, i, &tmpval)))
396 return err;
397
398 c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
399 /* MSI Megasky 580 GL861 533000000 */
400 return qt1010_set_params(fe);
401 }
402
qt1010_release(struct dvb_frontend * fe)403 static int qt1010_release(struct dvb_frontend *fe)
404 {
405 kfree(fe->tuner_priv);
406 fe->tuner_priv = NULL;
407 return 0;
408 }
409
qt1010_get_frequency(struct dvb_frontend * fe,u32 * frequency)410 static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
411 {
412 struct qt1010_priv *priv = fe->tuner_priv;
413 *frequency = priv->frequency;
414 return 0;
415 }
416
qt1010_get_if_frequency(struct dvb_frontend * fe,u32 * frequency)417 static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
418 {
419 *frequency = 36125000;
420 return 0;
421 }
422
423 static const struct dvb_tuner_ops qt1010_tuner_ops = {
424 .info = {
425 .name = "Quantek QT1010",
426 .frequency_min = QT1010_MIN_FREQ,
427 .frequency_max = QT1010_MAX_FREQ,
428 .frequency_step = QT1010_STEP,
429 },
430
431 .release = qt1010_release,
432 .init = qt1010_init,
433 /* TODO: implement sleep */
434
435 .set_params = qt1010_set_params,
436 .get_frequency = qt1010_get_frequency,
437 .get_if_frequency = qt1010_get_if_frequency,
438 };
439
qt1010_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,struct qt1010_config * cfg)440 struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
441 struct i2c_adapter *i2c,
442 struct qt1010_config *cfg)
443 {
444 struct qt1010_priv *priv = NULL;
445 u8 id;
446
447 priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
448 if (priv == NULL)
449 return NULL;
450
451 priv->cfg = cfg;
452 priv->i2c = i2c;
453
454 if (fe->ops.i2c_gate_ctrl)
455 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
456
457
458 /* Try to detect tuner chip. Probably this is not correct register. */
459 if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
460 kfree(priv);
461 return NULL;
462 }
463
464 if (fe->ops.i2c_gate_ctrl)
465 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
466
467 printk(KERN_INFO "Quantek QT1010 successfully identified.\n");
468 memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops,
469 sizeof(struct dvb_tuner_ops));
470
471 fe->tuner_priv = priv;
472 return fe;
473 }
474 EXPORT_SYMBOL(qt1010_attach);
475
476 MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
477 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
478 MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
479 MODULE_VERSION("0.1");
480 MODULE_LICENSE("GPL");
481