1 /*
2  * Freescale MXS I2C bus driver
3  *
4  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
5  *
6  * based on a (non-working) driver which was:
7  *
8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  *
10  * TODO: add dma-support if platform-support for it is available
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  */
18 
19 #include <linux/slab.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/completion.h>
26 #include <linux/platform_device.h>
27 #include <linux/jiffies.h>
28 #include <linux/io.h>
29 
30 #include <mach/common.h>
31 
32 #define DRIVER_NAME "mxs-i2c"
33 
34 #define MXS_I2C_CTRL0		(0x00)
35 #define MXS_I2C_CTRL0_SET	(0x04)
36 
37 #define MXS_I2C_CTRL0_SFTRST			0x80000000
38 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST		0x02000000
39 #define MXS_I2C_CTRL0_RETAIN_CLOCK		0x00200000
40 #define MXS_I2C_CTRL0_POST_SEND_STOP		0x00100000
41 #define MXS_I2C_CTRL0_PRE_SEND_START		0x00080000
42 #define MXS_I2C_CTRL0_MASTER_MODE		0x00020000
43 #define MXS_I2C_CTRL0_DIRECTION			0x00010000
44 #define MXS_I2C_CTRL0_XFER_COUNT(v)		((v) & 0x0000FFFF)
45 
46 #define MXS_I2C_CTRL1		(0x40)
47 #define MXS_I2C_CTRL1_SET	(0x44)
48 #define MXS_I2C_CTRL1_CLR	(0x48)
49 
50 #define MXS_I2C_CTRL1_BUS_FREE_IRQ		0x80
51 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ	0x40
52 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ		0x20
53 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ	0x10
54 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ		0x08
55 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ		0x04
56 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ		0x02
57 #define MXS_I2C_CTRL1_SLAVE_IRQ			0x01
58 
59 #define MXS_I2C_IRQ_MASK	(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
60 				 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
61 				 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
62 				 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
63 				 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
64 				 MXS_I2C_CTRL1_SLAVE_IRQ)
65 
66 #define MXS_I2C_QUEUECTRL	(0x60)
67 #define MXS_I2C_QUEUECTRL_SET	(0x64)
68 #define MXS_I2C_QUEUECTRL_CLR	(0x68)
69 
70 #define MXS_I2C_QUEUECTRL_QUEUE_RUN		0x20
71 #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE	0x04
72 
73 #define MXS_I2C_QUEUESTAT	(0x70)
74 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY        0x00002000
75 #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK	0x0000001F
76 
77 #define MXS_I2C_QUEUECMD	(0x80)
78 
79 #define MXS_I2C_QUEUEDATA	(0x90)
80 
81 #define MXS_I2C_DATA		(0xa0)
82 
83 
84 #define MXS_CMD_I2C_SELECT	(MXS_I2C_CTRL0_RETAIN_CLOCK |	\
85 				 MXS_I2C_CTRL0_PRE_SEND_START |	\
86 				 MXS_I2C_CTRL0_MASTER_MODE |	\
87 				 MXS_I2C_CTRL0_DIRECTION |	\
88 				 MXS_I2C_CTRL0_XFER_COUNT(1))
89 
90 #define MXS_CMD_I2C_WRITE	(MXS_I2C_CTRL0_PRE_SEND_START |	\
91 				 MXS_I2C_CTRL0_MASTER_MODE |	\
92 				 MXS_I2C_CTRL0_DIRECTION)
93 
94 #define MXS_CMD_I2C_READ	(MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
95 				 MXS_I2C_CTRL0_MASTER_MODE)
96 
97 /**
98  * struct mxs_i2c_dev - per device, private MXS-I2C data
99  *
100  * @dev: driver model device node
101  * @regs: IO registers pointer
102  * @cmd_complete: completion object for transaction wait
103  * @cmd_err: error code for last transaction
104  * @adapter: i2c subsystem adapter node
105  */
106 struct mxs_i2c_dev {
107 	struct device *dev;
108 	void __iomem *regs;
109 	struct completion cmd_complete;
110 	u32 cmd_err;
111 	struct i2c_adapter adapter;
112 };
113 
114 /*
115  * TODO: check if calls to here are really needed. If not, we could get rid of
116  * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
117  */
mxs_i2c_reset(struct mxs_i2c_dev * i2c)118 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
119 {
120 	mxs_reset_block(i2c->regs);
121 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
122 	writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
123 			i2c->regs + MXS_I2C_QUEUECTRL_SET);
124 }
125 
mxs_i2c_pioq_setup_read(struct mxs_i2c_dev * i2c,u8 addr,int len,int flags)126 static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
127 					int flags)
128 {
129 	u32 data;
130 
131 	writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
132 
133 	data = (addr << 1) | I2C_SMBUS_READ;
134 	writel(data, i2c->regs + MXS_I2C_DATA);
135 
136 	data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
137 	writel(data, i2c->regs + MXS_I2C_QUEUECMD);
138 }
139 
mxs_i2c_pioq_setup_write(struct mxs_i2c_dev * i2c,u8 addr,u8 * buf,int len,int flags)140 static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
141 				    u8 addr, u8 *buf, int len, int flags)
142 {
143 	u32 data;
144 	int i, shifts_left;
145 
146 	data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
147 	writel(data, i2c->regs + MXS_I2C_QUEUECMD);
148 
149 	/*
150 	 * We have to copy the slave address (u8) and buffer (arbitrary number
151 	 * of u8) into the data register (u32). To achieve that, the u8 are put
152 	 * into the MSBs of 'data' which is then shifted for the next u8. When
153 	 * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
154 	 * looks like this:
155 	 *
156 	 *  3          2          1          0
157 	 * 10987654|32109876|54321098|76543210
158 	 * --------+--------+--------+--------
159 	 * buffer+2|buffer+1|buffer+0|slave_addr
160 	 */
161 
162 	data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
163 
164 	for (i = 0; i < len; i++) {
165 		data >>= 8;
166 		data |= buf[i] << 24;
167 		if ((i & 3) == 2)
168 			writel(data, i2c->regs + MXS_I2C_DATA);
169 	}
170 
171 	/* Write out the remaining bytes if any */
172 	shifts_left = 24 - (i & 3) * 8;
173 	if (shifts_left)
174 		writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
175 }
176 
177 /*
178  * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
179  * rd_threshold to 1). Couldn't get this to work, though.
180  */
mxs_i2c_wait_for_data(struct mxs_i2c_dev * i2c)181 static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
182 {
183 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
184 
185 	while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
186 			& MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
187 			if (time_after(jiffies, timeout))
188 				return -ETIMEDOUT;
189 			cond_resched();
190 	}
191 
192 	return 0;
193 }
194 
mxs_i2c_finish_read(struct mxs_i2c_dev * i2c,u8 * buf,int len)195 static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
196 {
197 	u32 data;
198 	int i;
199 
200 	for (i = 0; i < len; i++) {
201 		if ((i & 3) == 0) {
202 			if (mxs_i2c_wait_for_data(i2c))
203 				return -ETIMEDOUT;
204 			data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
205 		}
206 		buf[i] = data & 0xff;
207 		data >>= 8;
208 	}
209 
210 	return 0;
211 }
212 
213 /*
214  * Low level master read/write transaction.
215  */
mxs_i2c_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)216 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
217 				int stop)
218 {
219 	struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
220 	int ret;
221 	int flags;
222 
223 	dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
224 		msg->addr, msg->len, msg->flags, stop);
225 
226 	if (msg->len == 0)
227 		return -EINVAL;
228 
229 	init_completion(&i2c->cmd_complete);
230 
231 	flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
232 
233 	if (msg->flags & I2C_M_RD)
234 		mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
235 	else
236 		mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
237 					flags);
238 
239 	writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
240 			i2c->regs + MXS_I2C_QUEUECTRL_SET);
241 
242 	ret = wait_for_completion_timeout(&i2c->cmd_complete,
243 						msecs_to_jiffies(1000));
244 	if (ret == 0)
245 		goto timeout;
246 
247 	if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
248 		ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
249 		if (ret)
250 			goto timeout;
251 	}
252 
253 	if (i2c->cmd_err == -ENXIO)
254 		mxs_i2c_reset(i2c);
255 
256 	dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
257 
258 	return i2c->cmd_err;
259 
260 timeout:
261 	dev_dbg(i2c->dev, "Timeout!\n");
262 	mxs_i2c_reset(i2c);
263 	return -ETIMEDOUT;
264 }
265 
mxs_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)266 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
267 			int num)
268 {
269 	int i;
270 	int err;
271 
272 	for (i = 0; i < num; i++) {
273 		err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
274 		if (err)
275 			return err;
276 	}
277 
278 	return num;
279 }
280 
mxs_i2c_func(struct i2c_adapter * adap)281 static u32 mxs_i2c_func(struct i2c_adapter *adap)
282 {
283 	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
284 }
285 
mxs_i2c_isr(int this_irq,void * dev_id)286 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
287 {
288 	struct mxs_i2c_dev *i2c = dev_id;
289 	u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
290 	bool is_last_cmd;
291 
292 	if (!stat)
293 		return IRQ_NONE;
294 
295 	if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
296 		i2c->cmd_err = -ENXIO;
297 	else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
298 		    MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
299 		    MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
300 		/* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
301 		i2c->cmd_err = -EIO;
302 	else
303 		i2c->cmd_err = 0;
304 
305 	is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
306 		MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
307 
308 	if (is_last_cmd || i2c->cmd_err)
309 		complete(&i2c->cmd_complete);
310 
311 	writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
312 
313 	return IRQ_HANDLED;
314 }
315 
316 static const struct i2c_algorithm mxs_i2c_algo = {
317 	.master_xfer = mxs_i2c_xfer,
318 	.functionality = mxs_i2c_func,
319 };
320 
mxs_i2c_probe(struct platform_device * pdev)321 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
322 {
323 	struct device *dev = &pdev->dev;
324 	struct mxs_i2c_dev *i2c;
325 	struct i2c_adapter *adap;
326 	struct resource *res;
327 	resource_size_t res_size;
328 	int err, irq;
329 
330 	i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
331 	if (!i2c)
332 		return -ENOMEM;
333 
334 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
335 	if (!res)
336 		return -ENOENT;
337 
338 	res_size = resource_size(res);
339 	if (!devm_request_mem_region(dev, res->start, res_size, res->name))
340 		return -EBUSY;
341 
342 	i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
343 	if (!i2c->regs)
344 		return -EBUSY;
345 
346 	irq = platform_get_irq(pdev, 0);
347 	if (irq < 0)
348 		return irq;
349 
350 	err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
351 	if (err)
352 		return err;
353 
354 	i2c->dev = dev;
355 	platform_set_drvdata(pdev, i2c);
356 
357 	/* Do reset to enforce correct startup after pinmuxing */
358 	mxs_i2c_reset(i2c);
359 
360 	adap = &i2c->adapter;
361 	strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
362 	adap->owner = THIS_MODULE;
363 	adap->algo = &mxs_i2c_algo;
364 	adap->dev.parent = dev;
365 	adap->nr = pdev->id;
366 	i2c_set_adapdata(adap, i2c);
367 	err = i2c_add_numbered_adapter(adap);
368 	if (err) {
369 		dev_err(dev, "Failed to add adapter (%d)\n", err);
370 		writel(MXS_I2C_CTRL0_SFTRST,
371 				i2c->regs + MXS_I2C_CTRL0_SET);
372 		return err;
373 	}
374 
375 	return 0;
376 }
377 
mxs_i2c_remove(struct platform_device * pdev)378 static int __devexit mxs_i2c_remove(struct platform_device *pdev)
379 {
380 	struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
381 	int ret;
382 
383 	ret = i2c_del_adapter(&i2c->adapter);
384 	if (ret)
385 		return -EBUSY;
386 
387 	writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
388 			i2c->regs + MXS_I2C_QUEUECTRL_CLR);
389 	writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
390 
391 	platform_set_drvdata(pdev, NULL);
392 
393 	return 0;
394 }
395 
396 static struct platform_driver mxs_i2c_driver = {
397 	.driver = {
398 		   .name = DRIVER_NAME,
399 		   .owner = THIS_MODULE,
400 		   },
401 	.remove = __devexit_p(mxs_i2c_remove),
402 };
403 
mxs_i2c_init(void)404 static int __init mxs_i2c_init(void)
405 {
406 	return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
407 }
408 subsys_initcall(mxs_i2c_init);
409 
mxs_i2c_exit(void)410 static void __exit mxs_i2c_exit(void)
411 {
412 	platform_driver_unregister(&mxs_i2c_driver);
413 }
414 module_exit(mxs_i2c_exit);
415 
416 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
417 MODULE_DESCRIPTION("MXS I2C Bus Driver");
418 MODULE_LICENSE("GPL");
419 MODULE_ALIAS("platform:" DRIVER_NAME);
420