1 /*
2 * Support for Moorestown/Medfield I2C chip
3 *
4 * Copyright (c) 2009 Intel Corporation.
5 * Copyright (c) 2009 Synopsys. Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License, version
9 * 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
13 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc., 51
18 * Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/err.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27 #include <linux/delay.h>
28 #include <linux/i2c.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/interrupt.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/io.h>
34
35 #define DRIVER_NAME "i2c-intel-mid"
36 #define VERSION "Version 0.5ac2"
37 #define PLATFORM "Moorestown/Medfield"
38
39 /* Tables use: 0 Moorestown, 1 Medfield */
40 #define NUM_PLATFORMS 2
41 enum platform_enum {
42 MOORESTOWN = 0,
43 MEDFIELD = 1,
44 };
45
46 enum mid_i2c_status {
47 STATUS_IDLE = 0,
48 STATUS_READ_START,
49 STATUS_READ_IN_PROGRESS,
50 STATUS_READ_SUCCESS,
51 STATUS_WRITE_START,
52 STATUS_WRITE_SUCCESS,
53 STATUS_XFER_ABORT,
54 STATUS_STANDBY
55 };
56
57 /**
58 * struct intel_mid_i2c_private - per device I²C context
59 * @adap: core i2c layer adapter information
60 * @dev: device reference for power management
61 * @base: register base
62 * @speed: speed mode for this port
63 * @complete: completion object for transaction wait
64 * @abort: reason for last abort
65 * @rx_buf: pointer into working receive buffer
66 * @rx_buf_len: receive buffer length
67 * @status: adapter state machine
68 * @msg: the message we are currently processing
69 * @platform: the MID device type we are part of
70 * @lock: transaction serialization
71 *
72 * We allocate one of these per device we discover, it holds the core
73 * i2c layer objects and the data we need to track privately.
74 */
75 struct intel_mid_i2c_private {
76 struct i2c_adapter adap;
77 struct device *dev;
78 void __iomem *base;
79 int speed;
80 struct completion complete;
81 int abort;
82 u8 *rx_buf;
83 int rx_buf_len;
84 enum mid_i2c_status status;
85 struct i2c_msg *msg;
86 enum platform_enum platform;
87 struct mutex lock;
88 };
89
90 #define NUM_SPEEDS 3
91
92 #define ACTIVE 0
93 #define STANDBY 1
94
95
96 /* Control register */
97 #define IC_CON 0x00
98 #define SLV_DIS (1 << 6) /* Disable slave mode */
99 #define RESTART (1 << 5) /* Send a Restart condition */
100 #define ADDR_10BIT (1 << 4) /* 10-bit addressing */
101 #define STANDARD_MODE (1 << 1) /* standard mode */
102 #define FAST_MODE (2 << 1) /* fast mode */
103 #define HIGH_MODE (3 << 1) /* high speed mode */
104 #define MASTER_EN (1 << 0) /* Master mode */
105
106 /* Target address register */
107 #define IC_TAR 0x04
108 #define IC_TAR_10BIT_ADDR (1 << 12) /* 10-bit addressing */
109 #define IC_TAR_SPECIAL (1 << 11) /* Perform special I2C cmd */
110 #define IC_TAR_GC_OR_START (1 << 10) /* 0: Gerneral Call Address */
111 /* 1: START BYTE */
112 /* Slave Address Register */
113 #define IC_SAR 0x08 /* Not used in Master mode */
114
115 /* High Speed Master Mode Code Address Register */
116 #define IC_HS_MADDR 0x0c
117
118 /* Rx/Tx Data Buffer and Command Register */
119 #define IC_DATA_CMD 0x10
120 #define IC_RD (1 << 8) /* 1: Read 0: Write */
121
122 /* Standard Speed Clock SCL High Count Register */
123 #define IC_SS_SCL_HCNT 0x14
124
125 /* Standard Speed Clock SCL Low Count Register */
126 #define IC_SS_SCL_LCNT 0x18
127
128 /* Fast Speed Clock SCL High Count Register */
129 #define IC_FS_SCL_HCNT 0x1c
130
131 /* Fast Spedd Clock SCL Low Count Register */
132 #define IC_FS_SCL_LCNT 0x20
133
134 /* High Speed Clock SCL High Count Register */
135 #define IC_HS_SCL_HCNT 0x24
136
137 /* High Speed Clock SCL Low Count Register */
138 #define IC_HS_SCL_LCNT 0x28
139
140 /* Interrupt Status Register */
141 #define IC_INTR_STAT 0x2c /* Read only */
142 #define R_GEN_CALL (1 << 11)
143 #define R_START_DET (1 << 10)
144 #define R_STOP_DET (1 << 9)
145 #define R_ACTIVITY (1 << 8)
146 #define R_RX_DONE (1 << 7)
147 #define R_TX_ABRT (1 << 6)
148 #define R_RD_REQ (1 << 5)
149 #define R_TX_EMPTY (1 << 4)
150 #define R_TX_OVER (1 << 3)
151 #define R_RX_FULL (1 << 2)
152 #define R_RX_OVER (1 << 1)
153 #define R_RX_UNDER (1 << 0)
154
155 /* Interrupt Mask Register */
156 #define IC_INTR_MASK 0x30 /* Read and Write */
157 #define M_GEN_CALL (1 << 11)
158 #define M_START_DET (1 << 10)
159 #define M_STOP_DET (1 << 9)
160 #define M_ACTIVITY (1 << 8)
161 #define M_RX_DONE (1 << 7)
162 #define M_TX_ABRT (1 << 6)
163 #define M_RD_REQ (1 << 5)
164 #define M_TX_EMPTY (1 << 4)
165 #define M_TX_OVER (1 << 3)
166 #define M_RX_FULL (1 << 2)
167 #define M_RX_OVER (1 << 1)
168 #define M_RX_UNDER (1 << 0)
169
170 /* Raw Interrupt Status Register */
171 #define IC_RAW_INTR_STAT 0x34 /* Read Only */
172 #define GEN_CALL (1 << 11) /* General call */
173 #define START_DET (1 << 10) /* (RE)START occurred */
174 #define STOP_DET (1 << 9) /* STOP occurred */
175 #define ACTIVITY (1 << 8) /* Bus busy */
176 #define RX_DONE (1 << 7) /* Not used in Master mode */
177 #define TX_ABRT (1 << 6) /* Transmit Abort */
178 #define RD_REQ (1 << 5) /* Not used in Master mode */
179 #define TX_EMPTY (1 << 4) /* TX FIFO <= threshold */
180 #define TX_OVER (1 << 3) /* TX FIFO overflow */
181 #define RX_FULL (1 << 2) /* RX FIFO >= threshold */
182 #define RX_OVER (1 << 1) /* RX FIFO overflow */
183 #define RX_UNDER (1 << 0) /* RX FIFO empty */
184
185 /* Receive FIFO Threshold Register */
186 #define IC_RX_TL 0x38
187
188 /* Transmit FIFO Treshold Register */
189 #define IC_TX_TL 0x3c
190
191 /* Clear Combined and Individual Interrupt Register */
192 #define IC_CLR_INTR 0x40
193 #define CLR_INTR (1 << 0)
194
195 /* Clear RX_UNDER Interrupt Register */
196 #define IC_CLR_RX_UNDER 0x44
197 #define CLR_RX_UNDER (1 << 0)
198
199 /* Clear RX_OVER Interrupt Register */
200 #define IC_CLR_RX_OVER 0x48
201 #define CLR_RX_OVER (1 << 0)
202
203 /* Clear TX_OVER Interrupt Register */
204 #define IC_CLR_TX_OVER 0x4c
205 #define CLR_TX_OVER (1 << 0)
206
207 #define IC_CLR_RD_REQ 0x50
208
209 /* Clear TX_ABRT Interrupt Register */
210 #define IC_CLR_TX_ABRT 0x54
211 #define CLR_TX_ABRT (1 << 0)
212 #define IC_CLR_RX_DONE 0x58
213
214 /* Clear ACTIVITY Interrupt Register */
215 #define IC_CLR_ACTIVITY 0x5c
216 #define CLR_ACTIVITY (1 << 0)
217
218 /* Clear STOP_DET Interrupt Register */
219 #define IC_CLR_STOP_DET 0x60
220 #define CLR_STOP_DET (1 << 0)
221
222 /* Clear START_DET Interrupt Register */
223 #define IC_CLR_START_DET 0x64
224 #define CLR_START_DET (1 << 0)
225
226 /* Clear GEN_CALL Interrupt Register */
227 #define IC_CLR_GEN_CALL 0x68
228 #define CLR_GEN_CALL (1 << 0)
229
230 /* Enable Register */
231 #define IC_ENABLE 0x6c
232 #define ENABLE (1 << 0)
233
234 /* Status Register */
235 #define IC_STATUS 0x70 /* Read Only */
236 #define STAT_SLV_ACTIVITY (1 << 6) /* Slave not in idle */
237 #define STAT_MST_ACTIVITY (1 << 5) /* Master not in idle */
238 #define STAT_RFF (1 << 4) /* RX FIFO Full */
239 #define STAT_RFNE (1 << 3) /* RX FIFO Not Empty */
240 #define STAT_TFE (1 << 2) /* TX FIFO Empty */
241 #define STAT_TFNF (1 << 1) /* TX FIFO Not Full */
242 #define STAT_ACTIVITY (1 << 0) /* Activity Status */
243
244 /* Transmit FIFO Level Register */
245 #define IC_TXFLR 0x74 /* Read Only */
246 #define TXFLR (1 << 0) /* TX FIFO level */
247
248 /* Receive FIFO Level Register */
249 #define IC_RXFLR 0x78 /* Read Only */
250 #define RXFLR (1 << 0) /* RX FIFO level */
251
252 /* Transmit Abort Source Register */
253 #define IC_TX_ABRT_SOURCE 0x80
254 #define ABRT_SLVRD_INTX (1 << 15)
255 #define ABRT_SLV_ARBLOST (1 << 14)
256 #define ABRT_SLVFLUSH_TXFIFO (1 << 13)
257 #define ARB_LOST (1 << 12)
258 #define ABRT_MASTER_DIS (1 << 11)
259 #define ABRT_10B_RD_NORSTRT (1 << 10)
260 #define ABRT_SBYTE_NORSTRT (1 << 9)
261 #define ABRT_HS_NORSTRT (1 << 8)
262 #define ABRT_SBYTE_ACKDET (1 << 7)
263 #define ABRT_HS_ACKDET (1 << 6)
264 #define ABRT_GCALL_READ (1 << 5)
265 #define ABRT_GCALL_NOACK (1 << 4)
266 #define ABRT_TXDATA_NOACK (1 << 3)
267 #define ABRT_10ADDR2_NOACK (1 << 2)
268 #define ABRT_10ADDR1_NOACK (1 << 1)
269 #define ABRT_7B_ADDR_NOACK (1 << 0)
270
271 /* Enable Status Register */
272 #define IC_ENABLE_STATUS 0x9c
273 #define IC_EN (1 << 0) /* I2C in an enabled state */
274
275 /* Component Parameter Register 1*/
276 #define IC_COMP_PARAM_1 0xf4
277 #define APB_DATA_WIDTH (0x3 << 0)
278
279 /* added by xiaolin --begin */
280 #define SS_MIN_SCL_HIGH 4000
281 #define SS_MIN_SCL_LOW 4700
282 #define FS_MIN_SCL_HIGH 600
283 #define FS_MIN_SCL_LOW 1300
284 #define HS_MIN_SCL_HIGH_100PF 60
285 #define HS_MIN_SCL_LOW_100PF 120
286
287 #define STANDARD 0
288 #define FAST 1
289 #define HIGH 2
290
291 #define NUM_SPEEDS 3
292
293 static int speed_mode[6] = {
294 FAST,
295 FAST,
296 FAST,
297 STANDARD,
298 FAST,
299 FAST
300 };
301
302 static int ctl_num = 6;
303 module_param_array(speed_mode, int, &ctl_num, S_IRUGO);
304 MODULE_PARM_DESC(speed_mode, "Set the speed of the i2c interface (0-2)");
305
306 /**
307 * intel_mid_i2c_disable - Disable I2C controller
308 * @adap: struct pointer to i2c_adapter
309 *
310 * Return Value:
311 * 0 success
312 * -EBUSY if device is busy
313 * -ETIMEDOUT if i2c cannot be disabled within the given time
314 *
315 * I2C bus state should be checked prior to disabling the hardware. If bus is
316 * not in idle state, an errno is returned. Write "0" to IC_ENABLE to disable
317 * I2C controller.
318 */
intel_mid_i2c_disable(struct i2c_adapter * adap)319 static int intel_mid_i2c_disable(struct i2c_adapter *adap)
320 {
321 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
322 int err = 0;
323 int count = 0;
324 int ret1, ret2;
325 static const u16 delay[NUM_SPEEDS] = {100, 25, 3};
326
327 /* Set IC_ENABLE to 0 */
328 writel(0, i2c->base + IC_ENABLE);
329
330 /* Check if device is busy */
331 dev_dbg(&adap->dev, "mrst i2c disable\n");
332 while ((ret1 = readl(i2c->base + IC_ENABLE_STATUS) & 0x1)
333 || (ret2 = readl(i2c->base + IC_STATUS) & 0x1)) {
334 udelay(delay[i2c->speed]);
335 writel(0, i2c->base + IC_ENABLE);
336 dev_dbg(&adap->dev, "i2c is busy, count is %d speed %d\n",
337 count, i2c->speed);
338 if (count++ > 10) {
339 err = -ETIMEDOUT;
340 break;
341 }
342 }
343
344 /* Clear all interrupts */
345 readl(i2c->base + IC_CLR_INTR);
346 readl(i2c->base + IC_CLR_STOP_DET);
347 readl(i2c->base + IC_CLR_START_DET);
348 readl(i2c->base + IC_CLR_ACTIVITY);
349 readl(i2c->base + IC_CLR_TX_ABRT);
350 readl(i2c->base + IC_CLR_RX_OVER);
351 readl(i2c->base + IC_CLR_RX_UNDER);
352 readl(i2c->base + IC_CLR_TX_OVER);
353 readl(i2c->base + IC_CLR_RX_DONE);
354 readl(i2c->base + IC_CLR_GEN_CALL);
355
356 /* Disable all interupts */
357 writel(0x0000, i2c->base + IC_INTR_MASK);
358
359 return err;
360 }
361
362 /**
363 * intel_mid_i2c_hwinit - Initialize the I2C hardware registers
364 * @dev: pci device struct pointer
365 *
366 * This function will be called in intel_mid_i2c_probe() before device
367 * registration.
368 *
369 * Return Values:
370 * 0 success
371 * -EBUSY i2c cannot be disabled
372 * -ETIMEDOUT i2c cannot be disabled
373 * -EFAULT If APB data width is not 32-bit wide
374 *
375 * I2C should be disabled prior to other register operation. If failed, an
376 * errno is returned. Mask and Clear all interrpts, this should be done at
377 * first. Set common registers which will not be modified during normal
378 * transfers, including: control register, FIFO threshold and clock freq.
379 * Check APB data width at last.
380 */
intel_mid_i2c_hwinit(struct intel_mid_i2c_private * i2c)381 static int intel_mid_i2c_hwinit(struct intel_mid_i2c_private *i2c)
382 {
383 int err;
384
385 static const u16 hcnt[NUM_PLATFORMS][NUM_SPEEDS] = {
386 { 0x75, 0x15, 0x07 },
387 { 0x04c, 0x10, 0x06 }
388 };
389 static const u16 lcnt[NUM_PLATFORMS][NUM_SPEEDS] = {
390 { 0x7C, 0x21, 0x0E },
391 { 0x053, 0x19, 0x0F }
392 };
393
394 /* Disable i2c first */
395 err = intel_mid_i2c_disable(&i2c->adap);
396 if (err)
397 return err;
398
399 /*
400 * Setup clock frequency and speed mode
401 * Enable restart condition,
402 * enable master FSM, disable slave FSM,
403 * use target address when initiating transfer
404 */
405
406 writel((i2c->speed + 1) << 1 | SLV_DIS | RESTART | MASTER_EN,
407 i2c->base + IC_CON);
408 writel(hcnt[i2c->platform][i2c->speed],
409 i2c->base + (IC_SS_SCL_HCNT + (i2c->speed << 3)));
410 writel(lcnt[i2c->platform][i2c->speed],
411 i2c->base + (IC_SS_SCL_LCNT + (i2c->speed << 3)));
412
413 /* Set tranmit & receive FIFO threshold to zero */
414 writel(0x0, i2c->base + IC_RX_TL);
415 writel(0x0, i2c->base + IC_TX_TL);
416
417 return 0;
418 }
419
420 /**
421 * intel_mid_i2c_func - Return the supported three I2C operations.
422 * @adapter: i2c_adapter struct pointer
423 */
intel_mid_i2c_func(struct i2c_adapter * adapter)424 static u32 intel_mid_i2c_func(struct i2c_adapter *adapter)
425 {
426 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
427 }
428
429 /**
430 * intel_mid_i2c_address_neq - To check if the addresses for different i2c messages
431 * are equal.
432 * @p1: first i2c_msg
433 * @p2: second i2c_msg
434 *
435 * Return Values:
436 * 0 if addresses are equal
437 * 1 if not equal
438 *
439 * Within a single transfer, the I2C client may need to send its address more
440 * than once. So a check if the addresses match is needed.
441 */
intel_mid_i2c_address_neq(const struct i2c_msg * p1,const struct i2c_msg * p2)442 static inline bool intel_mid_i2c_address_neq(const struct i2c_msg *p1,
443 const struct i2c_msg *p2)
444 {
445 if (p1->addr != p2->addr)
446 return 1;
447 if ((p1->flags ^ p2->flags) & I2C_M_TEN)
448 return 1;
449 return 0;
450 }
451
452 /**
453 * intel_mid_i2c_abort - To handle transfer abortions and print error messages.
454 * @adap: i2c_adapter struct pointer
455 *
456 * By reading register IC_TX_ABRT_SOURCE, various transfer errors can be
457 * distingushed. At present, no circumstances have been found out that
458 * multiple errors would be occurred simutaneously, so we simply use the
459 * register value directly.
460 *
461 * At last the error bits are cleared. (Note clear ABRT_SBYTE_NORSTRT bit need
462 * a few extra steps)
463 */
intel_mid_i2c_abort(struct intel_mid_i2c_private * i2c)464 static void intel_mid_i2c_abort(struct intel_mid_i2c_private *i2c)
465 {
466 /* Read about source register */
467 int abort = i2c->abort;
468 struct i2c_adapter *adap = &i2c->adap;
469
470 /* Single transfer error check:
471 * According to databook, TX/RX FIFOs would be flushed when
472 * the abort interrupt occurred.
473 */
474 if (abort & ABRT_MASTER_DIS)
475 dev_err(&adap->dev,
476 "initiate master operation with master mode disabled.\n");
477 if (abort & ABRT_10B_RD_NORSTRT)
478 dev_err(&adap->dev,
479 "RESTART disabled and master sent READ cmd in 10-bit addressing.\n");
480
481 if (abort & ABRT_SBYTE_NORSTRT) {
482 dev_err(&adap->dev,
483 "RESTART disabled and user is trying to send START byte.\n");
484 writel(~ABRT_SBYTE_NORSTRT, i2c->base + IC_TX_ABRT_SOURCE);
485 writel(RESTART, i2c->base + IC_CON);
486 writel(~IC_TAR_SPECIAL, i2c->base + IC_TAR);
487 }
488
489 if (abort & ABRT_SBYTE_ACKDET)
490 dev_err(&adap->dev,
491 "START byte was not acknowledged.\n");
492 if (abort & ABRT_TXDATA_NOACK)
493 dev_dbg(&adap->dev,
494 "No acknowledgement received from slave.\n");
495 if (abort & ABRT_10ADDR2_NOACK)
496 dev_dbg(&adap->dev,
497 "The 2nd address byte of the 10-bit address was not acknowledged.\n");
498 if (abort & ABRT_10ADDR1_NOACK)
499 dev_dbg(&adap->dev,
500 "The 1st address byte of 10-bit address was not acknowledged.\n");
501 if (abort & ABRT_7B_ADDR_NOACK)
502 dev_dbg(&adap->dev,
503 "I2C slave device not acknowledged.\n");
504
505 /* Clear TX_ABRT bit */
506 readl(i2c->base + IC_CLR_TX_ABRT);
507 i2c->status = STATUS_XFER_ABORT;
508 }
509
510 /**
511 * xfer_read - Internal function to implement master read transfer.
512 * @adap: i2c_adapter struct pointer
513 * @buf: buffer in i2c_msg
514 * @length: number of bytes to be read
515 *
516 * Return Values:
517 * 0 if the read transfer succeeds
518 * -ETIMEDOUT if cannot read the "raw" interrupt register
519 * -EINVAL if a transfer abort occurred
520 *
521 * For every byte, a "READ" command will be loaded into IC_DATA_CMD prior to
522 * data transfer. The actual "read" operation will be performed if an RX_FULL
523 * interrupt occurred.
524 *
525 * Note there may be two interrupt signals captured, one should read
526 * IC_RAW_INTR_STAT to separate between errors and actual data.
527 */
xfer_read(struct i2c_adapter * adap,unsigned char * buf,int length)528 static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
529 {
530 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
531 int i = length;
532 int err;
533
534 if (length >= 256) {
535 dev_err(&adap->dev,
536 "I2C FIFO cannot support larger than 256 bytes\n");
537 return -EMSGSIZE;
538 }
539
540 INIT_COMPLETION(i2c->complete);
541
542 readl(i2c->base + IC_CLR_INTR);
543 writel(0x0044, i2c->base + IC_INTR_MASK);
544
545 i2c->status = STATUS_READ_START;
546
547 while (i--)
548 writel(IC_RD, i2c->base + IC_DATA_CMD);
549
550 i2c->status = STATUS_READ_START;
551 err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);
552 if (!err) {
553 dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");
554 intel_mid_i2c_hwinit(i2c);
555 return -ETIMEDOUT;
556 }
557 if (i2c->status == STATUS_READ_SUCCESS)
558 return 0;
559 else
560 return -EIO;
561 }
562
563 /**
564 * xfer_write - Internal function to implement master write transfer.
565 * @adap: i2c_adapter struct pointer
566 * @buf: buffer in i2c_msg
567 * @length: number of bytes to be read
568 *
569 * Return Values:
570 * 0 if the read transfer succeeds
571 * -ETIMEDOUT if we cannot read the "raw" interrupt register
572 * -EINVAL if a transfer abort occurred
573 *
574 * For every byte, a "WRITE" command will be loaded into IC_DATA_CMD prior to
575 * data transfer. The actual "write" operation will be performed when the
576 * RX_FULL interrupt signal occurs.
577 *
578 * Note there may be two interrupt signals captured, one should read
579 * IC_RAW_INTR_STAT to separate between errors and actual data.
580 */
xfer_write(struct i2c_adapter * adap,unsigned char * buf,int length)581 static int xfer_write(struct i2c_adapter *adap,
582 unsigned char *buf, int length)
583 {
584 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
585 int i, err;
586
587 if (length >= 256) {
588 dev_err(&adap->dev,
589 "I2C FIFO cannot support larger than 256 bytes\n");
590 return -EMSGSIZE;
591 }
592
593 INIT_COMPLETION(i2c->complete);
594
595 readl(i2c->base + IC_CLR_INTR);
596 writel(0x0050, i2c->base + IC_INTR_MASK);
597
598 i2c->status = STATUS_WRITE_START;
599 for (i = 0; i < length; i++)
600 writel((u16)(*(buf + i)), i2c->base + IC_DATA_CMD);
601
602 i2c->status = STATUS_WRITE_START;
603 err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);
604 if (!err) {
605 dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");
606 intel_mid_i2c_hwinit(i2c);
607 return -ETIMEDOUT;
608 } else {
609 if (i2c->status == STATUS_WRITE_SUCCESS)
610 return 0;
611 else
612 return -EIO;
613 }
614 }
615
intel_mid_i2c_setup(struct i2c_adapter * adap,struct i2c_msg * pmsg)616 static int intel_mid_i2c_setup(struct i2c_adapter *adap, struct i2c_msg *pmsg)
617 {
618 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
619 int err;
620 u32 reg;
621 u32 bit_mask;
622 u32 mode;
623
624 /* Disable device first */
625 err = intel_mid_i2c_disable(adap);
626 if (err) {
627 dev_err(&adap->dev,
628 "Cannot disable i2c controller, timeout\n");
629 return err;
630 }
631
632 mode = (1 + i2c->speed) << 1;
633 /* set the speed mode */
634 reg = readl(i2c->base + IC_CON);
635 if ((reg & 0x06) != mode) {
636 dev_dbg(&adap->dev, "set mode %d\n", i2c->speed);
637 writel((reg & ~0x6) | mode, i2c->base + IC_CON);
638 }
639
640 reg = readl(i2c->base + IC_CON);
641 /* use 7-bit addressing */
642 if (pmsg->flags & I2C_M_TEN) {
643 if ((reg & ADDR_10BIT) != ADDR_10BIT) {
644 dev_dbg(&adap->dev, "set i2c 10 bit address mode\n");
645 writel(reg | ADDR_10BIT, i2c->base + IC_CON);
646 }
647 } else {
648 if ((reg & ADDR_10BIT) != 0x0) {
649 dev_dbg(&adap->dev, "set i2c 7 bit address mode\n");
650 writel(reg & ~ADDR_10BIT, i2c->base + IC_CON);
651 }
652 }
653 /* enable restart conditions */
654 reg = readl(i2c->base + IC_CON);
655 if ((reg & RESTART) != RESTART) {
656 dev_dbg(&adap->dev, "enable restart conditions\n");
657 writel(reg | RESTART, i2c->base + IC_CON);
658 }
659
660 /* enable master FSM */
661 reg = readl(i2c->base + IC_CON);
662 dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg);
663 writel(reg | MASTER_EN, i2c->base + IC_CON);
664 if ((reg & SLV_DIS) != SLV_DIS) {
665 dev_dbg(&adap->dev, "enable master FSM\n");
666 writel(reg | SLV_DIS, i2c->base + IC_CON);
667 dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg);
668 }
669
670 /* use target address when initiating transfer */
671 reg = readl(i2c->base + IC_TAR);
672 bit_mask = IC_TAR_SPECIAL | IC_TAR_GC_OR_START;
673
674 if ((reg & bit_mask) != 0x0) {
675 dev_dbg(&adap->dev,
676 "WR: use target address when intiating transfer, i2c_tx_target\n");
677 writel(reg & ~bit_mask, i2c->base + IC_TAR);
678 }
679
680 /* set target address to the I2C slave address */
681 dev_dbg(&adap->dev,
682 "set target address to the I2C slave address, addr is %x\n",
683 pmsg->addr);
684 writel(pmsg->addr | (pmsg->flags & I2C_M_TEN ? IC_TAR_10BIT_ADDR : 0),
685 i2c->base + IC_TAR);
686
687 /* Enable I2C controller */
688 writel(ENABLE, i2c->base + IC_ENABLE);
689
690 return 0;
691 }
692
693 /**
694 * intel_mid_i2c_xfer - Main master transfer routine.
695 * @adap: i2c_adapter struct pointer
696 * @pmsg: i2c_msg struct pointer
697 * @num: number of i2c_msg
698 *
699 * Return Values:
700 * + number of messages transferred
701 * -ETIMEDOUT If cannot disable I2C controller or read IC_STATUS
702 * -EINVAL If the address in i2c_msg is invalid
703 *
704 * This function will be registered in i2c-core and exposed to external
705 * I2C clients.
706 * 1. Disable I2C controller
707 * 2. Unmask three interrupts: RX_FULL, TX_EMPTY, TX_ABRT
708 * 3. Check if address in i2c_msg is valid
709 * 4. Enable I2C controller
710 * 5. Perform real transfer (call xfer_read or xfer_write)
711 * 6. Wait until the current transfer is finished (check bus state)
712 * 7. Mask and clear all interrupts
713 */
intel_mid_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * pmsg,int num)714 static int intel_mid_i2c_xfer(struct i2c_adapter *adap,
715 struct i2c_msg *pmsg,
716 int num)
717 {
718 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
719 int i, err = 0;
720
721 /* if number of messages equal 0*/
722 if (num == 0)
723 return 0;
724
725 pm_runtime_get(i2c->dev);
726
727 mutex_lock(&i2c->lock);
728 dev_dbg(&adap->dev, "intel_mid_i2c_xfer, process %d msg(s)\n", num);
729 dev_dbg(&adap->dev, "slave address is %x\n", pmsg->addr);
730
731
732 if (i2c->status != STATUS_IDLE) {
733 dev_err(&adap->dev, "Adapter %d in transfer/standby\n",
734 adap->nr);
735 mutex_unlock(&i2c->lock);
736 pm_runtime_put(i2c->dev);
737 return -1;
738 }
739
740
741 for (i = 1; i < num; i++) {
742 /* Message address equal? */
743 if (unlikely(intel_mid_i2c_address_neq(&pmsg[0], &pmsg[i]))) {
744 dev_err(&adap->dev, "Invalid address in msg[%d]\n", i);
745 mutex_unlock(&i2c->lock);
746 pm_runtime_put(i2c->dev);
747 return -EINVAL;
748 }
749 }
750
751 if (intel_mid_i2c_setup(adap, pmsg)) {
752 mutex_unlock(&i2c->lock);
753 pm_runtime_put(i2c->dev);
754 return -EINVAL;
755 }
756
757 for (i = 0; i < num; i++) {
758 i2c->msg = pmsg;
759 i2c->status = STATUS_IDLE;
760 /* Read or Write */
761 if (pmsg->flags & I2C_M_RD) {
762 dev_dbg(&adap->dev, "I2C_M_RD\n");
763 err = xfer_read(adap, pmsg->buf, pmsg->len);
764 } else {
765 dev_dbg(&adap->dev, "I2C_M_WR\n");
766 err = xfer_write(adap, pmsg->buf, pmsg->len);
767 }
768 if (err < 0)
769 break;
770 dev_dbg(&adap->dev, "msg[%d] transfer complete\n", i);
771 pmsg++; /* next message */
772 }
773
774 /* Mask interrupts */
775 writel(0x0000, i2c->base + IC_INTR_MASK);
776 /* Clear all interrupts */
777 readl(i2c->base + IC_CLR_INTR);
778
779 i2c->status = STATUS_IDLE;
780 mutex_unlock(&i2c->lock);
781 pm_runtime_put(i2c->dev);
782
783 return err;
784 }
785
intel_mid_i2c_runtime_suspend(struct device * dev)786 static int intel_mid_i2c_runtime_suspend(struct device *dev)
787 {
788 struct pci_dev *pdev = to_pci_dev(dev);
789 struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);
790 struct i2c_adapter *adap = to_i2c_adapter(dev);
791 int err;
792
793 if (i2c->status != STATUS_IDLE)
794 return -1;
795
796 intel_mid_i2c_disable(adap);
797
798 err = pci_save_state(pdev);
799 if (err) {
800 dev_err(dev, "pci_save_state failed\n");
801 return err;
802 }
803
804 err = pci_set_power_state(pdev, PCI_D3hot);
805 if (err) {
806 dev_err(dev, "pci_set_power_state failed\n");
807 return err;
808 }
809 i2c->status = STATUS_STANDBY;
810
811 return 0;
812 }
813
intel_mid_i2c_runtime_resume(struct device * dev)814 static int intel_mid_i2c_runtime_resume(struct device *dev)
815 {
816 struct pci_dev *pdev = to_pci_dev(dev);
817 struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);
818 int err;
819
820 if (i2c->status != STATUS_STANDBY)
821 return 0;
822
823 pci_set_power_state(pdev, PCI_D0);
824 pci_restore_state(pdev);
825 err = pci_enable_device(pdev);
826 if (err) {
827 dev_err(dev, "pci_enable_device failed\n");
828 return err;
829 }
830
831 i2c->status = STATUS_IDLE;
832
833 intel_mid_i2c_hwinit(i2c);
834 return err;
835 }
836
i2c_isr_read(struct intel_mid_i2c_private * i2c)837 static void i2c_isr_read(struct intel_mid_i2c_private *i2c)
838 {
839 struct i2c_msg *msg = i2c->msg;
840 int rx_num;
841 u32 len;
842 u8 *buf;
843
844 if (!(msg->flags & I2C_M_RD))
845 return;
846
847 if (i2c->status != STATUS_READ_IN_PROGRESS) {
848 len = msg->len;
849 buf = msg->buf;
850 } else {
851 len = i2c->rx_buf_len;
852 buf = i2c->rx_buf;
853 }
854
855 rx_num = readl(i2c->base + IC_RXFLR);
856
857 for (; len > 0 && rx_num > 0; len--, rx_num--)
858 *buf++ = readl(i2c->base + IC_DATA_CMD);
859
860 if (len > 0) {
861 i2c->status = STATUS_READ_IN_PROGRESS;
862 i2c->rx_buf_len = len;
863 i2c->rx_buf = buf;
864 } else
865 i2c->status = STATUS_READ_SUCCESS;
866
867 return;
868 }
869
intel_mid_i2c_isr(int this_irq,void * dev)870 static irqreturn_t intel_mid_i2c_isr(int this_irq, void *dev)
871 {
872 struct intel_mid_i2c_private *i2c = dev;
873 u32 stat = readl(i2c->base + IC_INTR_STAT);
874
875 if (!stat)
876 return IRQ_NONE;
877
878 dev_dbg(&i2c->adap.dev, "%s, stat = 0x%x\n", __func__, stat);
879 stat &= 0x54;
880
881 if (i2c->status != STATUS_WRITE_START &&
882 i2c->status != STATUS_READ_START &&
883 i2c->status != STATUS_READ_IN_PROGRESS)
884 goto err;
885
886 if (stat & TX_ABRT)
887 i2c->abort = readl(i2c->base + IC_TX_ABRT_SOURCE);
888
889 readl(i2c->base + IC_CLR_INTR);
890
891 if (stat & TX_ABRT) {
892 intel_mid_i2c_abort(i2c);
893 goto exit;
894 }
895
896 if (stat & RX_FULL) {
897 i2c_isr_read(i2c);
898 goto exit;
899 }
900
901 if (stat & TX_EMPTY) {
902 if (readl(i2c->base + IC_STATUS) & 0x4)
903 i2c->status = STATUS_WRITE_SUCCESS;
904 }
905
906 exit:
907 if (i2c->status == STATUS_READ_SUCCESS ||
908 i2c->status == STATUS_WRITE_SUCCESS ||
909 i2c->status == STATUS_XFER_ABORT) {
910 /* Clear all interrupts */
911 readl(i2c->base + IC_CLR_INTR);
912 /* Mask interrupts */
913 writel(0, i2c->base + IC_INTR_MASK);
914 complete(&i2c->complete);
915 }
916 err:
917 return IRQ_HANDLED;
918 }
919
920 static struct i2c_algorithm intel_mid_i2c_algorithm = {
921 .master_xfer = intel_mid_i2c_xfer,
922 .functionality = intel_mid_i2c_func,
923 };
924
925
926 static const struct dev_pm_ops intel_mid_i2c_pm_ops = {
927 .runtime_suspend = intel_mid_i2c_runtime_suspend,
928 .runtime_resume = intel_mid_i2c_runtime_resume,
929 };
930
931 /**
932 * intel_mid_i2c_probe - I2C controller initialization routine
933 * @dev: pci device
934 * @id: device id
935 *
936 * Return Values:
937 * 0 success
938 * -ENODEV If cannot allocate pci resource
939 * -ENOMEM If the register base remapping failed, or
940 * if kzalloc failed
941 *
942 * Initialization steps:
943 * 1. Request for PCI resource
944 * 2. Remap the start address of PCI resource to register base
945 * 3. Request for device memory region
946 * 4. Fill in the struct members of intel_mid_i2c_private
947 * 5. Call intel_mid_i2c_hwinit() for hardware initialization
948 * 6. Register I2C adapter in i2c-core
949 */
intel_mid_i2c_probe(struct pci_dev * dev,const struct pci_device_id * id)950 static int __devinit intel_mid_i2c_probe(struct pci_dev *dev,
951 const struct pci_device_id *id)
952 {
953 struct intel_mid_i2c_private *mrst;
954 unsigned long start, len;
955 int err, busnum;
956 void __iomem *base = NULL;
957
958 dev_dbg(&dev->dev, "Get into probe function for I2C\n");
959 err = pci_enable_device(dev);
960 if (err) {
961 dev_err(&dev->dev, "Failed to enable I2C PCI device (%d)\n",
962 err);
963 goto exit;
964 }
965
966 /* Determine the address of the I2C area */
967 start = pci_resource_start(dev, 0);
968 len = pci_resource_len(dev, 0);
969 if (!start || len == 0) {
970 dev_err(&dev->dev, "base address not set\n");
971 err = -ENODEV;
972 goto exit;
973 }
974 dev_dbg(&dev->dev, "%s i2c resource start 0x%lx, len=%ld\n",
975 PLATFORM, start, len);
976
977 err = pci_request_region(dev, 0, DRIVER_NAME);
978 if (err) {
979 dev_err(&dev->dev, "failed to request I2C region "
980 "0x%lx-0x%lx\n", start,
981 (unsigned long)pci_resource_end(dev, 0));
982 goto exit;
983 }
984
985 base = ioremap_nocache(start, len);
986 if (!base) {
987 dev_err(&dev->dev, "I/O memory remapping failed\n");
988 err = -ENOMEM;
989 goto fail0;
990 }
991
992 /* Allocate the per-device data structure, intel_mid_i2c_private */
993 mrst = kzalloc(sizeof(struct intel_mid_i2c_private), GFP_KERNEL);
994 if (mrst == NULL) {
995 dev_err(&dev->dev, "can't allocate interface\n");
996 err = -ENOMEM;
997 goto fail1;
998 }
999
1000 /* Initialize struct members */
1001 snprintf(mrst->adap.name, sizeof(mrst->adap.name),
1002 "Intel MID I2C at %lx", start);
1003 mrst->adap.owner = THIS_MODULE;
1004 mrst->adap.algo = &intel_mid_i2c_algorithm;
1005 mrst->adap.dev.parent = &dev->dev;
1006 mrst->dev = &dev->dev;
1007 mrst->base = base;
1008 mrst->speed = STANDARD;
1009 mrst->abort = 0;
1010 mrst->rx_buf_len = 0;
1011 mrst->status = STATUS_IDLE;
1012
1013 pci_set_drvdata(dev, mrst);
1014 i2c_set_adapdata(&mrst->adap, mrst);
1015
1016 mrst->adap.nr = busnum = id->driver_data;
1017 if (dev->device <= 0x0804)
1018 mrst->platform = MOORESTOWN;
1019 else
1020 mrst->platform = MEDFIELD;
1021
1022 dev_dbg(&dev->dev, "I2C%d\n", busnum);
1023
1024 if (ctl_num > busnum) {
1025 if (speed_mode[busnum] < 0 || speed_mode[busnum] >= NUM_SPEEDS)
1026 dev_warn(&dev->dev, "invalid speed %d ignored.\n",
1027 speed_mode[busnum]);
1028 else
1029 mrst->speed = speed_mode[busnum];
1030 }
1031
1032 /* Initialize i2c controller */
1033 err = intel_mid_i2c_hwinit(mrst);
1034 if (err < 0) {
1035 dev_err(&dev->dev, "I2C interface initialization failed\n");
1036 goto fail2;
1037 }
1038
1039 mutex_init(&mrst->lock);
1040 init_completion(&mrst->complete);
1041
1042 /* Clear all interrupts */
1043 readl(mrst->base + IC_CLR_INTR);
1044 writel(0x0000, mrst->base + IC_INTR_MASK);
1045
1046 err = request_irq(dev->irq, intel_mid_i2c_isr, IRQF_SHARED,
1047 mrst->adap.name, mrst);
1048 if (err) {
1049 dev_err(&dev->dev, "Failed to request IRQ for I2C controller: "
1050 "%s", mrst->adap.name);
1051 goto fail2;
1052 }
1053
1054 /* Adapter registration */
1055 err = i2c_add_numbered_adapter(&mrst->adap);
1056 if (err) {
1057 dev_err(&dev->dev, "Adapter %s registration failed\n",
1058 mrst->adap.name);
1059 goto fail3;
1060 }
1061
1062 dev_dbg(&dev->dev, "%s I2C bus %d driver bind success.\n",
1063 (mrst->platform == MOORESTOWN) ? "Moorestown" : "Medfield",
1064 busnum);
1065
1066 pm_runtime_enable(&dev->dev);
1067 return 0;
1068
1069 fail3:
1070 free_irq(dev->irq, mrst);
1071 fail2:
1072 pci_set_drvdata(dev, NULL);
1073 kfree(mrst);
1074 fail1:
1075 iounmap(base);
1076 fail0:
1077 pci_release_region(dev, 0);
1078 exit:
1079 return err;
1080 }
1081
intel_mid_i2c_remove(struct pci_dev * dev)1082 static void __devexit intel_mid_i2c_remove(struct pci_dev *dev)
1083 {
1084 struct intel_mid_i2c_private *mrst = pci_get_drvdata(dev);
1085 intel_mid_i2c_disable(&mrst->adap);
1086 if (i2c_del_adapter(&mrst->adap))
1087 dev_err(&dev->dev, "Failed to delete i2c adapter");
1088
1089 free_irq(dev->irq, mrst);
1090 pci_set_drvdata(dev, NULL);
1091 iounmap(mrst->base);
1092 kfree(mrst);
1093 pci_release_region(dev, 0);
1094 }
1095
1096 static DEFINE_PCI_DEVICE_TABLE(intel_mid_i2c_ids) = {
1097 /* Moorestown */
1098 { PCI_VDEVICE(INTEL, 0x0802), 0 },
1099 { PCI_VDEVICE(INTEL, 0x0803), 1 },
1100 { PCI_VDEVICE(INTEL, 0x0804), 2 },
1101 /* Medfield */
1102 { PCI_VDEVICE(INTEL, 0x0817), 3,},
1103 { PCI_VDEVICE(INTEL, 0x0818), 4 },
1104 { PCI_VDEVICE(INTEL, 0x0819), 5 },
1105 { PCI_VDEVICE(INTEL, 0x082C), 0 },
1106 { PCI_VDEVICE(INTEL, 0x082D), 1 },
1107 { PCI_VDEVICE(INTEL, 0x082E), 2 },
1108 { 0,}
1109 };
1110 MODULE_DEVICE_TABLE(pci, intel_mid_i2c_ids);
1111
1112 static struct pci_driver intel_mid_i2c_driver = {
1113 .name = DRIVER_NAME,
1114 .id_table = intel_mid_i2c_ids,
1115 .probe = intel_mid_i2c_probe,
1116 .remove = __devexit_p(intel_mid_i2c_remove),
1117 };
1118
intel_mid_i2c_init(void)1119 static int __init intel_mid_i2c_init(void)
1120 {
1121 return pci_register_driver(&intel_mid_i2c_driver);
1122 }
1123
intel_mid_i2c_exit(void)1124 static void __exit intel_mid_i2c_exit(void)
1125 {
1126 pci_unregister_driver(&intel_mid_i2c_driver);
1127 }
1128
1129 module_init(intel_mid_i2c_init);
1130 module_exit(intel_mid_i2c_exit);
1131
1132 MODULE_AUTHOR("Ba Zheng <zheng.ba@intel.com>");
1133 MODULE_DESCRIPTION("I2C driver for Moorestown Platform");
1134 MODULE_LICENSE("GPL");
1135 MODULE_VERSION(VERSION);
1136