1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef EVERGREEND_H 25 #define EVERGREEND_H 26 27 #define EVERGREEN_MAX_SH_GPRS 256 28 #define EVERGREEN_MAX_TEMP_GPRS 16 29 #define EVERGREEN_MAX_SH_THREADS 256 30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384 32 #define EVERGREEN_MAX_BACKENDS 8 33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34 #define EVERGREEN_MAX_SIMDS 16 35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36 #define EVERGREEN_MAX_PIPES 8 37 #define EVERGREEN_MAX_PIPES_MASK 0xFF 38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40 /* Registers */ 41 42 #define RCU_IND_INDEX 0x100 43 #define RCU_IND_DATA 0x104 44 45 #define GRBM_GFX_INDEX 0x802C 46 #define INSTANCE_INDEX(x) ((x) << 0) 47 #define SE_INDEX(x) ((x) << 16) 48 #define INSTANCE_BROADCAST_WRITES (1 << 30) 49 #define SE_BROADCAST_WRITES (1 << 31) 50 #define RLC_GFX_INDEX 0x3fC4 51 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 52 #define WRITE_DIS (1 << 0) 53 #define CC_RB_BACKEND_DISABLE 0x98F4 54 #define BACKEND_DISABLE(x) ((x) << 16) 55 #define GB_ADDR_CONFIG 0x98F8 56 #define NUM_PIPES(x) ((x) << 0) 57 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 58 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 59 #define NUM_SHADER_ENGINES(x) ((x) << 12) 60 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 61 #define NUM_GPUS(x) ((x) << 20) 62 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 63 #define ROW_SIZE(x) ((x) << 28) 64 #define GB_BACKEND_MAP 0x98FC 65 #define DMIF_ADDR_CONFIG 0xBD4 66 #define HDP_ADDR_CONFIG 0x2F48 67 #define HDP_MISC_CNTL 0x2F4C 68 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 69 70 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 71 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 72 73 #define CGTS_SYS_TCC_DISABLE 0x3F90 74 #define CGTS_TCC_DISABLE 0x9148 75 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 76 #define CGTS_USER_TCC_DISABLE 0x914C 77 78 #define CONFIG_MEMSIZE 0x5428 79 80 #define CP_ME_CNTL 0x86D8 81 #define CP_ME_HALT (1 << 28) 82 #define CP_PFP_HALT (1 << 26) 83 #define CP_ME_RAM_DATA 0xC160 84 #define CP_ME_RAM_RADDR 0xC158 85 #define CP_ME_RAM_WADDR 0xC15C 86 #define CP_MEQ_THRESHOLDS 0x8764 87 #define STQ_SPLIT(x) ((x) << 0) 88 #define CP_PERFMON_CNTL 0x87FC 89 #define CP_PFP_UCODE_ADDR 0xC150 90 #define CP_PFP_UCODE_DATA 0xC154 91 #define CP_QUEUE_THRESHOLDS 0x8760 92 #define ROQ_IB1_START(x) ((x) << 0) 93 #define ROQ_IB2_START(x) ((x) << 8) 94 #define CP_RB_BASE 0xC100 95 #define CP_RB_CNTL 0xC104 96 #define RB_BUFSZ(x) ((x) << 0) 97 #define RB_BLKSZ(x) ((x) << 8) 98 #define RB_NO_UPDATE (1 << 27) 99 #define RB_RPTR_WR_ENA (1 << 31) 100 #define BUF_SWAP_32BIT (2 << 16) 101 #define CP_RB_RPTR 0x8700 102 #define CP_RB_RPTR_ADDR 0xC10C 103 #define RB_RPTR_SWAP(x) ((x) << 0) 104 #define CP_RB_RPTR_ADDR_HI 0xC110 105 #define CP_RB_RPTR_WR 0xC108 106 #define CP_RB_WPTR 0xC114 107 #define CP_RB_WPTR_ADDR 0xC118 108 #define CP_RB_WPTR_ADDR_HI 0xC11C 109 #define CP_RB_WPTR_DELAY 0x8704 110 #define CP_SEM_WAIT_TIMER 0x85BC 111 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 112 #define CP_DEBUG 0xC1FC 113 114 115 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 116 #define INACTIVE_QD_PIPES(x) ((x) << 8) 117 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 118 #define INACTIVE_SIMDS(x) ((x) << 16) 119 #define INACTIVE_SIMDS_MASK 0x00FF0000 120 121 #define GRBM_CNTL 0x8000 122 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 123 #define GRBM_SOFT_RESET 0x8020 124 #define SOFT_RESET_CP (1 << 0) 125 #define SOFT_RESET_CB (1 << 1) 126 #define SOFT_RESET_DB (1 << 3) 127 #define SOFT_RESET_PA (1 << 5) 128 #define SOFT_RESET_SC (1 << 6) 129 #define SOFT_RESET_SPI (1 << 8) 130 #define SOFT_RESET_SH (1 << 9) 131 #define SOFT_RESET_SX (1 << 10) 132 #define SOFT_RESET_TC (1 << 11) 133 #define SOFT_RESET_TA (1 << 12) 134 #define SOFT_RESET_VC (1 << 13) 135 #define SOFT_RESET_VGT (1 << 14) 136 137 #define GRBM_STATUS 0x8010 138 #define CMDFIFO_AVAIL_MASK 0x0000000F 139 #define SRBM_RQ_PENDING (1 << 5) 140 #define CF_RQ_PENDING (1 << 7) 141 #define PF_RQ_PENDING (1 << 8) 142 #define GRBM_EE_BUSY (1 << 10) 143 #define SX_CLEAN (1 << 11) 144 #define DB_CLEAN (1 << 12) 145 #define CB_CLEAN (1 << 13) 146 #define TA_BUSY (1 << 14) 147 #define VGT_BUSY_NO_DMA (1 << 16) 148 #define VGT_BUSY (1 << 17) 149 #define SX_BUSY (1 << 20) 150 #define SH_BUSY (1 << 21) 151 #define SPI_BUSY (1 << 22) 152 #define SC_BUSY (1 << 24) 153 #define PA_BUSY (1 << 25) 154 #define DB_BUSY (1 << 26) 155 #define CP_COHERENCY_BUSY (1 << 28) 156 #define CP_BUSY (1 << 29) 157 #define CB_BUSY (1 << 30) 158 #define GUI_ACTIVE (1 << 31) 159 #define GRBM_STATUS_SE0 0x8014 160 #define GRBM_STATUS_SE1 0x8018 161 #define SE_SX_CLEAN (1 << 0) 162 #define SE_DB_CLEAN (1 << 1) 163 #define SE_CB_CLEAN (1 << 2) 164 #define SE_TA_BUSY (1 << 25) 165 #define SE_SX_BUSY (1 << 26) 166 #define SE_SPI_BUSY (1 << 27) 167 #define SE_SH_BUSY (1 << 28) 168 #define SE_SC_BUSY (1 << 29) 169 #define SE_DB_BUSY (1 << 30) 170 #define SE_CB_BUSY (1 << 31) 171 /* evergreen */ 172 #define CG_THERMAL_CTRL 0x72c 173 #define TOFFSET_MASK 0x00003FE0 174 #define TOFFSET_SHIFT 5 175 #define CG_MULT_THERMAL_STATUS 0x740 176 #define ASIC_T(x) ((x) << 16) 177 #define ASIC_T_MASK 0x07FF0000 178 #define ASIC_T_SHIFT 16 179 #define CG_TS0_STATUS 0x760 180 #define TS0_ADC_DOUT_MASK 0x000003FF 181 #define TS0_ADC_DOUT_SHIFT 0 182 /* APU */ 183 #define CG_THERMAL_STATUS 0x678 184 185 #define HDP_HOST_PATH_CNTL 0x2C00 186 #define HDP_NONSURFACE_BASE 0x2C04 187 #define HDP_NONSURFACE_INFO 0x2C08 188 #define HDP_NONSURFACE_SIZE 0x2C0C 189 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 190 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 191 #define HDP_TILING_CONFIG 0x2F3C 192 193 #define MC_SHARED_CHMAP 0x2004 194 #define NOOFCHAN_SHIFT 12 195 #define NOOFCHAN_MASK 0x00003000 196 #define MC_SHARED_CHREMAP 0x2008 197 198 #define MC_ARB_RAMCFG 0x2760 199 #define NOOFBANK_SHIFT 0 200 #define NOOFBANK_MASK 0x00000003 201 #define NOOFRANK_SHIFT 2 202 #define NOOFRANK_MASK 0x00000004 203 #define NOOFROWS_SHIFT 3 204 #define NOOFROWS_MASK 0x00000038 205 #define NOOFCOLS_SHIFT 6 206 #define NOOFCOLS_MASK 0x000000C0 207 #define CHANSIZE_SHIFT 8 208 #define CHANSIZE_MASK 0x00000100 209 #define BURSTLENGTH_SHIFT 9 210 #define BURSTLENGTH_MASK 0x00000200 211 #define CHANSIZE_OVERRIDE (1 << 11) 212 #define FUS_MC_ARB_RAMCFG 0x2768 213 #define MC_VM_AGP_TOP 0x2028 214 #define MC_VM_AGP_BOT 0x202C 215 #define MC_VM_AGP_BASE 0x2030 216 #define MC_VM_FB_LOCATION 0x2024 217 #define MC_FUS_VM_FB_OFFSET 0x2898 218 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 219 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 220 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 221 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 222 #define ENABLE_L1_TLB (1 << 0) 223 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 224 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 225 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 226 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 227 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 228 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 229 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 230 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 231 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 232 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 233 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 234 235 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 236 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 237 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 238 239 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 240 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 241 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 242 243 #define PA_CL_ENHANCE 0x8A14 244 #define CLIP_VTX_REORDER_ENA (1 << 0) 245 #define NUM_CLIP_SEQ(x) ((x) << 1) 246 #define PA_SC_ENHANCE 0x8BF0 247 #define PA_SC_AA_CONFIG 0x28C04 248 #define MSAA_NUM_SAMPLES_SHIFT 0 249 #define MSAA_NUM_SAMPLES_MASK 0x3 250 #define PA_SC_CLIPRECT_RULE 0x2820C 251 #define PA_SC_EDGERULE 0x28230 252 #define PA_SC_FIFO_SIZE 0x8BCC 253 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 254 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 255 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 256 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 257 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 258 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 259 #define PA_SC_LINE_STIPPLE 0x28A0C 260 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 261 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 262 263 #define SCRATCH_REG0 0x8500 264 #define SCRATCH_REG1 0x8504 265 #define SCRATCH_REG2 0x8508 266 #define SCRATCH_REG3 0x850C 267 #define SCRATCH_REG4 0x8510 268 #define SCRATCH_REG5 0x8514 269 #define SCRATCH_REG6 0x8518 270 #define SCRATCH_REG7 0x851C 271 #define SCRATCH_UMSK 0x8540 272 #define SCRATCH_ADDR 0x8544 273 274 #define SMX_DC_CTL0 0xA020 275 #define USE_HASH_FUNCTION (1 << 0) 276 #define NUMBER_OF_SETS(x) ((x) << 1) 277 #define FLUSH_ALL_ON_EVENT (1 << 10) 278 #define STALL_ON_EVENT (1 << 11) 279 #define SMX_EVENT_CTL 0xA02C 280 #define ES_FLUSH_CTL(x) ((x) << 0) 281 #define GS_FLUSH_CTL(x) ((x) << 3) 282 #define ACK_FLUSH_CTL(x) ((x) << 6) 283 #define SYNC_FLUSH_CTL (1 << 8) 284 285 #define SPI_CONFIG_CNTL 0x9100 286 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 287 #define SPI_CONFIG_CNTL_1 0x913C 288 #define VTX_DONE_DELAY(x) ((x) << 0) 289 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 290 #define SPI_INPUT_Z 0x286D8 291 #define SPI_PS_IN_CONTROL_0 0x286CC 292 #define NUM_INTERP(x) ((x)<<0) 293 #define POSITION_ENA (1<<8) 294 #define POSITION_CENTROID (1<<9) 295 #define POSITION_ADDR(x) ((x)<<10) 296 #define PARAM_GEN(x) ((x)<<15) 297 #define PARAM_GEN_ADDR(x) ((x)<<19) 298 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 299 #define PERSP_GRADIENT_ENA (1<<28) 300 #define LINEAR_GRADIENT_ENA (1<<29) 301 #define POSITION_SAMPLE (1<<30) 302 #define BARYC_AT_SAMPLE_ENA (1<<31) 303 304 #define SQ_CONFIG 0x8C00 305 #define VC_ENABLE (1 << 0) 306 #define EXPORT_SRC_C (1 << 1) 307 #define CS_PRIO(x) ((x) << 18) 308 #define LS_PRIO(x) ((x) << 20) 309 #define HS_PRIO(x) ((x) << 22) 310 #define PS_PRIO(x) ((x) << 24) 311 #define VS_PRIO(x) ((x) << 26) 312 #define GS_PRIO(x) ((x) << 28) 313 #define ES_PRIO(x) ((x) << 30) 314 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 315 #define NUM_PS_GPRS(x) ((x) << 0) 316 #define NUM_VS_GPRS(x) ((x) << 16) 317 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 318 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 319 #define NUM_GS_GPRS(x) ((x) << 0) 320 #define NUM_ES_GPRS(x) ((x) << 16) 321 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 322 #define NUM_HS_GPRS(x) ((x) << 0) 323 #define NUM_LS_GPRS(x) ((x) << 16) 324 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 325 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 326 #define SQ_THREAD_RESOURCE_MGMT 0x8C18 327 #define NUM_PS_THREADS(x) ((x) << 0) 328 #define NUM_VS_THREADS(x) ((x) << 8) 329 #define NUM_GS_THREADS(x) ((x) << 16) 330 #define NUM_ES_THREADS(x) ((x) << 24) 331 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 332 #define NUM_HS_THREADS(x) ((x) << 0) 333 #define NUM_LS_THREADS(x) ((x) << 8) 334 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 335 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 336 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 337 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 338 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 339 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 340 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 341 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 342 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 343 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 344 #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 345 #define SQ_STATIC_THREAD_MGMT_1 0x8E20 346 #define SQ_STATIC_THREAD_MGMT_2 0x8E24 347 #define SQ_STATIC_THREAD_MGMT_3 0x8E28 348 #define SQ_LDS_RESOURCE_MGMT 0x8E2C 349 350 #define SQ_MS_FIFO_SIZES 0x8CF0 351 #define CACHE_FIFO_SIZE(x) ((x) << 0) 352 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 353 #define DONE_FIFO_HIWATER(x) ((x) << 16) 354 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 355 356 #define SX_DEBUG_1 0x9058 357 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 358 #define SX_EXPORT_BUFFER_SIZES 0x900C 359 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 360 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 361 #define SMX_BUFFER_SIZE(x) ((x) << 16) 362 #define SX_MEMORY_EXPORT_BASE 0x9010 363 #define SX_MISC 0x28350 364 365 #define CB_PERF_CTR0_SEL_0 0x9A20 366 #define CB_PERF_CTR0_SEL_1 0x9A24 367 #define CB_PERF_CTR1_SEL_0 0x9A28 368 #define CB_PERF_CTR1_SEL_1 0x9A2C 369 #define CB_PERF_CTR2_SEL_0 0x9A30 370 #define CB_PERF_CTR2_SEL_1 0x9A34 371 #define CB_PERF_CTR3_SEL_0 0x9A38 372 #define CB_PERF_CTR3_SEL_1 0x9A3C 373 374 #define TA_CNTL_AUX 0x9508 375 #define DISABLE_CUBE_WRAP (1 << 0) 376 #define DISABLE_CUBE_ANISO (1 << 1) 377 #define SYNC_GRADIENT (1 << 24) 378 #define SYNC_WALKER (1 << 25) 379 #define SYNC_ALIGNER (1 << 26) 380 381 #define TCP_CHAN_STEER_LO 0x960c 382 #define TCP_CHAN_STEER_HI 0x9610 383 384 #define VGT_CACHE_INVALIDATION 0x88C4 385 #define CACHE_INVALIDATION(x) ((x) << 0) 386 #define VC_ONLY 0 387 #define TC_ONLY 1 388 #define VC_AND_TC 2 389 #define AUTO_INVLD_EN(x) ((x) << 6) 390 #define NO_AUTO 0 391 #define ES_AUTO 1 392 #define GS_AUTO 2 393 #define ES_AND_GS_AUTO 3 394 #define VGT_GS_VERTEX_REUSE 0x88D4 395 #define VGT_NUM_INSTANCES 0x8974 396 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 397 #define DEALLOC_DIST_MASK 0x0000007F 398 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 399 #define VTX_REUSE_DEPTH_MASK 0x000000FF 400 401 #define VM_CONTEXT0_CNTL 0x1410 402 #define ENABLE_CONTEXT (1 << 0) 403 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 404 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 405 #define VM_CONTEXT1_CNTL 0x1414 406 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 407 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 408 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 409 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 410 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 411 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 412 #define RESPONSE_TYPE_MASK 0x000000F0 413 #define RESPONSE_TYPE_SHIFT 4 414 #define VM_L2_CNTL 0x1400 415 #define ENABLE_L2_CACHE (1 << 0) 416 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 417 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 418 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 419 #define VM_L2_CNTL2 0x1404 420 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 421 #define INVALIDATE_L2_CACHE (1 << 1) 422 #define VM_L2_CNTL3 0x1408 423 #define BANK_SELECT(x) ((x) << 0) 424 #define CACHE_UPDATE_MODE(x) ((x) << 6) 425 #define VM_L2_STATUS 0x140C 426 #define L2_BUSY (1 << 0) 427 428 #define WAIT_UNTIL 0x8040 429 430 #define SRBM_STATUS 0x0E50 431 #define SRBM_SOFT_RESET 0x0E60 432 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 433 #define SOFT_RESET_BIF (1 << 1) 434 #define SOFT_RESET_CG (1 << 2) 435 #define SOFT_RESET_DC (1 << 5) 436 #define SOFT_RESET_GRBM (1 << 8) 437 #define SOFT_RESET_HDP (1 << 9) 438 #define SOFT_RESET_IH (1 << 10) 439 #define SOFT_RESET_MC (1 << 11) 440 #define SOFT_RESET_RLC (1 << 13) 441 #define SOFT_RESET_ROM (1 << 14) 442 #define SOFT_RESET_SEM (1 << 15) 443 #define SOFT_RESET_VMC (1 << 17) 444 #define SOFT_RESET_TST (1 << 21) 445 #define SOFT_RESET_REGBB (1 << 22) 446 #define SOFT_RESET_ORB (1 << 23) 447 448 /* display watermarks */ 449 #define DC_LB_MEMORY_SPLIT 0x6b0c 450 #define PRIORITY_A_CNT 0x6b18 451 #define PRIORITY_MARK_MASK 0x7fff 452 #define PRIORITY_OFF (1 << 16) 453 #define PRIORITY_ALWAYS_ON (1 << 20) 454 #define PRIORITY_B_CNT 0x6b1c 455 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 456 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 457 #define PIPE0_LATENCY_CONTROL 0x0bf4 458 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 459 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 460 461 #define IH_RB_CNTL 0x3e00 462 # define IH_RB_ENABLE (1 << 0) 463 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 464 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 465 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 466 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 467 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 468 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 469 #define IH_RB_BASE 0x3e04 470 #define IH_RB_RPTR 0x3e08 471 #define IH_RB_WPTR 0x3e0c 472 # define RB_OVERFLOW (1 << 0) 473 # define WPTR_OFFSET_MASK 0x3fffc 474 #define IH_RB_WPTR_ADDR_HI 0x3e10 475 #define IH_RB_WPTR_ADDR_LO 0x3e14 476 #define IH_CNTL 0x3e18 477 # define ENABLE_INTR (1 << 0) 478 # define IH_MC_SWAP(x) ((x) << 1) 479 # define IH_MC_SWAP_NONE 0 480 # define IH_MC_SWAP_16BIT 1 481 # define IH_MC_SWAP_32BIT 2 482 # define IH_MC_SWAP_64BIT 3 483 # define RPTR_REARM (1 << 4) 484 # define MC_WRREQ_CREDIT(x) ((x) << 15) 485 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 486 487 #define CP_INT_CNTL 0xc124 488 # define CNTX_BUSY_INT_ENABLE (1 << 19) 489 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 490 # define SCRATCH_INT_ENABLE (1 << 25) 491 # define TIME_STAMP_INT_ENABLE (1 << 26) 492 # define IB2_INT_ENABLE (1 << 29) 493 # define IB1_INT_ENABLE (1 << 30) 494 # define RB_INT_ENABLE (1 << 31) 495 #define CP_INT_STATUS 0xc128 496 # define SCRATCH_INT_STAT (1 << 25) 497 # define TIME_STAMP_INT_STAT (1 << 26) 498 # define IB2_INT_STAT (1 << 29) 499 # define IB1_INT_STAT (1 << 30) 500 # define RB_INT_STAT (1 << 31) 501 502 #define GRBM_INT_CNTL 0x8060 503 # define RDERR_INT_ENABLE (1 << 0) 504 # define GUI_IDLE_INT_ENABLE (1 << 19) 505 506 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 507 #define CRTC_STATUS_FRAME_COUNT 0x6e98 508 509 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 510 #define VLINE_STATUS 0x6bb8 511 # define VLINE_OCCURRED (1 << 0) 512 # define VLINE_ACK (1 << 4) 513 # define VLINE_STAT (1 << 12) 514 # define VLINE_INTERRUPT (1 << 16) 515 # define VLINE_INTERRUPT_TYPE (1 << 17) 516 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 517 #define VBLANK_STATUS 0x6bbc 518 # define VBLANK_OCCURRED (1 << 0) 519 # define VBLANK_ACK (1 << 4) 520 # define VBLANK_STAT (1 << 12) 521 # define VBLANK_INTERRUPT (1 << 16) 522 # define VBLANK_INTERRUPT_TYPE (1 << 17) 523 524 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 525 #define INT_MASK 0x6b40 526 # define VBLANK_INT_MASK (1 << 0) 527 # define VLINE_INT_MASK (1 << 4) 528 529 #define DISP_INTERRUPT_STATUS 0x60f4 530 # define LB_D1_VLINE_INTERRUPT (1 << 2) 531 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 532 # define DC_HPD1_INTERRUPT (1 << 17) 533 # define DC_HPD1_RX_INTERRUPT (1 << 18) 534 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 535 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 536 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 537 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 538 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 539 # define LB_D2_VLINE_INTERRUPT (1 << 2) 540 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 541 # define DC_HPD2_INTERRUPT (1 << 17) 542 # define DC_HPD2_RX_INTERRUPT (1 << 18) 543 # define DISP_TIMER_INTERRUPT (1 << 24) 544 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 545 # define LB_D3_VLINE_INTERRUPT (1 << 2) 546 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 547 # define DC_HPD3_INTERRUPT (1 << 17) 548 # define DC_HPD3_RX_INTERRUPT (1 << 18) 549 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 550 # define LB_D4_VLINE_INTERRUPT (1 << 2) 551 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 552 # define DC_HPD4_INTERRUPT (1 << 17) 553 # define DC_HPD4_RX_INTERRUPT (1 << 18) 554 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 555 # define LB_D5_VLINE_INTERRUPT (1 << 2) 556 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 557 # define DC_HPD5_INTERRUPT (1 << 17) 558 # define DC_HPD5_RX_INTERRUPT (1 << 18) 559 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 560 # define LB_D6_VLINE_INTERRUPT (1 << 2) 561 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 562 # define DC_HPD6_INTERRUPT (1 << 17) 563 # define DC_HPD6_RX_INTERRUPT (1 << 18) 564 565 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 566 #define GRPH_INT_STATUS 0x6858 567 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 568 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 569 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 570 #define GRPH_INT_CONTROL 0x685c 571 # define GRPH_PFLIP_INT_MASK (1 << 0) 572 # define GRPH_PFLIP_INT_TYPE (1 << 8) 573 574 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 575 #define DACB_AUTODETECT_INT_CONTROL 0x67c8 576 577 #define DC_HPD1_INT_STATUS 0x601c 578 #define DC_HPD2_INT_STATUS 0x6028 579 #define DC_HPD3_INT_STATUS 0x6034 580 #define DC_HPD4_INT_STATUS 0x6040 581 #define DC_HPD5_INT_STATUS 0x604c 582 #define DC_HPD6_INT_STATUS 0x6058 583 # define DC_HPDx_INT_STATUS (1 << 0) 584 # define DC_HPDx_SENSE (1 << 1) 585 # define DC_HPDx_RX_INT_STATUS (1 << 8) 586 587 #define DC_HPD1_INT_CONTROL 0x6020 588 #define DC_HPD2_INT_CONTROL 0x602c 589 #define DC_HPD3_INT_CONTROL 0x6038 590 #define DC_HPD4_INT_CONTROL 0x6044 591 #define DC_HPD5_INT_CONTROL 0x6050 592 #define DC_HPD6_INT_CONTROL 0x605c 593 # define DC_HPDx_INT_ACK (1 << 0) 594 # define DC_HPDx_INT_POLARITY (1 << 8) 595 # define DC_HPDx_INT_EN (1 << 16) 596 # define DC_HPDx_RX_INT_ACK (1 << 20) 597 # define DC_HPDx_RX_INT_EN (1 << 24) 598 599 #define DC_HPD1_CONTROL 0x6024 600 #define DC_HPD2_CONTROL 0x6030 601 #define DC_HPD3_CONTROL 0x603c 602 #define DC_HPD4_CONTROL 0x6048 603 #define DC_HPD5_CONTROL 0x6054 604 #define DC_HPD6_CONTROL 0x6060 605 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 606 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 607 # define DC_HPDx_EN (1 << 28) 608 609 /* PCIE link stuff */ 610 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 611 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 612 # define LC_LINK_WIDTH_SHIFT 0 613 # define LC_LINK_WIDTH_MASK 0x7 614 # define LC_LINK_WIDTH_X0 0 615 # define LC_LINK_WIDTH_X1 1 616 # define LC_LINK_WIDTH_X2 2 617 # define LC_LINK_WIDTH_X4 3 618 # define LC_LINK_WIDTH_X8 4 619 # define LC_LINK_WIDTH_X16 6 620 # define LC_LINK_WIDTH_RD_SHIFT 4 621 # define LC_LINK_WIDTH_RD_MASK 0x70 622 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 623 # define LC_RECONFIG_NOW (1 << 8) 624 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 625 # define LC_RENEGOTIATE_EN (1 << 10) 626 # define LC_SHORT_RECONFIG_EN (1 << 11) 627 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 628 # define LC_UPCONFIGURE_DIS (1 << 13) 629 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 630 # define LC_GEN2_EN_STRAP (1 << 0) 631 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 632 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 633 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 634 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 635 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 636 # define LC_CURRENT_DATA_RATE (1 << 11) 637 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 638 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 639 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 640 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 641 #define MM_CFGREGS_CNTL 0x544c 642 # define MM_WR_TO_CFG_EN (1 << 3) 643 #define LINK_CNTL2 0x88 /* F0 */ 644 # define TARGET_LINK_SPEED_MASK (0xf << 0) 645 # define SELECTABLE_DEEMPHASIS (1 << 6) 646 647 /* 648 * PM4 649 */ 650 #define PACKET_TYPE0 0 651 #define PACKET_TYPE1 1 652 #define PACKET_TYPE2 2 653 #define PACKET_TYPE3 3 654 655 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 656 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 657 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 658 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 659 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 660 (((reg) >> 2) & 0xFFFF) | \ 661 ((n) & 0x3FFF) << 16) 662 #define CP_PACKET2 0x80000000 663 #define PACKET2_PAD_SHIFT 0 664 #define PACKET2_PAD_MASK (0x3fffffff << 0) 665 666 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 667 668 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 669 (((op) & 0xFF) << 8) | \ 670 ((n) & 0x3FFF) << 16) 671 672 /* Packet 3 types */ 673 #define PACKET3_NOP 0x10 674 #define PACKET3_SET_BASE 0x11 675 #define PACKET3_CLEAR_STATE 0x12 676 #define PACKET3_INDEX_BUFFER_SIZE 0x13 677 #define PACKET3_DISPATCH_DIRECT 0x15 678 #define PACKET3_DISPATCH_INDIRECT 0x16 679 #define PACKET3_INDIRECT_BUFFER_END 0x17 680 #define PACKET3_MODE_CONTROL 0x18 681 #define PACKET3_SET_PREDICATION 0x20 682 #define PACKET3_REG_RMW 0x21 683 #define PACKET3_COND_EXEC 0x22 684 #define PACKET3_PRED_EXEC 0x23 685 #define PACKET3_DRAW_INDIRECT 0x24 686 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 687 #define PACKET3_INDEX_BASE 0x26 688 #define PACKET3_DRAW_INDEX_2 0x27 689 #define PACKET3_CONTEXT_CONTROL 0x28 690 #define PACKET3_DRAW_INDEX_OFFSET 0x29 691 #define PACKET3_INDEX_TYPE 0x2A 692 #define PACKET3_DRAW_INDEX 0x2B 693 #define PACKET3_DRAW_INDEX_AUTO 0x2D 694 #define PACKET3_DRAW_INDEX_IMMD 0x2E 695 #define PACKET3_NUM_INSTANCES 0x2F 696 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 697 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 698 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 699 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 700 #define PACKET3_MEM_SEMAPHORE 0x39 701 #define PACKET3_MPEG_INDEX 0x3A 702 #define PACKET3_COPY_DW 0x3B 703 #define PACKET3_WAIT_REG_MEM 0x3C 704 #define PACKET3_MEM_WRITE 0x3D 705 #define PACKET3_INDIRECT_BUFFER 0x32 706 #define PACKET3_SURFACE_SYNC 0x43 707 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 708 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 709 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 710 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 711 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 712 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 713 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 714 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 715 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 716 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 717 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 718 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 719 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 720 # define PACKET3_FULL_CACHE_ENA (1 << 20) 721 # define PACKET3_TC_ACTION_ENA (1 << 23) 722 # define PACKET3_VC_ACTION_ENA (1 << 24) 723 # define PACKET3_CB_ACTION_ENA (1 << 25) 724 # define PACKET3_DB_ACTION_ENA (1 << 26) 725 # define PACKET3_SH_ACTION_ENA (1 << 27) 726 # define PACKET3_SX_ACTION_ENA (1 << 28) 727 #define PACKET3_ME_INITIALIZE 0x44 728 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 729 #define PACKET3_COND_WRITE 0x45 730 #define PACKET3_EVENT_WRITE 0x46 731 #define PACKET3_EVENT_WRITE_EOP 0x47 732 #define PACKET3_EVENT_WRITE_EOS 0x48 733 #define PACKET3_PREAMBLE_CNTL 0x4A 734 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 735 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 736 #define PACKET3_RB_OFFSET 0x4B 737 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 738 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 739 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 740 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 741 #define PACKET3_ONE_REG_WRITE 0x57 742 #define PACKET3_SET_CONFIG_REG 0x68 743 #define PACKET3_SET_CONFIG_REG_START 0x00008000 744 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 745 #define PACKET3_SET_CONTEXT_REG 0x69 746 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 747 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 748 #define PACKET3_SET_ALU_CONST 0x6A 749 /* alu const buffers only; no reg file */ 750 #define PACKET3_SET_BOOL_CONST 0x6B 751 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 752 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 753 #define PACKET3_SET_LOOP_CONST 0x6C 754 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 755 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 756 #define PACKET3_SET_RESOURCE 0x6D 757 #define PACKET3_SET_RESOURCE_START 0x00030000 758 #define PACKET3_SET_RESOURCE_END 0x00038000 759 #define PACKET3_SET_SAMPLER 0x6E 760 #define PACKET3_SET_SAMPLER_START 0x0003c000 761 #define PACKET3_SET_SAMPLER_END 0x0003c600 762 #define PACKET3_SET_CTL_CONST 0x6F 763 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 764 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 765 #define PACKET3_SET_RESOURCE_OFFSET 0x70 766 #define PACKET3_SET_ALU_CONST_VS 0x71 767 #define PACKET3_SET_ALU_CONST_DI 0x72 768 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 769 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 770 #define PACKET3_SET_APPEND_CNT 0x75 771 772 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 773 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 774 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 775 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 776 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 777 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 778 #define SQ_TEX_VTX_VALID_BUFFER 0x3 779 780 #define VGT_VTX_VECT_EJECT_REG 0x88b0 781 782 #define SQ_CONST_MEM_BASE 0x8df8 783 784 #define SQ_ESGS_RING_BASE 0x8c40 785 #define SQ_ESGS_RING_SIZE 0x8c44 786 #define SQ_GSVS_RING_BASE 0x8c48 787 #define SQ_GSVS_RING_SIZE 0x8c4c 788 #define SQ_ESTMP_RING_BASE 0x8c50 789 #define SQ_ESTMP_RING_SIZE 0x8c54 790 #define SQ_GSTMP_RING_BASE 0x8c58 791 #define SQ_GSTMP_RING_SIZE 0x8c5c 792 #define SQ_VSTMP_RING_BASE 0x8c60 793 #define SQ_VSTMP_RING_SIZE 0x8c64 794 #define SQ_PSTMP_RING_BASE 0x8c68 795 #define SQ_PSTMP_RING_SIZE 0x8c6c 796 #define SQ_LSTMP_RING_BASE 0x8e10 797 #define SQ_LSTMP_RING_SIZE 0x8e14 798 #define SQ_HSTMP_RING_BASE 0x8e18 799 #define SQ_HSTMP_RING_SIZE 0x8e1c 800 #define VGT_TF_RING_SIZE 0x8988 801 802 #define SQ_ESGS_RING_ITEMSIZE 0x28900 803 #define SQ_GSVS_RING_ITEMSIZE 0x28904 804 #define SQ_ESTMP_RING_ITEMSIZE 0x28908 805 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c 806 #define SQ_VSTMP_RING_ITEMSIZE 0x28910 807 #define SQ_PSTMP_RING_ITEMSIZE 0x28914 808 #define SQ_LSTMP_RING_ITEMSIZE 0x28830 809 #define SQ_HSTMP_RING_ITEMSIZE 0x28834 810 811 #define SQ_GS_VERT_ITEMSIZE 0x2891c 812 #define SQ_GS_VERT_ITEMSIZE_1 0x28920 813 #define SQ_GS_VERT_ITEMSIZE_2 0x28924 814 #define SQ_GS_VERT_ITEMSIZE_3 0x28928 815 #define SQ_GSVS_RING_OFFSET_1 0x2892c 816 #define SQ_GSVS_RING_OFFSET_2 0x28930 817 #define SQ_GSVS_RING_OFFSET_3 0x28934 818 819 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 820 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 821 822 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 823 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 824 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 825 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 826 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 827 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 828 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 829 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 830 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 831 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 832 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 833 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 834 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 835 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 836 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 837 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 838 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 839 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 840 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 841 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 842 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 843 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 844 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 845 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 846 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 847 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 848 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 849 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 850 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 851 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 852 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 853 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 854 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 855 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 856 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 857 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 858 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 859 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 860 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 861 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 862 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 863 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 864 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 865 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 866 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 867 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 868 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 869 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 870 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 871 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 872 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 873 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 874 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 875 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 876 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 877 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 878 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 879 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 880 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 881 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 882 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 883 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 884 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 885 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 886 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 887 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 888 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 889 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 890 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 891 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 892 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 893 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 894 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 895 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 896 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 897 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 898 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 899 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 900 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 901 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 902 903 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 904 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 905 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 906 907 #define VGT_PRIMITIVE_TYPE 0x8958 908 #define VGT_INDEX_TYPE 0x895C 909 910 #define VGT_NUM_INDICES 0x8970 911 912 #define VGT_COMPUTE_DIM_X 0x8990 913 #define VGT_COMPUTE_DIM_Y 0x8994 914 #define VGT_COMPUTE_DIM_Z 0x8998 915 #define VGT_COMPUTE_START_X 0x899C 916 #define VGT_COMPUTE_START_Y 0x89A0 917 #define VGT_COMPUTE_START_Z 0x89A4 918 #define VGT_COMPUTE_INDEX 0x89A8 919 #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 920 #define VGT_HS_OFFCHIP_PARAM 0x89B0 921 922 #define DB_DEBUG 0x9830 923 #define DB_DEBUG2 0x9834 924 #define DB_DEBUG3 0x9838 925 #define DB_DEBUG4 0x983C 926 #define DB_WATERMARKS 0x9854 927 #define DB_DEPTH_CONTROL 0x28800 928 #define DB_DEPTH_VIEW 0x28008 929 #define DB_HTILE_DATA_BASE 0x28014 930 #define DB_Z_INFO 0x28040 931 # define Z_ARRAY_MODE(x) ((x) << 4) 932 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 933 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 934 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 935 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 936 #define DB_STENCIL_INFO 0x28044 937 #define DB_Z_READ_BASE 0x28048 938 #define DB_STENCIL_READ_BASE 0x2804c 939 #define DB_Z_WRITE_BASE 0x28050 940 #define DB_STENCIL_WRITE_BASE 0x28054 941 #define DB_DEPTH_SIZE 0x28058 942 943 #define SQ_PGM_START_PS 0x28840 944 #define SQ_PGM_START_VS 0x2885c 945 #define SQ_PGM_START_GS 0x28874 946 #define SQ_PGM_START_ES 0x2888c 947 #define SQ_PGM_START_FS 0x288a4 948 #define SQ_PGM_START_HS 0x288b8 949 #define SQ_PGM_START_LS 0x288d0 950 951 #define VGT_STRMOUT_CONFIG 0x28b94 952 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 953 954 #define CB_TARGET_MASK 0x28238 955 #define CB_SHADER_MASK 0x2823c 956 957 #define GDS_ADDR_BASE 0x28720 958 959 #define CB_IMMED0_BASE 0x28b9c 960 #define CB_IMMED1_BASE 0x28ba0 961 #define CB_IMMED2_BASE 0x28ba4 962 #define CB_IMMED3_BASE 0x28ba8 963 #define CB_IMMED4_BASE 0x28bac 964 #define CB_IMMED5_BASE 0x28bb0 965 #define CB_IMMED6_BASE 0x28bb4 966 #define CB_IMMED7_BASE 0x28bb8 967 #define CB_IMMED8_BASE 0x28bbc 968 #define CB_IMMED9_BASE 0x28bc0 969 #define CB_IMMED10_BASE 0x28bc4 970 #define CB_IMMED11_BASE 0x28bc8 971 972 /* all 12 CB blocks have these regs */ 973 #define CB_COLOR0_BASE 0x28c60 974 #define CB_COLOR0_PITCH 0x28c64 975 #define CB_COLOR0_SLICE 0x28c68 976 #define CB_COLOR0_VIEW 0x28c6c 977 #define CB_COLOR0_INFO 0x28c70 978 # define CB_FORMAT(x) ((x) << 2) 979 # define CB_ARRAY_MODE(x) ((x) << 8) 980 # define ARRAY_LINEAR_GENERAL 0 981 # define ARRAY_LINEAR_ALIGNED 1 982 # define ARRAY_1D_TILED_THIN1 2 983 # define ARRAY_2D_TILED_THIN1 4 984 # define CB_SOURCE_FORMAT(x) ((x) << 24) 985 # define CB_SF_EXPORT_FULL 0 986 # define CB_SF_EXPORT_NORM 1 987 #define CB_COLOR0_ATTRIB 0x28c74 988 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 989 # define ADDR_SURF_TILE_SPLIT_64B 0 990 # define ADDR_SURF_TILE_SPLIT_128B 1 991 # define ADDR_SURF_TILE_SPLIT_256B 2 992 # define ADDR_SURF_TILE_SPLIT_512B 3 993 # define ADDR_SURF_TILE_SPLIT_1KB 4 994 # define ADDR_SURF_TILE_SPLIT_2KB 5 995 # define ADDR_SURF_TILE_SPLIT_4KB 6 996 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 997 # define ADDR_SURF_2_BANK 0 998 # define ADDR_SURF_4_BANK 1 999 # define ADDR_SURF_8_BANK 2 1000 # define ADDR_SURF_16_BANK 3 1001 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1002 # define ADDR_SURF_BANK_WIDTH_1 0 1003 # define ADDR_SURF_BANK_WIDTH_2 1 1004 # define ADDR_SURF_BANK_WIDTH_4 2 1005 # define ADDR_SURF_BANK_WIDTH_8 3 1006 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1007 # define ADDR_SURF_BANK_HEIGHT_1 0 1008 # define ADDR_SURF_BANK_HEIGHT_2 1 1009 # define ADDR_SURF_BANK_HEIGHT_4 2 1010 # define ADDR_SURF_BANK_HEIGHT_8 3 1011 #define CB_COLOR0_DIM 0x28c78 1012 /* only CB0-7 blocks have these regs */ 1013 #define CB_COLOR0_CMASK 0x28c7c 1014 #define CB_COLOR0_CMASK_SLICE 0x28c80 1015 #define CB_COLOR0_FMASK 0x28c84 1016 #define CB_COLOR0_FMASK_SLICE 0x28c88 1017 #define CB_COLOR0_CLEAR_WORD0 0x28c8c 1018 #define CB_COLOR0_CLEAR_WORD1 0x28c90 1019 #define CB_COLOR0_CLEAR_WORD2 0x28c94 1020 #define CB_COLOR0_CLEAR_WORD3 0x28c98 1021 1022 #define CB_COLOR1_BASE 0x28c9c 1023 #define CB_COLOR2_BASE 0x28cd8 1024 #define CB_COLOR3_BASE 0x28d14 1025 #define CB_COLOR4_BASE 0x28d50 1026 #define CB_COLOR5_BASE 0x28d8c 1027 #define CB_COLOR6_BASE 0x28dc8 1028 #define CB_COLOR7_BASE 0x28e04 1029 #define CB_COLOR8_BASE 0x28e40 1030 #define CB_COLOR9_BASE 0x28e5c 1031 #define CB_COLOR10_BASE 0x28e78 1032 #define CB_COLOR11_BASE 0x28e94 1033 1034 #define CB_COLOR1_PITCH 0x28ca0 1035 #define CB_COLOR2_PITCH 0x28cdc 1036 #define CB_COLOR3_PITCH 0x28d18 1037 #define CB_COLOR4_PITCH 0x28d54 1038 #define CB_COLOR5_PITCH 0x28d90 1039 #define CB_COLOR6_PITCH 0x28dcc 1040 #define CB_COLOR7_PITCH 0x28e08 1041 #define CB_COLOR8_PITCH 0x28e44 1042 #define CB_COLOR9_PITCH 0x28e60 1043 #define CB_COLOR10_PITCH 0x28e7c 1044 #define CB_COLOR11_PITCH 0x28e98 1045 1046 #define CB_COLOR1_SLICE 0x28ca4 1047 #define CB_COLOR2_SLICE 0x28ce0 1048 #define CB_COLOR3_SLICE 0x28d1c 1049 #define CB_COLOR4_SLICE 0x28d58 1050 #define CB_COLOR5_SLICE 0x28d94 1051 #define CB_COLOR6_SLICE 0x28dd0 1052 #define CB_COLOR7_SLICE 0x28e0c 1053 #define CB_COLOR8_SLICE 0x28e48 1054 #define CB_COLOR9_SLICE 0x28e64 1055 #define CB_COLOR10_SLICE 0x28e80 1056 #define CB_COLOR11_SLICE 0x28e9c 1057 1058 #define CB_COLOR1_VIEW 0x28ca8 1059 #define CB_COLOR2_VIEW 0x28ce4 1060 #define CB_COLOR3_VIEW 0x28d20 1061 #define CB_COLOR4_VIEW 0x28d5c 1062 #define CB_COLOR5_VIEW 0x28d98 1063 #define CB_COLOR6_VIEW 0x28dd4 1064 #define CB_COLOR7_VIEW 0x28e10 1065 #define CB_COLOR8_VIEW 0x28e4c 1066 #define CB_COLOR9_VIEW 0x28e68 1067 #define CB_COLOR10_VIEW 0x28e84 1068 #define CB_COLOR11_VIEW 0x28ea0 1069 1070 #define CB_COLOR1_INFO 0x28cac 1071 #define CB_COLOR2_INFO 0x28ce8 1072 #define CB_COLOR3_INFO 0x28d24 1073 #define CB_COLOR4_INFO 0x28d60 1074 #define CB_COLOR5_INFO 0x28d9c 1075 #define CB_COLOR6_INFO 0x28dd8 1076 #define CB_COLOR7_INFO 0x28e14 1077 #define CB_COLOR8_INFO 0x28e50 1078 #define CB_COLOR9_INFO 0x28e6c 1079 #define CB_COLOR10_INFO 0x28e88 1080 #define CB_COLOR11_INFO 0x28ea4 1081 1082 #define CB_COLOR1_ATTRIB 0x28cb0 1083 #define CB_COLOR2_ATTRIB 0x28cec 1084 #define CB_COLOR3_ATTRIB 0x28d28 1085 #define CB_COLOR4_ATTRIB 0x28d64 1086 #define CB_COLOR5_ATTRIB 0x28da0 1087 #define CB_COLOR6_ATTRIB 0x28ddc 1088 #define CB_COLOR7_ATTRIB 0x28e18 1089 #define CB_COLOR8_ATTRIB 0x28e54 1090 #define CB_COLOR9_ATTRIB 0x28e70 1091 #define CB_COLOR10_ATTRIB 0x28e8c 1092 #define CB_COLOR11_ATTRIB 0x28ea8 1093 1094 #define CB_COLOR1_DIM 0x28cb4 1095 #define CB_COLOR2_DIM 0x28cf0 1096 #define CB_COLOR3_DIM 0x28d2c 1097 #define CB_COLOR4_DIM 0x28d68 1098 #define CB_COLOR5_DIM 0x28da4 1099 #define CB_COLOR6_DIM 0x28de0 1100 #define CB_COLOR7_DIM 0x28e1c 1101 #define CB_COLOR8_DIM 0x28e58 1102 #define CB_COLOR9_DIM 0x28e74 1103 #define CB_COLOR10_DIM 0x28e90 1104 #define CB_COLOR11_DIM 0x28eac 1105 1106 #define CB_COLOR1_CMASK 0x28cb8 1107 #define CB_COLOR2_CMASK 0x28cf4 1108 #define CB_COLOR3_CMASK 0x28d30 1109 #define CB_COLOR4_CMASK 0x28d6c 1110 #define CB_COLOR5_CMASK 0x28da8 1111 #define CB_COLOR6_CMASK 0x28de4 1112 #define CB_COLOR7_CMASK 0x28e20 1113 1114 #define CB_COLOR1_CMASK_SLICE 0x28cbc 1115 #define CB_COLOR2_CMASK_SLICE 0x28cf8 1116 #define CB_COLOR3_CMASK_SLICE 0x28d34 1117 #define CB_COLOR4_CMASK_SLICE 0x28d70 1118 #define CB_COLOR5_CMASK_SLICE 0x28dac 1119 #define CB_COLOR6_CMASK_SLICE 0x28de8 1120 #define CB_COLOR7_CMASK_SLICE 0x28e24 1121 1122 #define CB_COLOR1_FMASK 0x28cc0 1123 #define CB_COLOR2_FMASK 0x28cfc 1124 #define CB_COLOR3_FMASK 0x28d38 1125 #define CB_COLOR4_FMASK 0x28d74 1126 #define CB_COLOR5_FMASK 0x28db0 1127 #define CB_COLOR6_FMASK 0x28dec 1128 #define CB_COLOR7_FMASK 0x28e28 1129 1130 #define CB_COLOR1_FMASK_SLICE 0x28cc4 1131 #define CB_COLOR2_FMASK_SLICE 0x28d00 1132 #define CB_COLOR3_FMASK_SLICE 0x28d3c 1133 #define CB_COLOR4_FMASK_SLICE 0x28d78 1134 #define CB_COLOR5_FMASK_SLICE 0x28db4 1135 #define CB_COLOR6_FMASK_SLICE 0x28df0 1136 #define CB_COLOR7_FMASK_SLICE 0x28e2c 1137 1138 #define CB_COLOR1_CLEAR_WORD0 0x28cc8 1139 #define CB_COLOR2_CLEAR_WORD0 0x28d04 1140 #define CB_COLOR3_CLEAR_WORD0 0x28d40 1141 #define CB_COLOR4_CLEAR_WORD0 0x28d7c 1142 #define CB_COLOR5_CLEAR_WORD0 0x28db8 1143 #define CB_COLOR6_CLEAR_WORD0 0x28df4 1144 #define CB_COLOR7_CLEAR_WORD0 0x28e30 1145 1146 #define CB_COLOR1_CLEAR_WORD1 0x28ccc 1147 #define CB_COLOR2_CLEAR_WORD1 0x28d08 1148 #define CB_COLOR3_CLEAR_WORD1 0x28d44 1149 #define CB_COLOR4_CLEAR_WORD1 0x28d80 1150 #define CB_COLOR5_CLEAR_WORD1 0x28dbc 1151 #define CB_COLOR6_CLEAR_WORD1 0x28df8 1152 #define CB_COLOR7_CLEAR_WORD1 0x28e34 1153 1154 #define CB_COLOR1_CLEAR_WORD2 0x28cd0 1155 #define CB_COLOR2_CLEAR_WORD2 0x28d0c 1156 #define CB_COLOR3_CLEAR_WORD2 0x28d48 1157 #define CB_COLOR4_CLEAR_WORD2 0x28d84 1158 #define CB_COLOR5_CLEAR_WORD2 0x28dc0 1159 #define CB_COLOR6_CLEAR_WORD2 0x28dfc 1160 #define CB_COLOR7_CLEAR_WORD2 0x28e38 1161 1162 #define CB_COLOR1_CLEAR_WORD3 0x28cd4 1163 #define CB_COLOR2_CLEAR_WORD3 0x28d10 1164 #define CB_COLOR3_CLEAR_WORD3 0x28d4c 1165 #define CB_COLOR4_CLEAR_WORD3 0x28d88 1166 #define CB_COLOR5_CLEAR_WORD3 0x28dc4 1167 #define CB_COLOR6_CLEAR_WORD3 0x28e00 1168 #define CB_COLOR7_CLEAR_WORD3 0x28e3c 1169 1170 #define SQ_TEX_RESOURCE_WORD0_0 0x30000 1171 # define TEX_DIM(x) ((x) << 0) 1172 # define SQ_TEX_DIM_1D 0 1173 # define SQ_TEX_DIM_2D 1 1174 # define SQ_TEX_DIM_3D 2 1175 # define SQ_TEX_DIM_CUBEMAP 3 1176 # define SQ_TEX_DIM_1D_ARRAY 4 1177 # define SQ_TEX_DIM_2D_ARRAY 5 1178 # define SQ_TEX_DIM_2D_MSAA 6 1179 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1180 #define SQ_TEX_RESOURCE_WORD1_0 0x30004 1181 # define TEX_ARRAY_MODE(x) ((x) << 28) 1182 #define SQ_TEX_RESOURCE_WORD2_0 0x30008 1183 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1184 #define SQ_TEX_RESOURCE_WORD4_0 0x30010 1185 # define TEX_DST_SEL_X(x) ((x) << 16) 1186 # define TEX_DST_SEL_Y(x) ((x) << 19) 1187 # define TEX_DST_SEL_Z(x) ((x) << 22) 1188 # define TEX_DST_SEL_W(x) ((x) << 25) 1189 # define SQ_SEL_X 0 1190 # define SQ_SEL_Y 1 1191 # define SQ_SEL_Z 2 1192 # define SQ_SEL_W 3 1193 # define SQ_SEL_0 4 1194 # define SQ_SEL_1 5 1195 #define SQ_TEX_RESOURCE_WORD5_0 0x30014 1196 #define SQ_TEX_RESOURCE_WORD6_0 0x30018 1197 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1198 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1199 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1200 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1201 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1202 1203 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 1204 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 1205 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 1206 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1207 # define SQ_VTXC_STRIDE(x) ((x) << 8) 1208 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1209 # define SQ_ENDIAN_NONE 0 1210 # define SQ_ENDIAN_8IN16 1 1211 # define SQ_ENDIAN_8IN32 2 1212 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1213 # define SQ_VTCX_SEL_X(x) ((x) << 3) 1214 # define SQ_VTCX_SEL_Y(x) ((x) << 6) 1215 # define SQ_VTCX_SEL_Z(x) ((x) << 9) 1216 # define SQ_VTCX_SEL_W(x) ((x) << 12) 1217 #define SQ_VTX_CONSTANT_WORD4_0 0x30010 1218 #define SQ_VTX_CONSTANT_WORD5_0 0x30014 1219 #define SQ_VTX_CONSTANT_WORD6_0 0x30018 1220 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1221 1222 #define TD_PS_BORDER_COLOR_INDEX 0xA400 1223 #define TD_PS_BORDER_COLOR_RED 0xA404 1224 #define TD_PS_BORDER_COLOR_GREEN 0xA408 1225 #define TD_PS_BORDER_COLOR_BLUE 0xA40C 1226 #define TD_PS_BORDER_COLOR_ALPHA 0xA410 1227 #define TD_VS_BORDER_COLOR_INDEX 0xA414 1228 #define TD_VS_BORDER_COLOR_RED 0xA418 1229 #define TD_VS_BORDER_COLOR_GREEN 0xA41C 1230 #define TD_VS_BORDER_COLOR_BLUE 0xA420 1231 #define TD_VS_BORDER_COLOR_ALPHA 0xA424 1232 #define TD_GS_BORDER_COLOR_INDEX 0xA428 1233 #define TD_GS_BORDER_COLOR_RED 0xA42C 1234 #define TD_GS_BORDER_COLOR_GREEN 0xA430 1235 #define TD_GS_BORDER_COLOR_BLUE 0xA434 1236 #define TD_GS_BORDER_COLOR_ALPHA 0xA438 1237 #define TD_HS_BORDER_COLOR_INDEX 0xA43C 1238 #define TD_HS_BORDER_COLOR_RED 0xA440 1239 #define TD_HS_BORDER_COLOR_GREEN 0xA444 1240 #define TD_HS_BORDER_COLOR_BLUE 0xA448 1241 #define TD_HS_BORDER_COLOR_ALPHA 0xA44C 1242 #define TD_LS_BORDER_COLOR_INDEX 0xA450 1243 #define TD_LS_BORDER_COLOR_RED 0xA454 1244 #define TD_LS_BORDER_COLOR_GREEN 0xA458 1245 #define TD_LS_BORDER_COLOR_BLUE 0xA45C 1246 #define TD_LS_BORDER_COLOR_ALPHA 0xA460 1247 #define TD_CS_BORDER_COLOR_INDEX 0xA464 1248 #define TD_CS_BORDER_COLOR_RED 0xA468 1249 #define TD_CS_BORDER_COLOR_GREEN 0xA46C 1250 #define TD_CS_BORDER_COLOR_BLUE 0xA470 1251 #define TD_CS_BORDER_COLOR_ALPHA 0xA474 1252 1253 /* cayman 3D regs */ 1254 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 1255 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 1256 #define CAYMAN_DB_EQAA 0x28804 1257 #define CAYMAN_DB_DEPTH_INFO 0x2803C 1258 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 1259 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 1260 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 1261 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 1262 /* cayman packet3 addition */ 1263 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 1264 1265 #endif 1266