1 /*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
28 #include "nv50_display.h"
29 #include "nouveau_crtc.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_fb.h"
33 #include "nouveau_fbcon.h"
34 #include "nouveau_ramht.h"
35 #include "drm_crtc_helper.h"
36
37 static void nv50_display_isr(struct drm_device *);
38 static void nv50_display_bh(unsigned long);
39
40 static inline int
nv50_sor_nr(struct drm_device * dev)41 nv50_sor_nr(struct drm_device *dev)
42 {
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
44
45 if (dev_priv->chipset < 0x90 ||
46 dev_priv->chipset == 0x92 ||
47 dev_priv->chipset == 0xa0)
48 return 2;
49
50 return 4;
51 }
52
53 static int
evo_icmd(struct drm_device * dev,int ch,u32 mthd,u32 data)54 evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
55 {
56 int ret = 0;
57 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000001);
58 nv_wr32(dev, 0x610304 + (ch * 0x08), data);
59 nv_wr32(dev, 0x610300 + (ch * 0x08), 0x80000001 | mthd);
60 if (!nv_wait(dev, 0x610300 + (ch * 0x08), 0x80000000, 0x00000000))
61 ret = -EBUSY;
62 if (ret || (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO))
63 NV_INFO(dev, "EvoPIO: %d 0x%04x 0x%08x\n", ch, mthd, data);
64 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000000);
65 return ret;
66 }
67
68 int
nv50_display_early_init(struct drm_device * dev)69 nv50_display_early_init(struct drm_device *dev)
70 {
71 u32 ctrl = nv_rd32(dev, 0x610200);
72 int i;
73
74 /* check if master evo channel is already active, a good a sign as any
75 * that the display engine is in a weird state (hibernate/kexec), if
76 * it is, do our best to reset the display engine...
77 */
78 if ((ctrl & 0x00000003) == 0x00000003) {
79 NV_INFO(dev, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl);
80
81 /* deactivate both heads first, PDISP will disappear forever
82 * (well, until you power cycle) on some boards as soon as
83 * PMC_ENABLE is hit unless they are..
84 */
85 for (i = 0; i < 2; i++) {
86 evo_icmd(dev, 0, 0x0880 + (i * 0x400), 0x05000000);
87 evo_icmd(dev, 0, 0x089c + (i * 0x400), 0);
88 evo_icmd(dev, 0, 0x0840 + (i * 0x400), 0);
89 evo_icmd(dev, 0, 0x0844 + (i * 0x400), 0);
90 evo_icmd(dev, 0, 0x085c + (i * 0x400), 0);
91 evo_icmd(dev, 0, 0x0874 + (i * 0x400), 0);
92 }
93 evo_icmd(dev, 0, 0x0080, 0);
94
95 /* reset PDISP */
96 nv_mask(dev, 0x000200, 0x40000000, 0x00000000);
97 nv_mask(dev, 0x000200, 0x40000000, 0x40000000);
98 }
99
100 return 0;
101 }
102
103 void
nv50_display_late_takedown(struct drm_device * dev)104 nv50_display_late_takedown(struct drm_device *dev)
105 {
106 }
107
108 int
nv50_display_sync(struct drm_device * dev)109 nv50_display_sync(struct drm_device *dev)
110 {
111 struct drm_nouveau_private *dev_priv = dev->dev_private;
112 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
113 struct nv50_display *disp = nv50_display(dev);
114 struct nouveau_channel *evo = disp->master;
115 u64 start;
116 int ret;
117
118 ret = RING_SPACE(evo, 6);
119 if (ret == 0) {
120 BEGIN_RING(evo, 0, 0x0084, 1);
121 OUT_RING (evo, 0x80000000);
122 BEGIN_RING(evo, 0, 0x0080, 1);
123 OUT_RING (evo, 0);
124 BEGIN_RING(evo, 0, 0x0084, 1);
125 OUT_RING (evo, 0x00000000);
126
127 nv_wo32(disp->ntfy, 0x000, 0x00000000);
128 FIRE_RING (evo);
129
130 start = ptimer->read(dev);
131 do {
132 if (nv_ro32(disp->ntfy, 0x000))
133 return 0;
134 } while (ptimer->read(dev) - start < 2000000000ULL);
135 }
136
137 return -EBUSY;
138 }
139
140 int
nv50_display_init(struct drm_device * dev)141 nv50_display_init(struct drm_device *dev)
142 {
143 struct nouveau_channel *evo;
144 int ret, i;
145 u32 val;
146
147 NV_DEBUG_KMS(dev, "\n");
148
149 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
150
151 /*
152 * I think the 0x006101XX range is some kind of main control area
153 * that enables things.
154 */
155 /* CRTC? */
156 for (i = 0; i < 2; i++) {
157 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
158 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
159 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
160 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
161 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
162 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
163 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
164 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
165 }
166
167 /* DAC */
168 for (i = 0; i < 3; i++) {
169 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
170 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
171 }
172
173 /* SOR */
174 for (i = 0; i < nv50_sor_nr(dev); i++) {
175 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
176 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
177 }
178
179 /* EXT */
180 for (i = 0; i < 3; i++) {
181 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
182 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
183 }
184
185 for (i = 0; i < 3; i++) {
186 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
187 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
188 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
189 }
190
191 /* The precise purpose is unknown, i suspect it has something to do
192 * with text mode.
193 */
194 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
195 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
196 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
197 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
198 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
199 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
200 nv_rd32(dev, 0x6194e8));
201 return -EBUSY;
202 }
203 }
204
205 for (i = 0; i < 2; i++) {
206 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
207 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
208 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
209 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
210 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
211 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
212 return -EBUSY;
213 }
214
215 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
216 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
217 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
218 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
219 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
220 NV_ERROR(dev, "timeout: "
221 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
222 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
223 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
224 return -EBUSY;
225 }
226 }
227
228 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
229 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
230 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
231 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
232 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
233 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
234 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
235 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
236
237 ret = nv50_evo_init(dev);
238 if (ret)
239 return ret;
240 evo = nv50_display(dev)->master;
241
242 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
243
244 ret = RING_SPACE(evo, 3);
245 if (ret)
246 return ret;
247 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
248 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
249 OUT_RING (evo, NvEvoSync);
250
251 return nv50_display_sync(dev);
252 }
253
254 void
nv50_display_fini(struct drm_device * dev)255 nv50_display_fini(struct drm_device *dev)
256 {
257 struct nv50_display *disp = nv50_display(dev);
258 struct nouveau_channel *evo = disp->master;
259 struct drm_crtc *drm_crtc;
260 int ret, i;
261
262 NV_DEBUG_KMS(dev, "\n");
263
264 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
265 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
266
267 nv50_crtc_blank(crtc, true);
268 }
269
270 ret = RING_SPACE(evo, 2);
271 if (ret == 0) {
272 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
273 OUT_RING(evo, 0);
274 }
275 FIRE_RING(evo);
276
277 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
278 * cleaning up?
279 */
280 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
281 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
282 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
283
284 if (!crtc->base.enabled)
285 continue;
286
287 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
288 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
289 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
290 "0x%08x\n", mask, mask);
291 NV_ERROR(dev, "0x610024 = 0x%08x\n",
292 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
293 }
294 }
295
296 for (i = 0; i < 2; i++) {
297 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
298 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
299 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
300 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
301 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
302 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
303 }
304 }
305
306 nv50_evo_fini(dev);
307
308 for (i = 0; i < 3; i++) {
309 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
310 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
311 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
312 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
313 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
314 }
315 }
316
317 /* disable interrupts. */
318 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
319 }
320
321 int
nv50_display_create(struct drm_device * dev)322 nv50_display_create(struct drm_device *dev)
323 {
324 struct drm_nouveau_private *dev_priv = dev->dev_private;
325 struct dcb_table *dcb = &dev_priv->vbios.dcb;
326 struct drm_connector *connector, *ct;
327 struct nv50_display *priv;
328 int ret, i;
329
330 NV_DEBUG_KMS(dev, "\n");
331
332 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
333 if (!priv)
334 return -ENOMEM;
335 dev_priv->engine.display.priv = priv;
336
337 /* Create CRTC objects */
338 for (i = 0; i < 2; i++)
339 nv50_crtc_create(dev, i);
340
341 /* We setup the encoders from the BIOS table */
342 for (i = 0 ; i < dcb->entries; i++) {
343 struct dcb_entry *entry = &dcb->entry[i];
344
345 if (entry->location != DCB_LOC_ON_CHIP) {
346 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
347 entry->type, ffs(entry->or) - 1);
348 continue;
349 }
350
351 connector = nouveau_connector_create(dev, entry->connector);
352 if (IS_ERR(connector))
353 continue;
354
355 switch (entry->type) {
356 case OUTPUT_TMDS:
357 case OUTPUT_LVDS:
358 case OUTPUT_DP:
359 nv50_sor_create(connector, entry);
360 break;
361 case OUTPUT_ANALOG:
362 nv50_dac_create(connector, entry);
363 break;
364 default:
365 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
366 continue;
367 }
368 }
369
370 list_for_each_entry_safe(connector, ct,
371 &dev->mode_config.connector_list, head) {
372 if (!connector->encoder_ids[0]) {
373 NV_WARN(dev, "%s has no encoders, removing\n",
374 drm_get_connector_name(connector));
375 connector->funcs->destroy(connector);
376 }
377 }
378
379 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
380 nouveau_irq_register(dev, 26, nv50_display_isr);
381
382 ret = nv50_evo_create(dev);
383 if (ret) {
384 nv50_display_destroy(dev);
385 return ret;
386 }
387
388 return 0;
389 }
390
391 void
nv50_display_destroy(struct drm_device * dev)392 nv50_display_destroy(struct drm_device *dev)
393 {
394 struct nv50_display *disp = nv50_display(dev);
395
396 NV_DEBUG_KMS(dev, "\n");
397
398 nv50_evo_destroy(dev);
399 nouveau_irq_unregister(dev, 26);
400 kfree(disp);
401 }
402
403 void
nv50_display_flip_stop(struct drm_crtc * crtc)404 nv50_display_flip_stop(struct drm_crtc *crtc)
405 {
406 struct nv50_display *disp = nv50_display(crtc->dev);
407 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
408 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
409 struct nouveau_channel *evo = dispc->sync;
410 int ret;
411
412 ret = RING_SPACE(evo, 8);
413 if (ret) {
414 WARN_ON(1);
415 return;
416 }
417
418 BEGIN_RING(evo, 0, 0x0084, 1);
419 OUT_RING (evo, 0x00000000);
420 BEGIN_RING(evo, 0, 0x0094, 1);
421 OUT_RING (evo, 0x00000000);
422 BEGIN_RING(evo, 0, 0x00c0, 1);
423 OUT_RING (evo, 0x00000000);
424 BEGIN_RING(evo, 0, 0x0080, 1);
425 OUT_RING (evo, 0x00000000);
426 FIRE_RING (evo);
427 }
428
429 int
nv50_display_flip_next(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct nouveau_channel * chan)430 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
431 struct nouveau_channel *chan)
432 {
433 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
434 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
435 struct nv50_display *disp = nv50_display(crtc->dev);
436 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
437 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
438 struct nouveau_channel *evo = dispc->sync;
439 int ret;
440
441 ret = RING_SPACE(evo, chan ? 25 : 27);
442 if (unlikely(ret))
443 return ret;
444
445 /* synchronise with the rendering channel, if necessary */
446 if (likely(chan)) {
447 ret = RING_SPACE(chan, 10);
448 if (ret) {
449 WIND_RING(evo);
450 return ret;
451 }
452
453 if (dev_priv->chipset < 0xc0) {
454 BEGIN_RING(chan, NvSubSw, 0x0060, 2);
455 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
456 OUT_RING (chan, dispc->sem.offset);
457 BEGIN_RING(chan, NvSubSw, 0x006c, 1);
458 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
459 BEGIN_RING(chan, NvSubSw, 0x0064, 2);
460 OUT_RING (chan, dispc->sem.offset ^ 0x10);
461 OUT_RING (chan, 0x74b1e000);
462 BEGIN_RING(chan, NvSubSw, 0x0060, 1);
463 if (dev_priv->chipset < 0x84)
464 OUT_RING (chan, NvSema);
465 else
466 OUT_RING (chan, chan->vram_handle);
467 } else {
468 u64 offset = chan->dispc_vma[nv_crtc->index].offset;
469 offset += dispc->sem.offset;
470 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
471 OUT_RING (chan, upper_32_bits(offset));
472 OUT_RING (chan, lower_32_bits(offset));
473 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
474 OUT_RING (chan, 0x1002);
475 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
476 OUT_RING (chan, upper_32_bits(offset));
477 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
478 OUT_RING (chan, 0x74b1e000);
479 OUT_RING (chan, 0x1001);
480 }
481 FIRE_RING (chan);
482 } else {
483 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
484 0xf00d0000 | dispc->sem.value);
485 }
486
487 /* queue the flip on the crtc's "display sync" channel */
488 BEGIN_RING(evo, 0, 0x0100, 1);
489 OUT_RING (evo, 0xfffe0000);
490 if (chan) {
491 BEGIN_RING(evo, 0, 0x0084, 1);
492 OUT_RING (evo, 0x00000100);
493 } else {
494 BEGIN_RING(evo, 0, 0x0084, 1);
495 OUT_RING (evo, 0x00000010);
496 /* allows gamma somehow, PDISP will bitch at you if
497 * you don't wait for vblank before changing this..
498 */
499 BEGIN_RING(evo, 0, 0x00e0, 1);
500 OUT_RING (evo, 0x40000000);
501 }
502 BEGIN_RING(evo, 0, 0x0088, 4);
503 OUT_RING (evo, dispc->sem.offset);
504 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
505 OUT_RING (evo, 0x74b1e000);
506 OUT_RING (evo, NvEvoSync);
507 BEGIN_RING(evo, 0, 0x00a0, 2);
508 OUT_RING (evo, 0x00000000);
509 OUT_RING (evo, 0x00000000);
510 BEGIN_RING(evo, 0, 0x00c0, 1);
511 OUT_RING (evo, nv_fb->r_dma);
512 BEGIN_RING(evo, 0, 0x0110, 2);
513 OUT_RING (evo, 0x00000000);
514 OUT_RING (evo, 0x00000000);
515 BEGIN_RING(evo, 0, 0x0800, 5);
516 OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8);
517 OUT_RING (evo, 0);
518 OUT_RING (evo, (fb->height << 16) | fb->width);
519 OUT_RING (evo, nv_fb->r_pitch);
520 OUT_RING (evo, nv_fb->r_format);
521 BEGIN_RING(evo, 0, 0x0080, 1);
522 OUT_RING (evo, 0x00000000);
523 FIRE_RING (evo);
524
525 dispc->sem.offset ^= 0x10;
526 dispc->sem.value++;
527 return 0;
528 }
529
530 static u16
nv50_display_script_select(struct drm_device * dev,struct dcb_entry * dcb,u32 mc,int pxclk)531 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
532 u32 mc, int pxclk)
533 {
534 struct drm_nouveau_private *dev_priv = dev->dev_private;
535 struct nouveau_connector *nv_connector = NULL;
536 struct drm_encoder *encoder;
537 struct nvbios *bios = &dev_priv->vbios;
538 u32 script = 0, or;
539
540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
541 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
542
543 if (nv_encoder->dcb != dcb)
544 continue;
545
546 nv_connector = nouveau_encoder_connector_get(nv_encoder);
547 break;
548 }
549
550 or = ffs(dcb->or) - 1;
551 switch (dcb->type) {
552 case OUTPUT_LVDS:
553 script = (mc >> 8) & 0xf;
554 if (bios->fp_no_ddc) {
555 if (bios->fp.dual_link)
556 script |= 0x0100;
557 if (bios->fp.if_is_24bit)
558 script |= 0x0200;
559 } else {
560 /* determine number of lvds links */
561 if (nv_connector && nv_connector->edid &&
562 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
563 /* http://www.spwg.org */
564 if (((u8 *)nv_connector->edid)[121] == 2)
565 script |= 0x0100;
566 } else
567 if (pxclk >= bios->fp.duallink_transition_clk) {
568 script |= 0x0100;
569 }
570
571 /* determine panel depth */
572 if (script & 0x0100) {
573 if (bios->fp.strapless_is_24bit & 2)
574 script |= 0x0200;
575 } else {
576 if (bios->fp.strapless_is_24bit & 1)
577 script |= 0x0200;
578 }
579
580 if (nv_connector && nv_connector->edid &&
581 (nv_connector->edid->revision >= 4) &&
582 (nv_connector->edid->input & 0x70) >= 0x20)
583 script |= 0x0200;
584 }
585
586 if (nouveau_uscript_lvds >= 0) {
587 NV_INFO(dev, "override script 0x%04x with 0x%04x "
588 "for output LVDS-%d\n", script,
589 nouveau_uscript_lvds, or);
590 script = nouveau_uscript_lvds;
591 }
592 break;
593 case OUTPUT_TMDS:
594 script = (mc >> 8) & 0xf;
595 if (pxclk >= 165000)
596 script |= 0x0100;
597
598 if (nouveau_uscript_tmds >= 0) {
599 NV_INFO(dev, "override script 0x%04x with 0x%04x "
600 "for output TMDS-%d\n", script,
601 nouveau_uscript_tmds, or);
602 script = nouveau_uscript_tmds;
603 }
604 break;
605 case OUTPUT_DP:
606 script = (mc >> 8) & 0xf;
607 break;
608 case OUTPUT_ANALOG:
609 script = 0xff;
610 break;
611 default:
612 NV_ERROR(dev, "modeset on unsupported output type!\n");
613 break;
614 }
615
616 return script;
617 }
618
619 static void
nv50_display_vblank_crtc_handler(struct drm_device * dev,int crtc)620 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
621 {
622 struct drm_nouveau_private *dev_priv = dev->dev_private;
623 struct nouveau_channel *chan, *tmp;
624
625 list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
626 nvsw.vbl_wait) {
627 if (chan->nvsw.vblsem_head != crtc)
628 continue;
629
630 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
631 chan->nvsw.vblsem_rval);
632 list_del(&chan->nvsw.vbl_wait);
633 drm_vblank_put(dev, crtc);
634 }
635
636 drm_handle_vblank(dev, crtc);
637 }
638
639 static void
nv50_display_vblank_handler(struct drm_device * dev,uint32_t intr)640 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
641 {
642 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
643 nv50_display_vblank_crtc_handler(dev, 0);
644
645 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
646 nv50_display_vblank_crtc_handler(dev, 1);
647
648 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
649 }
650
651 static void
nv50_display_unk10_handler(struct drm_device * dev)652 nv50_display_unk10_handler(struct drm_device *dev)
653 {
654 struct drm_nouveau_private *dev_priv = dev->dev_private;
655 struct nv50_display *disp = nv50_display(dev);
656 u32 unk30 = nv_rd32(dev, 0x610030), mc;
657 int i, crtc, or = 0, type = OUTPUT_ANY;
658
659 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
660 disp->irq.dcb = NULL;
661
662 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
663
664 /* Determine which CRTC we're dealing with, only 1 ever will be
665 * signalled at the same time with the current nouveau code.
666 */
667 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
668 if (crtc < 0)
669 goto ack;
670
671 /* Nothing needs to be done for the encoder */
672 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
673 if (crtc < 0)
674 goto ack;
675
676 /* Find which encoder was connected to the CRTC */
677 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
678 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
679 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
680 if (!(mc & (1 << crtc)))
681 continue;
682
683 switch ((mc & 0x00000f00) >> 8) {
684 case 0: type = OUTPUT_ANALOG; break;
685 case 1: type = OUTPUT_TV; break;
686 default:
687 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
688 goto ack;
689 }
690
691 or = i;
692 }
693
694 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
695 if (dev_priv->chipset < 0x90 ||
696 dev_priv->chipset == 0x92 ||
697 dev_priv->chipset == 0xa0)
698 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
699 else
700 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
701
702 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
703 if (!(mc & (1 << crtc)))
704 continue;
705
706 switch ((mc & 0x00000f00) >> 8) {
707 case 0: type = OUTPUT_LVDS; break;
708 case 1: type = OUTPUT_TMDS; break;
709 case 2: type = OUTPUT_TMDS; break;
710 case 5: type = OUTPUT_TMDS; break;
711 case 8: type = OUTPUT_DP; break;
712 case 9: type = OUTPUT_DP; break;
713 default:
714 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
715 goto ack;
716 }
717
718 or = i;
719 }
720
721 /* There was no encoder to disable */
722 if (type == OUTPUT_ANY)
723 goto ack;
724
725 /* Disable the encoder */
726 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
727 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
728
729 if (dcb->type == type && (dcb->or & (1 << or))) {
730 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
731 disp->irq.dcb = dcb;
732 goto ack;
733 }
734 }
735
736 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
737 ack:
738 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
739 nv_wr32(dev, 0x610030, 0x80000000);
740 }
741
742 static void
nv50_display_unk20_handler(struct drm_device * dev)743 nv50_display_unk20_handler(struct drm_device *dev)
744 {
745 struct drm_nouveau_private *dev_priv = dev->dev_private;
746 struct nv50_display *disp = nv50_display(dev);
747 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
748 struct dcb_entry *dcb;
749 int i, crtc, or = 0, type = OUTPUT_ANY;
750
751 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
752 dcb = disp->irq.dcb;
753 if (dcb) {
754 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
755 disp->irq.dcb = NULL;
756 }
757
758 /* CRTC clock change requested? */
759 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
760 if (crtc >= 0) {
761 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
762 pclk &= 0x003fffff;
763 if (pclk)
764 nv50_crtc_set_clock(dev, crtc, pclk);
765
766 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
767 tmp &= ~0x000000f;
768 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
769 }
770
771 /* Nothing needs to be done for the encoder */
772 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
773 if (crtc < 0)
774 goto ack;
775 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
776
777 /* Find which encoder is connected to the CRTC */
778 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
779 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
780 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
781 if (!(mc & (1 << crtc)))
782 continue;
783
784 switch ((mc & 0x00000f00) >> 8) {
785 case 0: type = OUTPUT_ANALOG; break;
786 case 1: type = OUTPUT_TV; break;
787 default:
788 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
789 goto ack;
790 }
791
792 or = i;
793 }
794
795 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
796 if (dev_priv->chipset < 0x90 ||
797 dev_priv->chipset == 0x92 ||
798 dev_priv->chipset == 0xa0)
799 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
800 else
801 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
802
803 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
804 if (!(mc & (1 << crtc)))
805 continue;
806
807 switch ((mc & 0x00000f00) >> 8) {
808 case 0: type = OUTPUT_LVDS; break;
809 case 1: type = OUTPUT_TMDS; break;
810 case 2: type = OUTPUT_TMDS; break;
811 case 5: type = OUTPUT_TMDS; break;
812 case 8: type = OUTPUT_DP; break;
813 case 9: type = OUTPUT_DP; break;
814 default:
815 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
816 goto ack;
817 }
818
819 or = i;
820 }
821
822 if (type == OUTPUT_ANY)
823 goto ack;
824
825 /* Enable the encoder */
826 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
827 dcb = &dev_priv->vbios.dcb.entry[i];
828 if (dcb->type == type && (dcb->or & (1 << or)))
829 break;
830 }
831
832 if (i == dev_priv->vbios.dcb.entries) {
833 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
834 goto ack;
835 }
836
837 script = nv50_display_script_select(dev, dcb, mc, pclk);
838 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
839
840 if (type == OUTPUT_DP) {
841 int link = !(dcb->dpconf.sor.link & 1);
842 if ((mc & 0x000f0000) == 0x00020000)
843 nouveau_dp_tu_update(dev, or, link, pclk, 18);
844 else
845 nouveau_dp_tu_update(dev, or, link, pclk, 24);
846 }
847
848 if (dcb->type != OUTPUT_ANALOG) {
849 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
850 tmp &= ~0x00000f0f;
851 if (script & 0x0100)
852 tmp |= 0x00000101;
853 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
854 } else {
855 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
856 }
857
858 disp->irq.dcb = dcb;
859 disp->irq.pclk = pclk;
860 disp->irq.script = script;
861
862 ack:
863 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
864 nv_wr32(dev, 0x610030, 0x80000000);
865 }
866
867 /* If programming a TMDS output on a SOR that can also be configured for
868 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
869 *
870 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
871 * the VBIOS scripts on at least one board I have only switch it off on
872 * link 0, causing a blank display if the output has previously been
873 * programmed for DisplayPort.
874 */
875 static void
nv50_display_unk40_dp_set_tmds(struct drm_device * dev,struct dcb_entry * dcb)876 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
877 {
878 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
879 struct drm_encoder *encoder;
880 u32 tmp;
881
882 if (dcb->type != OUTPUT_TMDS)
883 return;
884
885 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
886 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
887
888 if (nv_encoder->dcb->type == OUTPUT_DP &&
889 nv_encoder->dcb->or & (1 << or)) {
890 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
891 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
892 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
893 break;
894 }
895 }
896 }
897
898 static void
nv50_display_unk40_handler(struct drm_device * dev)899 nv50_display_unk40_handler(struct drm_device *dev)
900 {
901 struct nv50_display *disp = nv50_display(dev);
902 struct dcb_entry *dcb = disp->irq.dcb;
903 u16 script = disp->irq.script;
904 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
905
906 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
907 disp->irq.dcb = NULL;
908 if (!dcb)
909 goto ack;
910
911 nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
912 nv50_display_unk40_dp_set_tmds(dev, dcb);
913
914 ack:
915 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
916 nv_wr32(dev, 0x610030, 0x80000000);
917 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
918 }
919
920 static void
nv50_display_bh(unsigned long data)921 nv50_display_bh(unsigned long data)
922 {
923 struct drm_device *dev = (struct drm_device *)data;
924
925 for (;;) {
926 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
927 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
928
929 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
930
931 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
932 nv50_display_unk10_handler(dev);
933 else
934 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
935 nv50_display_unk20_handler(dev);
936 else
937 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
938 nv50_display_unk40_handler(dev);
939 else
940 break;
941 }
942
943 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
944 }
945
946 static void
nv50_display_error_handler(struct drm_device * dev)947 nv50_display_error_handler(struct drm_device *dev)
948 {
949 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
950 u32 addr, data;
951 int chid;
952
953 for (chid = 0; chid < 5; chid++) {
954 if (!(channels & (1 << chid)))
955 continue;
956
957 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
958 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
959 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
960 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
961 "(0x%04x 0x%02x)\n", chid,
962 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
963
964 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
965 }
966 }
967
968 static void
nv50_display_isr(struct drm_device * dev)969 nv50_display_isr(struct drm_device *dev)
970 {
971 struct nv50_display *disp = nv50_display(dev);
972 uint32_t delayed = 0;
973
974 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
975 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
976 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
977 uint32_t clock;
978
979 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
980
981 if (!intr0 && !(intr1 & ~delayed))
982 break;
983
984 if (intr0 & 0x001f0000) {
985 nv50_display_error_handler(dev);
986 intr0 &= ~0x001f0000;
987 }
988
989 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
990 nv50_display_vblank_handler(dev, intr1);
991 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
992 }
993
994 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
995 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
996 NV50_PDISPLAY_INTR_1_CLK_UNK40));
997 if (clock) {
998 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
999 tasklet_schedule(&disp->tasklet);
1000 delayed |= clock;
1001 intr1 &= ~clock;
1002 }
1003
1004 if (intr0) {
1005 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1006 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1007 }
1008
1009 if (intr1) {
1010 NV_ERROR(dev,
1011 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1012 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1013 }
1014 }
1015 }
1016