1 /*
2 * Copyright 2005-2006 Stephane Marchesin
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "drmP.h"
26 #include "drm.h"
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
30 #include "nouveau_ramht.h"
31
32 static int
nouveau_channel_pushbuf_init(struct nouveau_channel * chan)33 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
34 {
35 u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
36 struct drm_device *dev = chan->dev;
37 struct drm_nouveau_private *dev_priv = dev->dev_private;
38 int ret;
39
40 /* allocate buffer object */
41 ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, &chan->pushbuf_bo);
42 if (ret)
43 goto out;
44
45 ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
46 if (ret)
47 goto out;
48
49 ret = nouveau_bo_map(chan->pushbuf_bo);
50 if (ret)
51 goto out;
52
53 /* create DMA object covering the entire memtype where the push
54 * buffer resides, userspace can submit its own push buffers from
55 * anywhere within the same memtype.
56 */
57 chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
58 if (dev_priv->card_type >= NV_50) {
59 ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
60 &chan->pushbuf_vma);
61 if (ret)
62 goto out;
63
64 if (dev_priv->card_type < NV_C0) {
65 ret = nouveau_gpuobj_dma_new(chan,
66 NV_CLASS_DMA_IN_MEMORY, 0,
67 (1ULL << 40),
68 NV_MEM_ACCESS_RO,
69 NV_MEM_TARGET_VM,
70 &chan->pushbuf);
71 }
72 chan->pushbuf_base = chan->pushbuf_vma.offset;
73 } else
74 if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
75 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
76 dev_priv->gart_info.aper_size,
77 NV_MEM_ACCESS_RO,
78 NV_MEM_TARGET_GART,
79 &chan->pushbuf);
80 } else
81 if (dev_priv->card_type != NV_04) {
82 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
83 dev_priv->fb_available_size,
84 NV_MEM_ACCESS_RO,
85 NV_MEM_TARGET_VRAM,
86 &chan->pushbuf);
87 } else {
88 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
89 * exact reason for existing :) PCI access to cmdbuf in
90 * VRAM.
91 */
92 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
93 pci_resource_start(dev->pdev, 1),
94 dev_priv->fb_available_size,
95 NV_MEM_ACCESS_RO,
96 NV_MEM_TARGET_PCI,
97 &chan->pushbuf);
98 }
99
100 out:
101 if (ret) {
102 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
103 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
104 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
105 if (chan->pushbuf_bo) {
106 nouveau_bo_unmap(chan->pushbuf_bo);
107 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
108 }
109 }
110
111 return 0;
112 }
113
114 /* allocates and initializes a fifo for user space consumption */
115 int
nouveau_channel_alloc(struct drm_device * dev,struct nouveau_channel ** chan_ret,struct drm_file * file_priv,uint32_t vram_handle,uint32_t gart_handle)116 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
117 struct drm_file *file_priv,
118 uint32_t vram_handle, uint32_t gart_handle)
119 {
120 struct drm_nouveau_private *dev_priv = dev->dev_private;
121 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
122 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
123 struct nouveau_channel *chan;
124 unsigned long flags;
125 int ret;
126
127 /* allocate and lock channel structure */
128 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
129 if (!chan)
130 return -ENOMEM;
131 chan->dev = dev;
132 chan->file_priv = file_priv;
133 chan->vram_handle = vram_handle;
134 chan->gart_handle = gart_handle;
135
136 kref_init(&chan->ref);
137 atomic_set(&chan->users, 1);
138 mutex_init(&chan->mutex);
139 mutex_lock(&chan->mutex);
140
141 /* allocate hw channel id */
142 spin_lock_irqsave(&dev_priv->channels.lock, flags);
143 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
144 if (!dev_priv->channels.ptr[chan->id]) {
145 nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
146 break;
147 }
148 }
149 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
150
151 if (chan->id == pfifo->channels) {
152 mutex_unlock(&chan->mutex);
153 kfree(chan);
154 return -ENODEV;
155 }
156
157 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
158 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
159 INIT_LIST_HEAD(&chan->nvsw.flip);
160 INIT_LIST_HEAD(&chan->fence.pending);
161 spin_lock_init(&chan->fence.lock);
162
163 /* setup channel's memory and vm */
164 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
165 if (ret) {
166 NV_ERROR(dev, "gpuobj %d\n", ret);
167 nouveau_channel_put(&chan);
168 return ret;
169 }
170
171 /* Allocate space for per-channel fixed notifier memory */
172 ret = nouveau_notifier_init_channel(chan);
173 if (ret) {
174 NV_ERROR(dev, "ntfy %d\n", ret);
175 nouveau_channel_put(&chan);
176 return ret;
177 }
178
179 /* Allocate DMA push buffer */
180 ret = nouveau_channel_pushbuf_init(chan);
181 if (ret) {
182 NV_ERROR(dev, "pushbuf %d\n", ret);
183 nouveau_channel_put(&chan);
184 return ret;
185 }
186
187 nouveau_dma_pre_init(chan);
188 chan->user_put = 0x40;
189 chan->user_get = 0x44;
190 if (dev_priv->card_type >= NV_50)
191 chan->user_get_hi = 0x60;
192
193 /* disable the fifo caches */
194 pfifo->reassign(dev, false);
195
196 /* Construct initial RAMFC for new channel */
197 ret = pfifo->create_context(chan);
198 if (ret) {
199 nouveau_channel_put(&chan);
200 return ret;
201 }
202
203 pfifo->reassign(dev, true);
204
205 ret = nouveau_dma_init(chan);
206 if (!ret)
207 ret = nouveau_fence_channel_init(chan);
208 if (ret) {
209 nouveau_channel_put(&chan);
210 return ret;
211 }
212
213 nouveau_debugfs_channel_init(chan);
214
215 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
216 if (fpriv) {
217 spin_lock(&fpriv->lock);
218 list_add(&chan->list, &fpriv->channels);
219 spin_unlock(&fpriv->lock);
220 }
221 *chan_ret = chan;
222 return 0;
223 }
224
225 struct nouveau_channel *
nouveau_channel_get_unlocked(struct nouveau_channel * ref)226 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
227 {
228 struct nouveau_channel *chan = NULL;
229
230 if (likely(ref && atomic_inc_not_zero(&ref->users)))
231 nouveau_channel_ref(ref, &chan);
232
233 return chan;
234 }
235
236 struct nouveau_channel *
nouveau_channel_get(struct drm_file * file_priv,int id)237 nouveau_channel_get(struct drm_file *file_priv, int id)
238 {
239 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
240 struct nouveau_channel *chan;
241
242 spin_lock(&fpriv->lock);
243 list_for_each_entry(chan, &fpriv->channels, list) {
244 if (chan->id == id) {
245 chan = nouveau_channel_get_unlocked(chan);
246 spin_unlock(&fpriv->lock);
247 mutex_lock(&chan->mutex);
248 return chan;
249 }
250 }
251 spin_unlock(&fpriv->lock);
252
253 return ERR_PTR(-EINVAL);
254 }
255
256 void
nouveau_channel_put_unlocked(struct nouveau_channel ** pchan)257 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
258 {
259 struct nouveau_channel *chan = *pchan;
260 struct drm_device *dev = chan->dev;
261 struct drm_nouveau_private *dev_priv = dev->dev_private;
262 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
263 unsigned long flags;
264 int i;
265
266 /* decrement the refcount, and we're done if there's still refs */
267 if (likely(!atomic_dec_and_test(&chan->users))) {
268 nouveau_channel_ref(NULL, pchan);
269 return;
270 }
271
272 /* no one wants the channel anymore */
273 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
274 nouveau_debugfs_channel_fini(chan);
275
276 /* give it chance to idle */
277 nouveau_channel_idle(chan);
278
279 /* ensure all outstanding fences are signaled. they should be if the
280 * above attempts at idling were OK, but if we failed this'll tell TTM
281 * we're done with the buffers.
282 */
283 nouveau_fence_channel_fini(chan);
284
285 /* boot it off the hardware */
286 pfifo->reassign(dev, false);
287
288 /* destroy the engine specific contexts */
289 pfifo->destroy_context(chan);
290 for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
291 if (chan->engctx[i])
292 dev_priv->eng[i]->context_del(chan, i);
293 }
294
295 pfifo->reassign(dev, true);
296
297 /* aside from its resources, the channel should now be dead,
298 * remove it from the channel list
299 */
300 spin_lock_irqsave(&dev_priv->channels.lock, flags);
301 nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
302 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
303
304 /* destroy any resources the channel owned */
305 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
306 if (chan->pushbuf_bo) {
307 nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
308 nouveau_bo_unmap(chan->pushbuf_bo);
309 nouveau_bo_unpin(chan->pushbuf_bo);
310 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
311 }
312 nouveau_ramht_ref(NULL, &chan->ramht, chan);
313 nouveau_notifier_takedown_channel(chan);
314 nouveau_gpuobj_channel_takedown(chan);
315
316 nouveau_channel_ref(NULL, pchan);
317 }
318
319 void
nouveau_channel_put(struct nouveau_channel ** pchan)320 nouveau_channel_put(struct nouveau_channel **pchan)
321 {
322 mutex_unlock(&(*pchan)->mutex);
323 nouveau_channel_put_unlocked(pchan);
324 }
325
326 static void
nouveau_channel_del(struct kref * ref)327 nouveau_channel_del(struct kref *ref)
328 {
329 struct nouveau_channel *chan =
330 container_of(ref, struct nouveau_channel, ref);
331
332 kfree(chan);
333 }
334
335 void
nouveau_channel_ref(struct nouveau_channel * chan,struct nouveau_channel ** pchan)336 nouveau_channel_ref(struct nouveau_channel *chan,
337 struct nouveau_channel **pchan)
338 {
339 if (chan)
340 kref_get(&chan->ref);
341
342 if (*pchan)
343 kref_put(&(*pchan)->ref, nouveau_channel_del);
344
345 *pchan = chan;
346 }
347
348 void
nouveau_channel_idle(struct nouveau_channel * chan)349 nouveau_channel_idle(struct nouveau_channel *chan)
350 {
351 struct drm_device *dev = chan->dev;
352 struct nouveau_fence *fence = NULL;
353 int ret;
354
355 nouveau_fence_update(chan);
356
357 if (chan->fence.sequence != chan->fence.sequence_ack) {
358 ret = nouveau_fence_new(chan, &fence, true);
359 if (!ret) {
360 ret = nouveau_fence_wait(fence, false, false);
361 nouveau_fence_unref(&fence);
362 }
363
364 if (ret)
365 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
366 }
367 }
368
369 /* cleans up all the fifos from file_priv */
370 void
nouveau_channel_cleanup(struct drm_device * dev,struct drm_file * file_priv)371 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
372 {
373 struct drm_nouveau_private *dev_priv = dev->dev_private;
374 struct nouveau_engine *engine = &dev_priv->engine;
375 struct nouveau_channel *chan;
376 int i;
377
378 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
379 for (i = 0; i < engine->fifo.channels; i++) {
380 chan = nouveau_channel_get(file_priv, i);
381 if (IS_ERR(chan))
382 continue;
383
384 list_del(&chan->list);
385 atomic_dec(&chan->users);
386 nouveau_channel_put(&chan);
387 }
388 }
389
390
391 /***********************************
392 * ioctls wrapping the functions
393 ***********************************/
394
395 static int
nouveau_ioctl_fifo_alloc(struct drm_device * dev,void * data,struct drm_file * file_priv)396 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
397 struct drm_file *file_priv)
398 {
399 struct drm_nouveau_private *dev_priv = dev->dev_private;
400 struct drm_nouveau_channel_alloc *init = data;
401 struct nouveau_channel *chan;
402 int ret;
403
404 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
405 return -ENODEV;
406
407 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
408 return -EINVAL;
409
410 ret = nouveau_channel_alloc(dev, &chan, file_priv,
411 init->fb_ctxdma_handle,
412 init->tt_ctxdma_handle);
413 if (ret)
414 return ret;
415 init->channel = chan->id;
416
417 if (nouveau_vram_pushbuf == 0) {
418 if (chan->dma.ib_max)
419 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
420 NOUVEAU_GEM_DOMAIN_GART;
421 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
422 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
423 else
424 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
425 } else {
426 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
427 }
428
429 if (dev_priv->card_type < NV_C0) {
430 init->subchan[0].handle = NvM2MF;
431 if (dev_priv->card_type < NV_50)
432 init->subchan[0].grclass = 0x0039;
433 else
434 init->subchan[0].grclass = 0x5039;
435 init->subchan[1].handle = NvSw;
436 init->subchan[1].grclass = NV_SW;
437 init->nr_subchan = 2;
438 } else {
439 init->subchan[0].handle = 0x9039;
440 init->subchan[0].grclass = 0x9039;
441 init->nr_subchan = 1;
442 }
443
444 /* Named memory object area */
445 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
446 &init->notifier_handle);
447
448 if (ret == 0)
449 atomic_inc(&chan->users); /* userspace reference */
450 nouveau_channel_put(&chan);
451 return ret;
452 }
453
454 static int
nouveau_ioctl_fifo_free(struct drm_device * dev,void * data,struct drm_file * file_priv)455 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
456 struct drm_file *file_priv)
457 {
458 struct drm_nouveau_channel_free *req = data;
459 struct nouveau_channel *chan;
460
461 chan = nouveau_channel_get(file_priv, req->channel);
462 if (IS_ERR(chan))
463 return PTR_ERR(chan);
464
465 list_del(&chan->list);
466 atomic_dec(&chan->users);
467 nouveau_channel_put(&chan);
468 return 0;
469 }
470
471 /***********************************
472 * finally, the ioctl table
473 ***********************************/
474
475 struct drm_ioctl_desc nouveau_ioctls[] = {
476 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
477 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
478 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
479 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
480 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
481 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
482 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
483 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
484 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
485 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
486 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
488 };
489
490 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
491