1 /*
2 * Moorestown platform Langwell chip GPIO driver
3 *
4 * Copyright (c) 2008 - 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 /* Supports:
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
23 * Whitney point.
24 */
25
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/stddef.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/gpio.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39
40 /*
41 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
42 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
43 * registers to control them, so we only define the order here instead of a
44 * structure, to get a bit offset for a pin (use GPDR as an example):
45 *
46 * nreg = ngpio / 32;
47 * reg = offset / 32;
48 * bit = offset % 32;
49 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
50 *
51 * so the bit of reg_addr is to control pin offset's GPDR feature
52 */
53
54 enum GPIO_REG {
55 GPLR = 0, /* pin level read-only */
56 GPDR, /* pin direction */
57 GPSR, /* pin set */
58 GPCR, /* pin clear */
59 GRER, /* rising edge detect */
60 GFER, /* falling edge detect */
61 GEDR, /* edge detect result */
62 GAFR, /* alt function */
63 };
64
65 struct lnw_gpio {
66 struct gpio_chip chip;
67 void *reg_base;
68 spinlock_t lock;
69 unsigned irq_base;
70 struct pci_dev *pdev;
71 };
72
gpio_reg(struct gpio_chip * chip,unsigned offset,enum GPIO_REG reg_type)73 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
74 enum GPIO_REG reg_type)
75 {
76 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
77 unsigned nreg = chip->ngpio / 32;
78 u8 reg = offset / 32;
79 void __iomem *ptr;
80
81 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
82 return ptr;
83 }
84
gpio_reg_2bit(struct gpio_chip * chip,unsigned offset,enum GPIO_REG reg_type)85 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
86 enum GPIO_REG reg_type)
87 {
88 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
89 unsigned nreg = chip->ngpio / 32;
90 u8 reg = offset / 16;
91 void __iomem *ptr;
92
93 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
94 return ptr;
95 }
96
lnw_gpio_request(struct gpio_chip * chip,unsigned offset)97 static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
98 {
99 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
100 u32 value = readl(gafr);
101 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
102
103 if (af) {
104 value &= ~(3 << shift);
105 writel(value, gafr);
106 }
107 return 0;
108 }
109
lnw_gpio_get(struct gpio_chip * chip,unsigned offset)110 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
111 {
112 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
113
114 return readl(gplr) & BIT(offset % 32);
115 }
116
lnw_gpio_set(struct gpio_chip * chip,unsigned offset,int value)117 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
118 {
119 void __iomem *gpsr, *gpcr;
120
121 if (value) {
122 gpsr = gpio_reg(chip, offset, GPSR);
123 writel(BIT(offset % 32), gpsr);
124 } else {
125 gpcr = gpio_reg(chip, offset, GPCR);
126 writel(BIT(offset % 32), gpcr);
127 }
128 }
129
lnw_gpio_direction_input(struct gpio_chip * chip,unsigned offset)130 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
131 {
132 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
133 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
134 u32 value;
135 unsigned long flags;
136
137 if (lnw->pdev)
138 pm_runtime_get(&lnw->pdev->dev);
139
140 spin_lock_irqsave(&lnw->lock, flags);
141 value = readl(gpdr);
142 value &= ~BIT(offset % 32);
143 writel(value, gpdr);
144 spin_unlock_irqrestore(&lnw->lock, flags);
145
146 if (lnw->pdev)
147 pm_runtime_put(&lnw->pdev->dev);
148
149 return 0;
150 }
151
lnw_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)152 static int lnw_gpio_direction_output(struct gpio_chip *chip,
153 unsigned offset, int value)
154 {
155 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
156 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
157 unsigned long flags;
158
159 lnw_gpio_set(chip, offset, value);
160
161 if (lnw->pdev)
162 pm_runtime_get(&lnw->pdev->dev);
163
164 spin_lock_irqsave(&lnw->lock, flags);
165 value = readl(gpdr);
166 value |= BIT(offset % 32);
167 writel(value, gpdr);
168 spin_unlock_irqrestore(&lnw->lock, flags);
169
170 if (lnw->pdev)
171 pm_runtime_put(&lnw->pdev->dev);
172
173 return 0;
174 }
175
lnw_gpio_to_irq(struct gpio_chip * chip,unsigned offset)176 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
177 {
178 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
179 return lnw->irq_base + offset;
180 }
181
lnw_irq_type(struct irq_data * d,unsigned type)182 static int lnw_irq_type(struct irq_data *d, unsigned type)
183 {
184 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
185 u32 gpio = d->irq - lnw->irq_base;
186 unsigned long flags;
187 u32 value;
188 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
189 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
190
191 if (gpio >= lnw->chip.ngpio)
192 return -EINVAL;
193
194 if (lnw->pdev)
195 pm_runtime_get(&lnw->pdev->dev);
196
197 spin_lock_irqsave(&lnw->lock, flags);
198 if (type & IRQ_TYPE_EDGE_RISING)
199 value = readl(grer) | BIT(gpio % 32);
200 else
201 value = readl(grer) & (~BIT(gpio % 32));
202 writel(value, grer);
203
204 if (type & IRQ_TYPE_EDGE_FALLING)
205 value = readl(gfer) | BIT(gpio % 32);
206 else
207 value = readl(gfer) & (~BIT(gpio % 32));
208 writel(value, gfer);
209 spin_unlock_irqrestore(&lnw->lock, flags);
210
211 if (lnw->pdev)
212 pm_runtime_put(&lnw->pdev->dev);
213
214 return 0;
215 }
216
lnw_irq_unmask(struct irq_data * d)217 static void lnw_irq_unmask(struct irq_data *d)
218 {
219 }
220
lnw_irq_mask(struct irq_data * d)221 static void lnw_irq_mask(struct irq_data *d)
222 {
223 }
224
225 static struct irq_chip lnw_irqchip = {
226 .name = "LNW-GPIO",
227 .irq_mask = lnw_irq_mask,
228 .irq_unmask = lnw_irq_unmask,
229 .irq_set_type = lnw_irq_type,
230 };
231
232 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
233 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
234 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
235 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
236 { 0, }
237 };
238 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
239
lnw_irq_handler(unsigned irq,struct irq_desc * desc)240 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
241 {
242 struct irq_data *data = irq_desc_get_irq_data(desc);
243 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
244 struct irq_chip *chip = irq_data_get_irq_chip(data);
245 u32 base, gpio, mask;
246 unsigned long pending;
247 void __iomem *gedr;
248
249 /* check GPIO controller to check which pin triggered the interrupt */
250 for (base = 0; base < lnw->chip.ngpio; base += 32) {
251 gedr = gpio_reg(&lnw->chip, base, GEDR);
252 pending = readl(gedr);
253 while (pending) {
254 gpio = __ffs(pending);
255 mask = BIT(gpio);
256 pending &= ~mask;
257 /* Clear before handling so we can't lose an edge */
258 writel(mask, gedr);
259 generic_handle_irq(lnw->irq_base + base + gpio);
260 }
261 }
262
263 chip->irq_eoi(data);
264 }
265
266 #ifdef CONFIG_PM
lnw_gpio_runtime_resume(struct device * dev)267 static int lnw_gpio_runtime_resume(struct device *dev)
268 {
269 return 0;
270 }
271
lnw_gpio_runtime_suspend(struct device * dev)272 static int lnw_gpio_runtime_suspend(struct device *dev)
273 {
274 return 0;
275 }
276
lnw_gpio_runtime_idle(struct device * dev)277 static int lnw_gpio_runtime_idle(struct device *dev)
278 {
279 int err = pm_schedule_suspend(dev, 500);
280
281 if (!err)
282 return 0;
283
284 return -EBUSY;
285 }
286
287 #else
288 #define lnw_gpio_runtime_suspend NULL
289 #define lnw_gpio_runtime_resume NULL
290 #define lnw_gpio_runtime_idle NULL
291 #endif
292
293 static const struct dev_pm_ops lnw_gpio_pm_ops = {
294 .runtime_suspend = lnw_gpio_runtime_suspend,
295 .runtime_resume = lnw_gpio_runtime_resume,
296 .runtime_idle = lnw_gpio_runtime_idle,
297 };
298
lnw_gpio_probe(struct pci_dev * pdev,const struct pci_device_id * id)299 static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
300 const struct pci_device_id *id)
301 {
302 void *base;
303 int i;
304 resource_size_t start, len;
305 struct lnw_gpio *lnw;
306 u32 irq_base;
307 u32 gpio_base;
308 int retval = 0;
309
310 retval = pci_enable_device(pdev);
311 if (retval)
312 goto done;
313
314 retval = pci_request_regions(pdev, "langwell_gpio");
315 if (retval) {
316 dev_err(&pdev->dev, "error requesting resources\n");
317 goto err2;
318 }
319 /* get the irq_base from bar1 */
320 start = pci_resource_start(pdev, 1);
321 len = pci_resource_len(pdev, 1);
322 base = ioremap_nocache(start, len);
323 if (!base) {
324 dev_err(&pdev->dev, "error mapping bar1\n");
325 goto err3;
326 }
327 irq_base = *(u32 *)base;
328 gpio_base = *((u32 *)base + 1);
329 /* release the IO mapping, since we already get the info from bar1 */
330 iounmap(base);
331 /* get the register base from bar0 */
332 start = pci_resource_start(pdev, 0);
333 len = pci_resource_len(pdev, 0);
334 base = ioremap_nocache(start, len);
335 if (!base) {
336 dev_err(&pdev->dev, "error mapping bar0\n");
337 retval = -EFAULT;
338 goto err3;
339 }
340
341 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
342 if (!lnw) {
343 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
344 retval = -ENOMEM;
345 goto err4;
346 }
347 lnw->reg_base = base;
348 lnw->irq_base = irq_base;
349 lnw->chip.label = dev_name(&pdev->dev);
350 lnw->chip.request = lnw_gpio_request;
351 lnw->chip.direction_input = lnw_gpio_direction_input;
352 lnw->chip.direction_output = lnw_gpio_direction_output;
353 lnw->chip.get = lnw_gpio_get;
354 lnw->chip.set = lnw_gpio_set;
355 lnw->chip.to_irq = lnw_gpio_to_irq;
356 lnw->chip.base = gpio_base;
357 lnw->chip.ngpio = id->driver_data;
358 lnw->chip.can_sleep = 0;
359 lnw->pdev = pdev;
360 pci_set_drvdata(pdev, lnw);
361 retval = gpiochip_add(&lnw->chip);
362 if (retval) {
363 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
364 goto err5;
365 }
366 irq_set_handler_data(pdev->irq, lnw);
367 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
368 for (i = 0; i < lnw->chip.ngpio; i++) {
369 irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
370 handle_simple_irq, "demux");
371 irq_set_chip_data(i + lnw->irq_base, lnw);
372 }
373
374 spin_lock_init(&lnw->lock);
375
376 pm_runtime_put_noidle(&pdev->dev);
377 pm_runtime_allow(&pdev->dev);
378
379 goto done;
380 err5:
381 kfree(lnw);
382 err4:
383 iounmap(base);
384 err3:
385 pci_release_regions(pdev);
386 err2:
387 pci_disable_device(pdev);
388 done:
389 return retval;
390 }
391
392 static struct pci_driver lnw_gpio_driver = {
393 .name = "langwell_gpio",
394 .id_table = lnw_gpio_ids,
395 .probe = lnw_gpio_probe,
396 .driver = {
397 .pm = &lnw_gpio_pm_ops,
398 },
399 };
400
401
wp_gpio_probe(struct platform_device * pdev)402 static int __devinit wp_gpio_probe(struct platform_device *pdev)
403 {
404 struct lnw_gpio *lnw;
405 struct gpio_chip *gc;
406 struct resource *rc;
407 int retval = 0;
408
409 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
410 if (!rc)
411 return -EINVAL;
412
413 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
414 if (!lnw) {
415 dev_err(&pdev->dev,
416 "can't allocate whitneypoint_gpio chip data\n");
417 return -ENOMEM;
418 }
419 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
420 if (lnw->reg_base == NULL) {
421 retval = -EINVAL;
422 goto err_kmalloc;
423 }
424 spin_lock_init(&lnw->lock);
425 gc = &lnw->chip;
426 gc->label = dev_name(&pdev->dev);
427 gc->owner = THIS_MODULE;
428 gc->direction_input = lnw_gpio_direction_input;
429 gc->direction_output = lnw_gpio_direction_output;
430 gc->get = lnw_gpio_get;
431 gc->set = lnw_gpio_set;
432 gc->to_irq = NULL;
433 gc->base = 0;
434 gc->ngpio = 64;
435 gc->can_sleep = 0;
436 retval = gpiochip_add(gc);
437 if (retval) {
438 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
439 retval);
440 goto err_ioremap;
441 }
442 platform_set_drvdata(pdev, lnw);
443 return 0;
444 err_ioremap:
445 iounmap(lnw->reg_base);
446 err_kmalloc:
447 kfree(lnw);
448 return retval;
449 }
450
wp_gpio_remove(struct platform_device * pdev)451 static int __devexit wp_gpio_remove(struct platform_device *pdev)
452 {
453 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
454 int err;
455 err = gpiochip_remove(&lnw->chip);
456 if (err)
457 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
458 iounmap(lnw->reg_base);
459 kfree(lnw);
460 platform_set_drvdata(pdev, NULL);
461 return 0;
462 }
463
464 static struct platform_driver wp_gpio_driver = {
465 .probe = wp_gpio_probe,
466 .remove = __devexit_p(wp_gpio_remove),
467 .driver = {
468 .name = "wp_gpio",
469 .owner = THIS_MODULE,
470 },
471 };
472
lnw_gpio_init(void)473 static int __init lnw_gpio_init(void)
474 {
475 int ret;
476 ret = pci_register_driver(&lnw_gpio_driver);
477 if (ret < 0)
478 return ret;
479 ret = platform_driver_register(&wp_gpio_driver);
480 if (ret < 0)
481 pci_unregister_driver(&lnw_gpio_driver);
482 return ret;
483 }
484
485 device_initcall(lnw_gpio_init);
486