1 /* 2 * Xtensa processor core configuration information. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (c) 1999-2008 Tensilica Inc. 9 */ 10 11 #ifndef _XTENSA_CORE_CONFIGURATION_H 12 #define _XTENSA_CORE_CONFIGURATION_H 13 14 15 /**************************************************************************** 16 Parameters Useful for Any Code, USER or PRIVILEGED 17 ****************************************************************************/ 18 19 /* 20 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 21 * configured, and a value of 0 otherwise. These macros are always defined. 22 */ 23 24 25 /*---------------------------------------------------------------------- 26 ISA 27 ----------------------------------------------------------------------*/ 28 29 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 30 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 31 #define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ 32 #define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ 33 #define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ 34 #define XCHAL_HAVE_DEBUG 1 /* debug option */ 35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 37 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 38 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 39 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 40 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 41 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 42 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 43 #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ 44 #define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ 45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 47 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 48 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 49 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 50 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 51 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 52 #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 53 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 54 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 55 #define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */ 56 #define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ 57 #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 58 #define XCHAL_HAVE_FULL_RESET 0 /* all regs/state reset */ 59 #define XCHAL_NUM_CONTEXTS 1 /* */ 60 #define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ 61 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 62 #define XCHAL_HAVE_PRID 0 /* processor ID register */ 63 #define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ 64 #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 65 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 66 #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 67 #define XCHAL_HAVE_MAC16 0 /* MAC16 package */ 68 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 69 #define XCHAL_HAVE_FP 1 /* floating point pkg */ 70 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 71 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 72 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 73 74 75 /*---------------------------------------------------------------------- 76 MISC 77 ----------------------------------------------------------------------*/ 78 79 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 80 #define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ 81 #define XCHAL_DATA_WIDTH 16 /* data width in bytes */ 82 /* In T1050, applies to selected core load and store instructions (see ISA): */ 83 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 84 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 85 86 #define XCHAL_SW_VERSION 701001 /* sw version of this header */ 87 88 #define XCHAL_CORE_ID "stretch_bali" /* alphanum core name 89 (CoreID) set in the Xtensa 90 Processor Generator */ 91 92 #define XCHAL_BUILD_UNIQUE_ID 0x000104B9 /* 22-bit sw build ID */ 93 94 /* 95 * These definitions describe the hardware targeted by this software. 96 */ 97 #define XCHAL_HW_CONFIGID0 0xC2F3F9FE /* ConfigID hi 32 bits*/ 98 #define XCHAL_HW_CONFIGID1 0x054104B9 /* ConfigID lo 32 bits*/ 99 #define XCHAL_HW_VERSION_NAME "LX1.0.2" /* full version name */ 100 #define XCHAL_HW_VERSION_MAJOR 2100 /* major ver# of targeted hw */ 101 #define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ 102 #define XCHAL_HW_VERSION 210002 /* major*100+minor */ 103 #define XCHAL_HW_REL_LX1 1 104 #define XCHAL_HW_REL_LX1_0 1 105 #define XCHAL_HW_REL_LX1_0_2 1 106 #define XCHAL_HW_CONFIGID_RELIABLE 1 107 /* If software targets a *range* of hardware versions, these are the bounds: */ 108 #define XCHAL_HW_MIN_VERSION_MAJOR 2100 /* major v of earliest tgt hw */ 109 #define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ 110 #define XCHAL_HW_MIN_VERSION 210002 /* earliest targeted hw */ 111 #define XCHAL_HW_MAX_VERSION_MAJOR 2100 /* major v of latest tgt hw */ 112 #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ 113 #define XCHAL_HW_MAX_VERSION 210002 /* latest targeted hw */ 114 115 116 /*---------------------------------------------------------------------- 117 CACHE 118 ----------------------------------------------------------------------*/ 119 120 #define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ 121 #define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ 122 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ 123 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ 124 125 #define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ 126 #define XCHAL_DCACHE_SIZE 32768 /* D-cache size in bytes or 0 */ 127 128 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 129 130 131 132 133 /**************************************************************************** 134 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 135 ****************************************************************************/ 136 137 138 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 139 140 /*---------------------------------------------------------------------- 141 CACHE 142 ----------------------------------------------------------------------*/ 143 144 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 145 146 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 147 148 /* Number of cache sets in log2(lines per way): */ 149 #define XCHAL_ICACHE_SETWIDTH 9 150 #define XCHAL_DCACHE_SETWIDTH 10 151 152 /* Cache set associativity (number of ways): */ 153 #define XCHAL_ICACHE_WAYS 4 154 #define XCHAL_DCACHE_WAYS 2 155 156 /* Cache features: */ 157 #define XCHAL_ICACHE_LINE_LOCKABLE 1 158 #define XCHAL_DCACHE_LINE_LOCKABLE 0 159 #define XCHAL_ICACHE_ECC_PARITY 0 160 #define XCHAL_DCACHE_ECC_PARITY 0 161 162 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 163 #define XCHAL_CA_BITS 4 164 165 166 /*---------------------------------------------------------------------- 167 INTERNAL I/D RAM/ROMs and XLMI 168 ----------------------------------------------------------------------*/ 169 170 #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 171 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 172 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 173 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ 174 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 175 #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ 176 177 /* Data RAM 0: */ 178 #define XCHAL_DATARAM0_VADDR 0x3FFF0000 179 #define XCHAL_DATARAM0_PADDR 0x3FFF0000 180 #define XCHAL_DATARAM0_SIZE 65536 181 #define XCHAL_DATARAM0_ECC_PARITY 0 182 183 /* XLMI Port 0: */ 184 #define XCHAL_XLMI0_VADDR 0x37F80000 185 #define XCHAL_XLMI0_PADDR 0x37F80000 186 #define XCHAL_XLMI0_SIZE 262144 187 #define XCHAL_XLMI0_ECC_PARITY 0 188 189 190 /*---------------------------------------------------------------------- 191 INTERRUPTS and TIMERS 192 ----------------------------------------------------------------------*/ 193 194 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 195 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 196 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 197 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 198 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 199 #define XCHAL_NUM_INTERRUPTS 27 /* number of interrupts */ 200 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 201 #define XCHAL_NUM_EXTINTERRUPTS 20 /* num of external interrupts */ 202 #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels 203 (not including level zero) */ 204 #define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */ 205 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 206 207 /* Masks of interrupts at each interrupt level: */ 208 #define XCHAL_INTLEVEL1_MASK 0x01F07FFF 209 #define XCHAL_INTLEVEL2_MASK 0x02018000 210 #define XCHAL_INTLEVEL3_MASK 0x04060000 211 #define XCHAL_INTLEVEL4_MASK 0x00000000 212 #define XCHAL_INTLEVEL5_MASK 0x00080000 213 #define XCHAL_INTLEVEL6_MASK 0x00000000 214 #define XCHAL_INTLEVEL7_MASK 0x00000000 215 216 /* Masks of interrupts at each range 1..n of interrupt levels: */ 217 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x01F07FFF 218 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x03F1FFFF 219 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x07F7FFFF 220 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x07F7FFFF 221 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x07FFFFFF 222 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x07FFFFFF 223 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x07FFFFFF 224 225 /* Level of each interrupt: */ 226 #define XCHAL_INT0_LEVEL 1 227 #define XCHAL_INT1_LEVEL 1 228 #define XCHAL_INT2_LEVEL 1 229 #define XCHAL_INT3_LEVEL 1 230 #define XCHAL_INT4_LEVEL 1 231 #define XCHAL_INT5_LEVEL 1 232 #define XCHAL_INT6_LEVEL 1 233 #define XCHAL_INT7_LEVEL 1 234 #define XCHAL_INT8_LEVEL 1 235 #define XCHAL_INT9_LEVEL 1 236 #define XCHAL_INT10_LEVEL 1 237 #define XCHAL_INT11_LEVEL 1 238 #define XCHAL_INT12_LEVEL 1 239 #define XCHAL_INT13_LEVEL 1 240 #define XCHAL_INT14_LEVEL 1 241 #define XCHAL_INT15_LEVEL 2 242 #define XCHAL_INT16_LEVEL 2 243 #define XCHAL_INT17_LEVEL 3 244 #define XCHAL_INT18_LEVEL 3 245 #define XCHAL_INT19_LEVEL 5 246 #define XCHAL_INT20_LEVEL 1 247 #define XCHAL_INT21_LEVEL 1 248 #define XCHAL_INT22_LEVEL 1 249 #define XCHAL_INT23_LEVEL 1 250 #define XCHAL_INT24_LEVEL 1 251 #define XCHAL_INT25_LEVEL 2 252 #define XCHAL_INT26_LEVEL 3 253 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ 254 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 255 #define XCHAL_NMILEVEL 5 /* NMI "level" (for use with 256 EXCSAVE/EPS/EPC_n, RFI n) */ 257 258 /* Type of each interrupt: */ 259 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 260 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 261 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 262 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 263 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 264 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 265 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 266 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 267 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 268 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 269 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 270 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 271 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 272 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 273 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 274 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 275 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 276 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 277 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 278 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_NMI 279 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_SOFTWARE 280 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE 281 #define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE 282 #define XCHAL_INT23_TYPE XTHAL_INTTYPE_SOFTWARE 283 #define XCHAL_INT24_TYPE XTHAL_INTTYPE_TIMER 284 #define XCHAL_INT25_TYPE XTHAL_INTTYPE_TIMER 285 #define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER 286 287 /* Masks of interrupts for each type of interrupt: */ 288 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xF8000000 289 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00F00000 290 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 291 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0007FFFF 292 #define XCHAL_INTTYPE_MASK_TIMER 0x07000000 293 #define XCHAL_INTTYPE_MASK_NMI 0x00080000 294 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 295 296 /* Interrupt numbers assigned to specific interrupt sources: */ 297 #define XCHAL_TIMER0_INTERRUPT 24 /* CCOMPARE0 */ 298 #define XCHAL_TIMER1_INTERRUPT 25 /* CCOMPARE1 */ 299 #define XCHAL_TIMER2_INTERRUPT 26 /* CCOMPARE2 */ 300 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 301 #define XCHAL_NMI_INTERRUPT 19 /* non-maskable interrupt */ 302 303 /* Interrupt numbers for levels at which only one interrupt is configured: */ 304 #define XCHAL_INTLEVEL5_NUM 19 305 /* (There are many interrupts each at level(s) 1, 2, 3.) */ 306 307 308 /* 309 * External interrupt vectors/levels. 310 * These macros describe how Xtensa processor interrupt numbers 311 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 312 * map to external BInterrupt<n> pins, for those interrupts 313 * configured as external (level-triggered, edge-triggered, or NMI). 314 * See the Xtensa processor databook for more details. 315 */ 316 317 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 318 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 319 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 320 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 321 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 322 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 323 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 324 #define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ 325 #define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ 326 #define XCHAL_EXTINT8_NUM 8 /* (intlevel 1) */ 327 #define XCHAL_EXTINT9_NUM 9 /* (intlevel 1) */ 328 #define XCHAL_EXTINT10_NUM 10 /* (intlevel 1) */ 329 #define XCHAL_EXTINT11_NUM 11 /* (intlevel 1) */ 330 #define XCHAL_EXTINT12_NUM 12 /* (intlevel 1) */ 331 #define XCHAL_EXTINT13_NUM 13 /* (intlevel 1) */ 332 #define XCHAL_EXTINT14_NUM 14 /* (intlevel 1) */ 333 #define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */ 334 #define XCHAL_EXTINT16_NUM 16 /* (intlevel 2) */ 335 #define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */ 336 #define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */ 337 #define XCHAL_EXTINT19_NUM 19 /* (intlevel 5) */ 338 339 340 /*---------------------------------------------------------------------- 341 EXCEPTIONS and VECTORS 342 ----------------------------------------------------------------------*/ 343 344 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 345 number: 1 == XEA1 (old) 346 2 == XEA2 (new) 347 0 == XEAX (extern) */ 348 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 349 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 350 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 351 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 352 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 353 #define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */ 354 #define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */ 355 356 #define XCHAL_RESET_VECOFS 0x00000000 357 #define XCHAL_RESET_VECTOR_VADDR 0x3FFE03D0 358 #define XCHAL_RESET_VECTOR_PADDR 0x3FFE03D0 359 #define XCHAL_USER_VECOFS 0x00000000 360 #define XCHAL_USER_VECTOR_VADDR 0x40000220 361 #define XCHAL_USER_VECTOR_PADDR 0x40000220 362 #define XCHAL_KERNEL_VECOFS 0x00000000 363 #define XCHAL_KERNEL_VECTOR_VADDR 0x40000200 364 #define XCHAL_KERNEL_VECTOR_PADDR 0x40000200 365 #define XCHAL_DOUBLEEXC_VECOFS 0x00000000 366 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400002A0 367 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400002A0 368 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 369 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 370 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 371 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 372 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 373 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 374 #define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 375 #define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 376 #define XCHAL_INTLEVEL2_VECOFS 0x00000000 377 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000240 378 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000240 379 #define XCHAL_INTLEVEL3_VECOFS 0x00000000 380 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x40000260 381 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x40000260 382 #define XCHAL_INTLEVEL4_VECOFS 0x00000000 383 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000390 384 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000390 385 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS 386 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR 387 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR 388 #define XCHAL_NMI_VECOFS 0x00000000 389 #define XCHAL_NMI_VECTOR_VADDR 0x400003B0 390 #define XCHAL_NMI_VECTOR_PADDR 0x400003B0 391 #define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS 392 #define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 393 #define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 394 395 396 /*---------------------------------------------------------------------- 397 DEBUG 398 ----------------------------------------------------------------------*/ 399 400 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 401 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 402 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 403 #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ 404 405 406 /*---------------------------------------------------------------------- 407 MMU 408 ----------------------------------------------------------------------*/ 409 410 /* See core-matmap.h header file for more details. */ 411 412 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 413 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 414 #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ 415 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 416 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ 417 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 418 #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table 419 [autorefill] and protection) 420 usable for an MMU-based OS */ 421 /* If none of the above last 4 are set, it's a custom TLB configuration. */ 422 423 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ 424 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ 425 #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ 426 427 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 428 429 430 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 431 432