1 #include <linux/export.h>
2 #include <linux/init.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <asm/processor.h>
9 #include <asm/apic.h>
10 #include <asm/cpu.h>
11 #include <asm/pci-direct.h>
12
13 #ifdef CONFIG_X86_64
14 # include <asm/numa_64.h>
15 # include <asm/mmconfig.h>
16 # include <asm/cacheflush.h>
17 #endif
18
19 #include "cpu.h"
20
21 #ifdef CONFIG_X86_32
22 /*
23 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
24 * misexecution of code under Linux. Owners of such processors should
25 * contact AMD for precise details and a CPU swap.
26 *
27 * See http://www.multimania.com/poulot/k6bug.html
28 * http://www.amd.com/K6/k6docs/revgd.html
29 *
30 * The following test is erm.. interesting. AMD neglected to up
31 * the chip setting when fixing the bug but they also tweaked some
32 * performance at the same time..
33 */
34
35 extern void vide(void);
36 __asm__(".align 4\nvide: ret");
37
init_amd_k5(struct cpuinfo_x86 * c)38 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
39 {
40 /*
41 * General Systems BIOSen alias the cpu frequency registers
42 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
43 * drivers subsequently pokes it, and changes the CPU speed.
44 * Workaround : Remove the unneeded alias.
45 */
46 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
47 #define CBAR_ENB (0x80000000)
48 #define CBAR_KEY (0X000000CB)
49 if (c->x86_model == 9 || c->x86_model == 10) {
50 if (inl(CBAR) & CBAR_ENB)
51 outl(0 | CBAR_KEY, CBAR);
52 }
53 }
54
55
init_amd_k6(struct cpuinfo_x86 * c)56 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
57 {
58 u32 l, h;
59 int mbytes = num_physpages >> (20-PAGE_SHIFT);
60
61 if (c->x86_model < 6) {
62 /* Based on AMD doc 20734R - June 2000 */
63 if (c->x86_model == 0) {
64 clear_cpu_cap(c, X86_FEATURE_APIC);
65 set_cpu_cap(c, X86_FEATURE_PGE);
66 }
67 return;
68 }
69
70 if (c->x86_model == 6 && c->x86_mask == 1) {
71 const int K6_BUG_LOOP = 1000000;
72 int n;
73 void (*f_vide)(void);
74 unsigned long d, d2;
75
76 printk(KERN_INFO "AMD K6 stepping B detected - ");
77
78 /*
79 * It looks like AMD fixed the 2.6.2 bug and improved indirect
80 * calls at the same time.
81 */
82
83 n = K6_BUG_LOOP;
84 f_vide = vide;
85 rdtscl(d);
86 while (n--)
87 f_vide();
88 rdtscl(d2);
89 d = d2-d;
90
91 if (d > 20*K6_BUG_LOOP)
92 printk(KERN_CONT
93 "system stability may be impaired when more than 32 MB are used.\n");
94 else
95 printk(KERN_CONT "probably OK (after B9730xxxx).\n");
96 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
97 }
98
99 /* K6 with old style WHCR */
100 if (c->x86_model < 8 ||
101 (c->x86_model == 8 && c->x86_mask < 8)) {
102 /* We can only write allocate on the low 508Mb */
103 if (mbytes > 508)
104 mbytes = 508;
105
106 rdmsr(MSR_K6_WHCR, l, h);
107 if ((l&0x0000FFFF) == 0) {
108 unsigned long flags;
109 l = (1<<0)|((mbytes/4)<<1);
110 local_irq_save(flags);
111 wbinvd();
112 wrmsr(MSR_K6_WHCR, l, h);
113 local_irq_restore(flags);
114 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
115 mbytes);
116 }
117 return;
118 }
119
120 if ((c->x86_model == 8 && c->x86_mask > 7) ||
121 c->x86_model == 9 || c->x86_model == 13) {
122 /* The more serious chips .. */
123
124 if (mbytes > 4092)
125 mbytes = 4092;
126
127 rdmsr(MSR_K6_WHCR, l, h);
128 if ((l&0xFFFF0000) == 0) {
129 unsigned long flags;
130 l = ((mbytes>>2)<<22)|(1<<16);
131 local_irq_save(flags);
132 wbinvd();
133 wrmsr(MSR_K6_WHCR, l, h);
134 local_irq_restore(flags);
135 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
136 mbytes);
137 }
138
139 return;
140 }
141
142 if (c->x86_model == 10) {
143 /* AMD Geode LX is model 10 */
144 /* placeholder for any needed mods */
145 return;
146 }
147 }
148
amd_k7_smp_check(struct cpuinfo_x86 * c)149 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
150 {
151 /* calling is from identify_secondary_cpu() ? */
152 if (!c->cpu_index)
153 return;
154
155 /*
156 * Certain Athlons might work (for various values of 'work') in SMP
157 * but they are not certified as MP capable.
158 */
159 /* Athlon 660/661 is valid. */
160 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
161 (c->x86_mask == 1)))
162 goto valid_k7;
163
164 /* Duron 670 is valid */
165 if ((c->x86_model == 7) && (c->x86_mask == 0))
166 goto valid_k7;
167
168 /*
169 * Athlon 662, Duron 671, and Athlon >model 7 have capability
170 * bit. It's worth noting that the A5 stepping (662) of some
171 * Athlon XP's have the MP bit set.
172 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
173 * more.
174 */
175 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
176 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
177 (c->x86_model > 7))
178 if (cpu_has_mp)
179 goto valid_k7;
180
181 /* If we get here, not a certified SMP capable AMD system. */
182
183 /*
184 * Don't taint if we are running SMP kernel on a single non-MP
185 * approved Athlon
186 */
187 WARN_ONCE(1, "WARNING: This combination of AMD"
188 " processors is not suitable for SMP.\n");
189 if (!test_taint(TAINT_UNSAFE_SMP))
190 add_taint(TAINT_UNSAFE_SMP);
191
192 valid_k7:
193 ;
194 }
195
init_amd_k7(struct cpuinfo_x86 * c)196 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
197 {
198 u32 l, h;
199
200 /*
201 * Bit 15 of Athlon specific MSR 15, needs to be 0
202 * to enable SSE on Palomino/Morgan/Barton CPU's.
203 * If the BIOS didn't enable it already, enable it here.
204 */
205 if (c->x86_model >= 6 && c->x86_model <= 10) {
206 if (!cpu_has(c, X86_FEATURE_XMM)) {
207 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
208 rdmsr(MSR_K7_HWCR, l, h);
209 l &= ~0x00008000;
210 wrmsr(MSR_K7_HWCR, l, h);
211 set_cpu_cap(c, X86_FEATURE_XMM);
212 }
213 }
214
215 /*
216 * It's been determined by AMD that Athlons since model 8 stepping 1
217 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
218 * As per AMD technical note 27212 0.2
219 */
220 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
221 rdmsr(MSR_K7_CLK_CTL, l, h);
222 if ((l & 0xfff00000) != 0x20000000) {
223 printk(KERN_INFO
224 "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
225 l, ((l & 0x000fffff)|0x20000000));
226 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
227 }
228 }
229
230 set_cpu_cap(c, X86_FEATURE_K7);
231
232 amd_k7_smp_check(c);
233 }
234 #endif
235
236 #ifdef CONFIG_NUMA
237 /*
238 * To workaround broken NUMA config. Read the comment in
239 * srat_detect_node().
240 */
nearby_node(int apicid)241 static int __cpuinit nearby_node(int apicid)
242 {
243 int i, node;
244
245 for (i = apicid - 1; i >= 0; i--) {
246 node = __apicid_to_node[i];
247 if (node != NUMA_NO_NODE && node_online(node))
248 return node;
249 }
250 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
251 node = __apicid_to_node[i];
252 if (node != NUMA_NO_NODE && node_online(node))
253 return node;
254 }
255 return first_node(node_online_map); /* Shouldn't happen */
256 }
257 #endif
258
259 /*
260 * Fixup core topology information for
261 * (1) AMD multi-node processors
262 * Assumption: Number of cores in each internal node is the same.
263 * (2) AMD processors supporting compute units
264 */
265 #ifdef CONFIG_X86_HT
amd_get_topology(struct cpuinfo_x86 * c)266 static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
267 {
268 u32 nodes, cores_per_cu = 1;
269 u8 node_id;
270 int cpu = smp_processor_id();
271
272 /* get information required for multi-node processors */
273 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
274 u32 eax, ebx, ecx, edx;
275
276 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
277 nodes = ((ecx >> 8) & 7) + 1;
278 node_id = ecx & 7;
279
280 /* get compute unit information */
281 smp_num_siblings = ((ebx >> 8) & 3) + 1;
282 c->compute_unit_id = ebx & 0xff;
283 cores_per_cu += ((ebx >> 8) & 3);
284 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
285 u64 value;
286
287 rdmsrl(MSR_FAM10H_NODE_ID, value);
288 nodes = ((value >> 3) & 7) + 1;
289 node_id = value & 7;
290 } else
291 return;
292
293 /* fixup multi-node processor information */
294 if (nodes > 1) {
295 u32 cores_per_node;
296 u32 cus_per_node;
297
298 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
299 cores_per_node = c->x86_max_cores / nodes;
300 cus_per_node = cores_per_node / cores_per_cu;
301
302 /* store NodeID, use llc_shared_map to store sibling info */
303 per_cpu(cpu_llc_id, cpu) = node_id;
304
305 /* core id has to be in the [0 .. cores_per_node - 1] range */
306 c->cpu_core_id %= cores_per_node;
307 c->compute_unit_id %= cus_per_node;
308 }
309 }
310 #endif
311
312 /*
313 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
314 * Assumes number of cores is a power of two.
315 */
amd_detect_cmp(struct cpuinfo_x86 * c)316 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
317 {
318 #ifdef CONFIG_X86_HT
319 unsigned bits;
320 int cpu = smp_processor_id();
321
322 bits = c->x86_coreid_bits;
323 /* Low order bits define the core id (index of core in socket) */
324 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
325 /* Convert the initial APIC ID into the socket ID */
326 c->phys_proc_id = c->initial_apicid >> bits;
327 /* use socket ID also for last level cache */
328 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
329 amd_get_topology(c);
330 #endif
331 }
332
amd_get_nb_id(int cpu)333 int amd_get_nb_id(int cpu)
334 {
335 int id = 0;
336 #ifdef CONFIG_SMP
337 id = per_cpu(cpu_llc_id, cpu);
338 #endif
339 return id;
340 }
341 EXPORT_SYMBOL_GPL(amd_get_nb_id);
342
srat_detect_node(struct cpuinfo_x86 * c)343 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
344 {
345 #ifdef CONFIG_NUMA
346 int cpu = smp_processor_id();
347 int node;
348 unsigned apicid = c->apicid;
349
350 node = numa_cpu_node(cpu);
351 if (node == NUMA_NO_NODE)
352 node = per_cpu(cpu_llc_id, cpu);
353
354 /*
355 * If core numbers are inconsistent, it's likely a multi-fabric platform,
356 * so invoke platform-specific handler
357 */
358 if (c->phys_proc_id != node)
359 x86_cpuinit.fixup_cpu_id(c, node);
360
361 if (!node_online(node)) {
362 /*
363 * Two possibilities here:
364 *
365 * - The CPU is missing memory and no node was created. In
366 * that case try picking one from a nearby CPU.
367 *
368 * - The APIC IDs differ from the HyperTransport node IDs
369 * which the K8 northbridge parsing fills in. Assume
370 * they are all increased by a constant offset, but in
371 * the same order as the HT nodeids. If that doesn't
372 * result in a usable node fall back to the path for the
373 * previous case.
374 *
375 * This workaround operates directly on the mapping between
376 * APIC ID and NUMA node, assuming certain relationship
377 * between APIC ID, HT node ID and NUMA topology. As going
378 * through CPU mapping may alter the outcome, directly
379 * access __apicid_to_node[].
380 */
381 int ht_nodeid = c->initial_apicid;
382
383 if (ht_nodeid >= 0 &&
384 __apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
385 node = __apicid_to_node[ht_nodeid];
386 /* Pick a nearby node */
387 if (!node_online(node))
388 node = nearby_node(apicid);
389 }
390 numa_set_node(cpu, node);
391 #endif
392 }
393
early_init_amd_mc(struct cpuinfo_x86 * c)394 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
395 {
396 #ifdef CONFIG_X86_HT
397 unsigned bits, ecx;
398
399 /* Multi core CPU? */
400 if (c->extended_cpuid_level < 0x80000008)
401 return;
402
403 ecx = cpuid_ecx(0x80000008);
404
405 c->x86_max_cores = (ecx & 0xff) + 1;
406
407 /* CPU telling us the core id bits shift? */
408 bits = (ecx >> 12) & 0xF;
409
410 /* Otherwise recompute */
411 if (bits == 0) {
412 while ((1 << bits) < c->x86_max_cores)
413 bits++;
414 }
415
416 c->x86_coreid_bits = bits;
417 #endif
418 }
419
bsp_init_amd(struct cpuinfo_x86 * c)420 static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c)
421 {
422 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
423
424 if (c->x86 > 0x10 ||
425 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
426 u64 val;
427
428 rdmsrl(MSR_K7_HWCR, val);
429 if (!(val & BIT(24)))
430 printk(KERN_WARNING FW_BUG "TSC doesn't count "
431 "with P0 frequency!\n");
432 }
433 }
434
435 if (c->x86 == 0x15) {
436 unsigned long upperbit;
437 u32 cpuid, assoc;
438
439 cpuid = cpuid_edx(0x80000005);
440 assoc = cpuid >> 16 & 0xff;
441 upperbit = ((cpuid >> 24) << 10) / assoc;
442
443 va_align.mask = (upperbit - 1) & PAGE_MASK;
444 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
445 }
446 }
447
early_init_amd(struct cpuinfo_x86 * c)448 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
449 {
450 early_init_amd_mc(c);
451
452 /*
453 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
454 * with P/T states and does not stop in deep C-states
455 */
456 if (c->x86_power & (1 << 8)) {
457 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
458 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
459 }
460
461 #ifdef CONFIG_X86_64
462 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
463 #else
464 /* Set MTRR capability flag if appropriate */
465 if (c->x86 == 5)
466 if (c->x86_model == 13 || c->x86_model == 9 ||
467 (c->x86_model == 8 && c->x86_mask >= 8))
468 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
469 #endif
470 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
471 /* check CPU config space for extended APIC ID */
472 if (cpu_has_apic && c->x86 >= 0xf) {
473 unsigned int val;
474 val = read_pci_config(0, 24, 0, 0x68);
475 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
476 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
477 }
478 #endif
479 }
480
init_amd(struct cpuinfo_x86 * c)481 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
482 {
483 u32 dummy;
484
485 #ifdef CONFIG_SMP
486 unsigned long long value;
487
488 /*
489 * Disable TLB flush filter by setting HWCR.FFDIS on K8
490 * bit 6 of msr C001_0015
491 *
492 * Errata 63 for SH-B3 steppings
493 * Errata 122 for all steppings (F+ have it disabled by default)
494 */
495 if (c->x86 == 0xf) {
496 rdmsrl(MSR_K7_HWCR, value);
497 value |= 1 << 6;
498 wrmsrl(MSR_K7_HWCR, value);
499 }
500 #endif
501
502 early_init_amd(c);
503
504 /*
505 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
506 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
507 */
508 clear_cpu_cap(c, 0*32+31);
509
510 #ifdef CONFIG_X86_64
511 /* On C+ stepping K8 rep microcode works well for copy/memset */
512 if (c->x86 == 0xf) {
513 u32 level;
514
515 level = cpuid_eax(1);
516 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
517 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
518
519 /*
520 * Some BIOSes incorrectly force this feature, but only K8
521 * revision D (model = 0x14) and later actually support it.
522 * (AMD Erratum #110, docId: 25759).
523 */
524 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
525 u64 val;
526
527 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
528 if (!rdmsrl_amd_safe(0xc001100d, &val)) {
529 val &= ~(1ULL << 32);
530 wrmsrl_amd_safe(0xc001100d, val);
531 }
532 }
533
534 }
535 if (c->x86 >= 0x10)
536 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
537
538 /* get apicid instead of initial apic id from cpuid */
539 c->apicid = hard_smp_processor_id();
540 #else
541
542 /*
543 * FIXME: We should handle the K5 here. Set up the write
544 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
545 * no bus pipeline)
546 */
547
548 switch (c->x86) {
549 case 4:
550 init_amd_k5(c);
551 break;
552 case 5:
553 init_amd_k6(c);
554 break;
555 case 6: /* An Athlon/Duron */
556 init_amd_k7(c);
557 break;
558 }
559
560 /* K6s reports MCEs but don't actually have all the MSRs */
561 if (c->x86 < 6)
562 clear_cpu_cap(c, X86_FEATURE_MCE);
563 #endif
564
565 /* Enable workaround for FXSAVE leak */
566 if (c->x86 >= 6)
567 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
568
569 if (!c->x86_model_id[0]) {
570 switch (c->x86) {
571 case 0xf:
572 /* Should distinguish Models here, but this is only
573 a fallback anyways. */
574 strcpy(c->x86_model_id, "Hammer");
575 break;
576 }
577 }
578
579 cpu_detect_cache_sizes(c);
580
581 /* Multi core CPU? */
582 if (c->extended_cpuid_level >= 0x80000008) {
583 amd_detect_cmp(c);
584 srat_detect_node(c);
585 }
586
587 #ifdef CONFIG_X86_32
588 detect_ht(c);
589 #endif
590
591 if (c->extended_cpuid_level >= 0x80000006) {
592 if (cpuid_edx(0x80000006) & 0xf000)
593 num_cache_leaves = 4;
594 else
595 num_cache_leaves = 3;
596 }
597
598 if (c->x86 >= 0xf)
599 set_cpu_cap(c, X86_FEATURE_K8);
600
601 if (cpu_has_xmm2) {
602 /* MFENCE stops RDTSC speculation */
603 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
604 }
605
606 #ifdef CONFIG_X86_64
607 if (c->x86 == 0x10) {
608 /* do this for boot cpu */
609 if (c == &boot_cpu_data)
610 check_enable_amd_mmconf_dmi();
611
612 fam10h_check_enable_mmcfg();
613 }
614
615 if (c == &boot_cpu_data && c->x86 >= 0xf) {
616 unsigned long long tseg;
617
618 /*
619 * Split up direct mapping around the TSEG SMM area.
620 * Don't do it for gbpages because there seems very little
621 * benefit in doing so.
622 */
623 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
624 printk(KERN_DEBUG "tseg: %010llx\n", tseg);
625 if ((tseg>>PMD_SHIFT) <
626 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
627 ((tseg>>PMD_SHIFT) <
628 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
629 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
630 set_memory_4k((unsigned long)__va(tseg), 1);
631 }
632 }
633 #endif
634
635 /*
636 * Family 0x12 and above processors have APIC timer
637 * running in deep C states.
638 */
639 if (c->x86 > 0x11)
640 set_cpu_cap(c, X86_FEATURE_ARAT);
641
642 /*
643 * Disable GART TLB Walk Errors on Fam10h. We do this here
644 * because this is always needed when GART is enabled, even in a
645 * kernel which has no MCE support built in.
646 */
647 if (c->x86 == 0x10) {
648 /*
649 * BIOS should disable GartTlbWlk Errors themself. If
650 * it doesn't do it here as suggested by the BKDG.
651 *
652 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
653 */
654 u64 mask;
655 int err;
656
657 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
658 if (err == 0) {
659 mask |= (1 << 10);
660 checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
661 }
662 }
663
664 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
665 }
666
667 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)668 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
669 unsigned int size)
670 {
671 /* AMD errata T13 (order #21922) */
672 if ((c->x86 == 6)) {
673 /* Duron Rev A0 */
674 if (c->x86_model == 3 && c->x86_mask == 0)
675 size = 64;
676 /* Tbird rev A1/A2 */
677 if (c->x86_model == 4 &&
678 (c->x86_mask == 0 || c->x86_mask == 1))
679 size = 256;
680 }
681 return size;
682 }
683 #endif
684
685 static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
686 .c_vendor = "AMD",
687 .c_ident = { "AuthenticAMD" },
688 #ifdef CONFIG_X86_32
689 .c_models = {
690 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
691 {
692 [3] = "486 DX/2",
693 [7] = "486 DX/2-WB",
694 [8] = "486 DX/4",
695 [9] = "486 DX/4-WB",
696 [14] = "Am5x86-WT",
697 [15] = "Am5x86-WB"
698 }
699 },
700 },
701 .c_size_cache = amd_size_cache,
702 #endif
703 .c_early_init = early_init_amd,
704 .c_bsp_init = bsp_init_amd,
705 .c_init = init_amd,
706 .c_x86_vendor = X86_VENDOR_AMD,
707 };
708
709 cpu_dev_register(amd_cpu_dev);
710
711 /*
712 * AMD errata checking
713 *
714 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
715 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
716 * have an OSVW id assigned, which it takes as first argument. Both take a
717 * variable number of family-specific model-stepping ranges created by
718 * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
719 * int[] in arch/x86/include/asm/processor.h.
720 *
721 * Example:
722 *
723 * const int amd_erratum_319[] =
724 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
725 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
726 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
727 */
728
729 const int amd_erratum_400[] =
730 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
731 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
732 EXPORT_SYMBOL_GPL(amd_erratum_400);
733
734 const int amd_erratum_383[] =
735 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
736 EXPORT_SYMBOL_GPL(amd_erratum_383);
737
cpu_has_amd_erratum(const int * erratum)738 bool cpu_has_amd_erratum(const int *erratum)
739 {
740 struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info);
741 int osvw_id = *erratum++;
742 u32 range;
743 u32 ms;
744
745 /*
746 * If called early enough that current_cpu_data hasn't been initialized
747 * yet, fall back to boot_cpu_data.
748 */
749 if (cpu->x86 == 0)
750 cpu = &boot_cpu_data;
751
752 if (cpu->x86_vendor != X86_VENDOR_AMD)
753 return false;
754
755 if (osvw_id >= 0 && osvw_id < 65536 &&
756 cpu_has(cpu, X86_FEATURE_OSVW)) {
757 u64 osvw_len;
758
759 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
760 if (osvw_id < osvw_len) {
761 u64 osvw_bits;
762
763 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
764 osvw_bits);
765 return osvw_bits & (1ULL << (osvw_id & 0x3f));
766 }
767 }
768
769 /* OSVW unavailable or ID unknown, match family-model-stepping range */
770 ms = (cpu->x86_model << 4) | cpu->x86_mask;
771 while ((range = *erratum++))
772 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
773 (ms >= AMD_MODEL_RANGE_START(range)) &&
774 (ms <= AMD_MODEL_RANGE_END(range)))
775 return true;
776
777 return false;
778 }
779
780 EXPORT_SYMBOL_GPL(cpu_has_amd_erratum);
781