1 /*
2 * apb_timer.c: Driver for Langwell APB timers
3 *
4 * (C) Copyright 2009 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * Note:
13 * Langwell is the south complex of Intel Moorestown MID platform. There are
14 * eight external timers in total that can be used by the operating system.
15 * The timer information, such as frequency and addresses, is provided to the
16 * OS via SFI tables.
17 * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
18 * individual redirection table entries (RTE).
19 * Unlike HPET, there is no master counter, therefore one of the timers are
20 * used as clocksource. The overall allocation looks like:
21 * - timer 0 - NR_CPUs for per cpu timer
22 * - one timer for clocksource
23 * - one timer for watchdog driver.
24 * It is also worth notice that APB timer does not support true one-shot mode,
25 * free-running mode will be used here to emulate one-shot mode.
26 * APB timer can also be used as broadcast timer along with per cpu local APIC
27 * timer, but by default APB timer has higher rating than local APIC timers.
28 */
29
30 #include <linux/delay.h>
31 #include <linux/dw_apb_timer.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/slab.h>
35 #include <linux/pm.h>
36 #include <linux/sfi.h>
37 #include <linux/interrupt.h>
38 #include <linux/cpu.h>
39 #include <linux/irq.h>
40
41 #include <asm/fixmap.h>
42 #include <asm/apb_timer.h>
43 #include <asm/mrst.h>
44 #include <asm/time.h>
45
46 #define APBT_CLOCKEVENT_RATING 110
47 #define APBT_CLOCKSOURCE_RATING 250
48
49 #define APBT_CLOCKEVENT0_NUM (0)
50 #define APBT_CLOCKSOURCE_NUM (2)
51
52 static phys_addr_t apbt_address;
53 static int apb_timer_block_enabled;
54 static void __iomem *apbt_virt_address;
55
56 /*
57 * Common DW APB timer info
58 */
59 static unsigned long apbt_freq;
60
61 struct apbt_dev {
62 struct dw_apb_clock_event_device *timer;
63 unsigned int num;
64 int cpu;
65 unsigned int irq;
66 char name[10];
67 };
68
69 static struct dw_apb_clocksource *clocksource_apbt;
70
adev_virt_addr(struct apbt_dev * adev)71 static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
72 {
73 return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
74 }
75
76 static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
77
78 #ifdef CONFIG_SMP
79 static unsigned int apbt_num_timers_used;
80 #endif
81
apbt_set_mapping(void)82 static inline void apbt_set_mapping(void)
83 {
84 struct sfi_timer_table_entry *mtmr;
85 int phy_cs_timer_id = 0;
86
87 if (apbt_virt_address) {
88 pr_debug("APBT base already mapped\n");
89 return;
90 }
91 mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
92 if (mtmr == NULL) {
93 printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
94 APBT_CLOCKEVENT0_NUM);
95 return;
96 }
97 apbt_address = (phys_addr_t)mtmr->phys_addr;
98 if (!apbt_address) {
99 printk(KERN_WARNING "No timer base from SFI, use default\n");
100 apbt_address = APBT_DEFAULT_BASE;
101 }
102 apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
103 if (!apbt_virt_address) {
104 pr_debug("Failed mapping APBT phy address at %lu\n",\
105 (unsigned long)apbt_address);
106 goto panic_noapbt;
107 }
108 apbt_freq = mtmr->freq_hz;
109 sfi_free_mtmr(mtmr);
110
111 /* Now figure out the physical timer id for clocksource device */
112 mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
113 if (mtmr == NULL)
114 goto panic_noapbt;
115
116 /* Now figure out the physical timer id */
117 pr_debug("Use timer %d for clocksource\n",
118 (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
119 phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
120 APBTMRS_REG_SIZE;
121
122 clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
123 "apbt0", apbt_virt_address + phy_cs_timer_id *
124 APBTMRS_REG_SIZE, apbt_freq);
125 return;
126
127 panic_noapbt:
128 panic("Failed to setup APB system timer\n");
129
130 }
131
apbt_clear_mapping(void)132 static inline void apbt_clear_mapping(void)
133 {
134 iounmap(apbt_virt_address);
135 apbt_virt_address = NULL;
136 }
137
138 /*
139 * APBT timer interrupt enable / disable
140 */
is_apbt_capable(void)141 static inline int is_apbt_capable(void)
142 {
143 return apbt_virt_address ? 1 : 0;
144 }
145
apbt_clockevent_register(void)146 static int __init apbt_clockevent_register(void)
147 {
148 struct sfi_timer_table_entry *mtmr;
149 struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev);
150
151 mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
152 if (mtmr == NULL) {
153 printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
154 APBT_CLOCKEVENT0_NUM);
155 return -ENODEV;
156 }
157
158 adev->num = smp_processor_id();
159 adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
160 mrst_timer_options == MRST_TIMER_LAPIC_APBT ?
161 APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
162 adev_virt_addr(adev), 0, apbt_freq);
163 /* Firmware does EOI handling for us. */
164 adev->timer->eoi = NULL;
165
166 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
167 global_clock_event = &adev->timer->ced;
168 printk(KERN_DEBUG "%s clockevent registered as global\n",
169 global_clock_event->name);
170 }
171
172 dw_apb_clockevent_register(adev->timer);
173
174 sfi_free_mtmr(mtmr);
175 return 0;
176 }
177
178 #ifdef CONFIG_SMP
179
apbt_setup_irq(struct apbt_dev * adev)180 static void apbt_setup_irq(struct apbt_dev *adev)
181 {
182 /* timer0 irq has been setup early */
183 if (adev->irq == 0)
184 return;
185
186 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
187 irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
188 /* APB timer irqs are set up as mp_irqs, timer is edge type */
189 __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
190 }
191
192 /* Should be called with per cpu */
apbt_setup_secondary_clock(void)193 void apbt_setup_secondary_clock(void)
194 {
195 struct apbt_dev *adev;
196 int cpu;
197
198 /* Don't register boot CPU clockevent */
199 cpu = smp_processor_id();
200 if (!cpu)
201 return;
202
203 adev = &__get_cpu_var(cpu_apbt_dev);
204 if (!adev->timer) {
205 adev->timer = dw_apb_clockevent_init(cpu, adev->name,
206 APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
207 adev->irq, apbt_freq);
208 adev->timer->eoi = NULL;
209 } else {
210 dw_apb_clockevent_resume(adev->timer);
211 }
212
213 printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
214 cpu, adev->name, adev->cpu);
215
216 apbt_setup_irq(adev);
217 dw_apb_clockevent_register(adev->timer);
218
219 return;
220 }
221
222 /*
223 * this notify handler process CPU hotplug events. in case of S0i3, nonboot
224 * cpus are disabled/enabled frequently, for performance reasons, we keep the
225 * per cpu timer irq registered so that we do need to do free_irq/request_irq.
226 *
227 * TODO: it might be more reliable to directly disable percpu clockevent device
228 * without the notifier chain. currently, cpu 0 may get interrupts from other
229 * cpu timers during the offline process due to the ordering of notification.
230 * the extra interrupt is harmless.
231 */
apbt_cpuhp_notify(struct notifier_block * n,unsigned long action,void * hcpu)232 static int apbt_cpuhp_notify(struct notifier_block *n,
233 unsigned long action, void *hcpu)
234 {
235 unsigned long cpu = (unsigned long)hcpu;
236 struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
237
238 switch (action & 0xf) {
239 case CPU_DEAD:
240 dw_apb_clockevent_pause(adev->timer);
241 if (system_state == SYSTEM_RUNNING) {
242 pr_debug("skipping APBT CPU %lu offline\n", cpu);
243 } else if (adev) {
244 pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
245 dw_apb_clockevent_stop(adev->timer);
246 }
247 break;
248 default:
249 pr_debug("APBT notified %lu, no action\n", action);
250 }
251 return NOTIFY_OK;
252 }
253
apbt_late_init(void)254 static __init int apbt_late_init(void)
255 {
256 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
257 !apb_timer_block_enabled)
258 return 0;
259 /* This notifier should be called after workqueue is ready */
260 hotcpu_notifier(apbt_cpuhp_notify, -20);
261 return 0;
262 }
263 fs_initcall(apbt_late_init);
264 #else
265
apbt_setup_secondary_clock(void)266 void apbt_setup_secondary_clock(void) {}
267
268 #endif /* CONFIG_SMP */
269
apbt_clocksource_register(void)270 static int apbt_clocksource_register(void)
271 {
272 u64 start, now;
273 cycle_t t1;
274
275 /* Start the counter, use timer 2 as source, timer 0/1 for event */
276 dw_apb_clocksource_start(clocksource_apbt);
277
278 /* Verify whether apbt counter works */
279 t1 = dw_apb_clocksource_read(clocksource_apbt);
280 rdtscll(start);
281
282 /*
283 * We don't know the TSC frequency yet, but waiting for
284 * 200000 TSC cycles is safe:
285 * 4 GHz == 50us
286 * 1 GHz == 200us
287 */
288 do {
289 rep_nop();
290 rdtscll(now);
291 } while ((now - start) < 200000UL);
292
293 /* APBT is the only always on clocksource, it has to work! */
294 if (t1 == dw_apb_clocksource_read(clocksource_apbt))
295 panic("APBT counter not counting. APBT disabled\n");
296
297 dw_apb_clocksource_register(clocksource_apbt);
298
299 return 0;
300 }
301
302 /*
303 * Early setup the APBT timer, only use timer 0 for booting then switch to
304 * per CPU timer if possible.
305 * returns 1 if per cpu apbt is setup
306 * returns 0 if no per cpu apbt is chosen
307 * panic if set up failed, this is the only platform timer on Moorestown.
308 */
apbt_time_init(void)309 void __init apbt_time_init(void)
310 {
311 #ifdef CONFIG_SMP
312 int i;
313 struct sfi_timer_table_entry *p_mtmr;
314 unsigned int percpu_timer;
315 struct apbt_dev *adev;
316 #endif
317
318 if (apb_timer_block_enabled)
319 return;
320 apbt_set_mapping();
321 if (!apbt_virt_address)
322 goto out_noapbt;
323 /*
324 * Read the frequency and check for a sane value, for ESL model
325 * we extend the possible clock range to allow time scaling.
326 */
327
328 if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
329 pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
330 goto out_noapbt;
331 }
332 if (apbt_clocksource_register()) {
333 pr_debug("APBT has failed to register clocksource\n");
334 goto out_noapbt;
335 }
336 if (!apbt_clockevent_register())
337 apb_timer_block_enabled = 1;
338 else {
339 pr_debug("APBT has failed to register clockevent\n");
340 goto out_noapbt;
341 }
342 #ifdef CONFIG_SMP
343 /* kernel cmdline disable apb timer, so we will use lapic timers */
344 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
345 printk(KERN_INFO "apbt: disabled per cpu timer\n");
346 return;
347 }
348 pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
349 if (num_possible_cpus() <= sfi_mtimer_num) {
350 percpu_timer = 1;
351 apbt_num_timers_used = num_possible_cpus();
352 } else {
353 percpu_timer = 0;
354 apbt_num_timers_used = 1;
355 }
356 pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
357
358 /* here we set up per CPU timer data structure */
359 for (i = 0; i < apbt_num_timers_used; i++) {
360 adev = &per_cpu(cpu_apbt_dev, i);
361 adev->num = i;
362 adev->cpu = i;
363 p_mtmr = sfi_get_mtmr(i);
364 if (p_mtmr)
365 adev->irq = p_mtmr->irq;
366 else
367 printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
368 snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
369 }
370 #endif
371
372 return;
373
374 out_noapbt:
375 apbt_clear_mapping();
376 apb_timer_block_enabled = 0;
377 panic("failed to enable APB timer\n");
378 }
379
380 /* called before apb_timer_enable, use early map */
apbt_quick_calibrate(void)381 unsigned long apbt_quick_calibrate(void)
382 {
383 int i, scale;
384 u64 old, new;
385 cycle_t t1, t2;
386 unsigned long khz = 0;
387 u32 loop, shift;
388
389 apbt_set_mapping();
390 dw_apb_clocksource_start(clocksource_apbt);
391
392 /* check if the timer can count down, otherwise return */
393 old = dw_apb_clocksource_read(clocksource_apbt);
394 i = 10000;
395 while (--i) {
396 if (old != dw_apb_clocksource_read(clocksource_apbt))
397 break;
398 }
399 if (!i)
400 goto failed;
401
402 /* count 16 ms */
403 loop = (apbt_freq / 1000) << 4;
404
405 /* restart the timer to ensure it won't get to 0 in the calibration */
406 dw_apb_clocksource_start(clocksource_apbt);
407
408 old = dw_apb_clocksource_read(clocksource_apbt);
409 old += loop;
410
411 t1 = __native_read_tsc();
412
413 do {
414 new = dw_apb_clocksource_read(clocksource_apbt);
415 } while (new < old);
416
417 t2 = __native_read_tsc();
418
419 shift = 5;
420 if (unlikely(loop >> shift == 0)) {
421 printk(KERN_INFO
422 "APBT TSC calibration failed, not enough resolution\n");
423 return 0;
424 }
425 scale = (int)div_u64((t2 - t1), loop >> shift);
426 khz = (scale * (apbt_freq / 1000)) >> shift;
427 printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
428 return khz;
429 failed:
430 return 0;
431 }
432