1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_BAU_H
12 #define _ASM_X86_UV_UV_BAU_H
13
14 #include <linux/bitmap.h>
15 #define BITSPERBYTE 8
16
17 /*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use one set for sending BAU messages from each of the
30 * cpu's on the uvhub.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36 #define MAX_CPUS_PER_UVHUB 64
37 #define MAX_CPUS_PER_SOCKET 32
38 #define ADP_SZ 64 /* hardware-provided max. */
39 #define UV_CPUS_PER_AS 32 /* hardware-provided max. */
40 #define ITEMS_PER_DESC 8
41 /* the 'throttle' to prevent the hardware stay-busy bug */
42 #define MAX_BAU_CONCURRENT 3
43 #define UV_ACT_STATUS_MASK 0x3
44 #define UV_ACT_STATUS_SIZE 2
45 #define UV_DISTRIBUTION_SIZE 256
46 #define UV_SW_ACK_NPENDING 8
47 #define UV1_NET_ENDPOINT_INTD 0x38
48 #define UV2_NET_ENDPOINT_INTD 0x28
49 #define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51 #define UV_DESC_PSHIFT 49
52 #define UV_PAYLOADQ_PNODE_SHIFT 49
53 #define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54 #define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55 #define UV_BAU_TUNABLES_DIR "sgi_uv"
56 #define UV_BAU_TUNABLES_FILE "bau_tunables"
57 #define WHITESPACE " \t\n"
58 #define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59 #define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60 #define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
62
63 /* [19:16] SOFT_ACK timeout period 19: 1 is urgency 7 17:16 1 is multiplier */
64 /*
65 * UV2: Bit 19 selects between
66 * (0): 10 microsecond timebase and
67 * (1): 80 microseconds
68 * we're using 560us, similar to UV1: 65 units of 10us
69 */
70 #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71 #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73 #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77 #define BAU_MISC_CONTROL_MULT_MASK 3
78
79 #define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80 /* [30:28] URGENCY_7 an index into a table of times */
81 #define BAU_URGENCY_7_SHIFT 28
82 #define BAU_URGENCY_7_MASK 7
83
84 #define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
86 #define BAU_TRANS_SHIFT 40
87 #define BAU_TRANS_MASK 0x3f
88
89 /*
90 * shorten some awkward names
91 */
92 #define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93 #define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94 #define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95 #define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96 #define write_gmmr uv_write_global_mmr64
97 #define write_lmmr uv_write_local_mmr
98 #define read_lmmr uv_read_local_mmr
99 #define read_gmmr uv_read_global_mmr64
100
101 /*
102 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
103 */
104 #define DS_IDLE 0
105 #define DS_ACTIVE 1
106 #define DS_DESTINATION_TIMEOUT 2
107 #define DS_SOURCE_TIMEOUT 3
108 /*
109 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
110 * values 1 and 3 will not occur
111 * Decoded meaning ERROR BUSY AUX ERR
112 * ------------------------------- ---- ----- -------
113 * IDLE 0 0 0
114 * BUSY (active) 0 1 0
115 * SW Ack Timeout (destination) 1 0 0
116 * SW Ack INTD rejected (strong NACK) 1 0 1
117 * Source Side Time Out Detected 1 1 0
118 * Destination Side PUT Failed 1 1 1
119 */
120 #define UV2H_DESC_IDLE 0
121 #define UV2H_DESC_BUSY 2
122 #define UV2H_DESC_DEST_TIMEOUT 4
123 #define UV2H_DESC_DEST_STRONG_NACK 5
124 #define UV2H_DESC_SOURCE_TIMEOUT 6
125 #define UV2H_DESC_DEST_PUT_ERR 7
126
127 /*
128 * delay for 'plugged' timeout retries, in microseconds
129 */
130 #define PLUGGED_DELAY 10
131
132 /*
133 * threshholds at which to use IPI to free resources
134 */
135 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
136 #define PLUGSB4RESET 100
137 /* after this many consecutive timeouts, use IPI to release resources */
138 #define TIMEOUTSB4RESET 1
139 /* at this number uses of IPI to release resources, giveup the request */
140 #define IPI_RESET_LIMIT 1
141 /* after this # consecutive successes, bump up the throttle if it was lowered */
142 #define COMPLETE_THRESHOLD 5
143
144 #define UV_LB_SUBNODEID 0x10
145
146 /* these two are the same for UV1 and UV2: */
147 #define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
148 #define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
149 /* 4 bits of software ack period */
150 #define UV2_ACK_MASK 0x7UL
151 #define UV2_ACK_UNITS_SHFT 3
152 #define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
153 #define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
154
155 /*
156 * number of entries in the destination side payload queue
157 */
158 #define DEST_Q_SIZE 20
159 /*
160 * number of destination side software ack resources
161 */
162 #define DEST_NUM_RESOURCES 8
163 /*
164 * completion statuses for sending a TLB flush message
165 */
166 #define FLUSH_RETRY_PLUGGED 1
167 #define FLUSH_RETRY_TIMEOUT 2
168 #define FLUSH_GIVEUP 3
169 #define FLUSH_COMPLETE 4
170 #define FLUSH_RETRY_BUSYBUG 5
171
172 /*
173 * tuning the action when the numalink network is extremely delayed
174 */
175 #define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in
176 microseconds */
177 #define CONGESTED_REPS 10 /* long delays averaged over
178 this many broadcasts */
179 #define CONGESTED_PERIOD 30 /* time for the bau to be
180 disabled, in seconds */
181 /* see msg_type: */
182 #define MSG_NOOP 0
183 #define MSG_REGULAR 1
184 #define MSG_RETRY 2
185
186 /*
187 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
188 * If the 'multilevel' flag in the header portion of the descriptor
189 * has been set to 0, then endpoint multi-unicast mode is selected.
190 * The distribution specification (32 bytes) is interpreted as a 256-bit
191 * distribution vector. Adjacent bits correspond to consecutive even numbered
192 * nodeIDs. The result of adding the index of a given bit to the 15-bit
193 * 'base_dest_nasid' field of the header corresponds to the
194 * destination nodeID associated with that specified bit.
195 */
196 struct pnmask {
197 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
198 };
199
200 /*
201 * mask of cpu's on a uvhub
202 * (during initialization we need to check that unsigned long has
203 * enough bits for max. cpu's per uvhub)
204 */
205 struct bau_local_cpumask {
206 unsigned long bits;
207 };
208
209 /*
210 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
211 * only 12 bytes (96 bits) of the payload area are usable.
212 * An additional 3 bytes (bits 27:4) of the header address are carried
213 * to the next bytes of the destination payload queue.
214 * And an additional 2 bytes of the header Suppl_A field are also
215 * carried to the destination payload queue.
216 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
217 * of the destination payload queue, which is written by the hardware
218 * with the s/w ack resource bit vector.
219 * [ effective message contents (16 bytes (128 bits) maximum), not counting
220 * the s/w ack bit vector ]
221 */
222
223 /*
224 * The payload is software-defined for INTD transactions
225 */
226 struct bau_msg_payload {
227 unsigned long address; /* signifies a page or all
228 TLB's of the cpu */
229 /* 64 bits */
230 unsigned short sending_cpu; /* filled in by sender */
231 /* 16 bits */
232 unsigned short acknowledge_count; /* filled in by destination */
233 /* 16 bits */
234 unsigned int reserved1:32; /* not usable */
235 };
236
237
238 /*
239 * UV1 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
240 * see table 4.2.3.0.1 in broacast_assist spec.
241 */
242 struct uv1_bau_msg_header {
243 unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */
244 /* bits 5:0 */
245 unsigned int base_dest_nasid:15; /* nasid of the first bit */
246 /* bits 20:6 */ /* in uvhub map */
247 unsigned int command:8; /* message type */
248 /* bits 28:21 */
249 /* 0x38: SN3net EndPoint Message */
250 unsigned int rsvd_1:3; /* must be zero */
251 /* bits 31:29 */
252 /* int will align on 32 bits */
253 unsigned int rsvd_2:9; /* must be zero */
254 /* bits 40:32 */
255 /* Suppl_A is 56-41 */
256 unsigned int sequence:16; /* message sequence number */
257 /* bits 56:41 */ /* becomes bytes 16-17 of msg */
258 /* Address field (96:57) is
259 never used as an address
260 (these are address bits
261 42:3) */
262
263 unsigned int rsvd_3:1; /* must be zero */
264 /* bit 57 */
265 /* address bits 27:4 are payload */
266 /* these next 24 (58-81) bits become bytes 12-14 of msg */
267 /* bits 65:58 land in byte 12 */
268 unsigned int replied_to:1; /* sent as 0 by the source to
269 byte 12 */
270 /* bit 58 */
271 unsigned int msg_type:3; /* software type of the
272 message */
273 /* bits 61:59 */
274 unsigned int canceled:1; /* message canceled, resource
275 is to be freed*/
276 /* bit 62 */
277 unsigned int payload_1a:1; /* not currently used */
278 /* bit 63 */
279 unsigned int payload_1b:2; /* not currently used */
280 /* bits 65:64 */
281
282 /* bits 73:66 land in byte 13 */
283 unsigned int payload_1ca:6; /* not currently used */
284 /* bits 71:66 */
285 unsigned int payload_1c:2; /* not currently used */
286 /* bits 73:72 */
287
288 /* bits 81:74 land in byte 14 */
289 unsigned int payload_1d:6; /* not currently used */
290 /* bits 79:74 */
291 unsigned int payload_1e:2; /* not currently used */
292 /* bits 81:80 */
293
294 unsigned int rsvd_4:7; /* must be zero */
295 /* bits 88:82 */
296 unsigned int swack_flag:1; /* software acknowledge flag */
297 /* bit 89 */
298 /* INTD trasactions at
299 destination are to wait for
300 software acknowledge */
301 unsigned int rsvd_5:6; /* must be zero */
302 /* bits 95:90 */
303 unsigned int rsvd_6:5; /* must be zero */
304 /* bits 100:96 */
305 unsigned int int_both:1; /* if 1, interrupt both sockets
306 on the uvhub */
307 /* bit 101*/
308 unsigned int fairness:3; /* usually zero */
309 /* bits 104:102 */
310 unsigned int multilevel:1; /* multi-level multicast
311 format */
312 /* bit 105 */
313 /* 0 for TLB: endpoint multi-unicast messages */
314 unsigned int chaining:1; /* next descriptor is part of
315 this activation*/
316 /* bit 106 */
317 unsigned int rsvd_7:21; /* must be zero */
318 /* bits 127:107 */
319 };
320
321 /*
322 * UV2 Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
323 * see figure 9-2 of harp_sys.pdf
324 */
325 struct uv2_bau_msg_header {
326 unsigned int base_dest_nasid:15; /* nasid of the first bit */
327 /* bits 14:0 */ /* in uvhub map */
328 unsigned int dest_subnodeid:5; /* must be 0x10, for the LB */
329 /* bits 19:15 */
330 unsigned int rsvd_1:1; /* must be zero */
331 /* bit 20 */
332 /* Address bits 59:21 */
333 /* bits 25:2 of address (44:21) are payload */
334 /* these next 24 bits become bytes 12-14 of msg */
335 /* bits 28:21 land in byte 12 */
336 unsigned int replied_to:1; /* sent as 0 by the source to
337 byte 12 */
338 /* bit 21 */
339 unsigned int msg_type:3; /* software type of the
340 message */
341 /* bits 24:22 */
342 unsigned int canceled:1; /* message canceled, resource
343 is to be freed*/
344 /* bit 25 */
345 unsigned int payload_1:3; /* not currently used */
346 /* bits 28:26 */
347
348 /* bits 36:29 land in byte 13 */
349 unsigned int payload_2a:3; /* not currently used */
350 unsigned int payload_2b:5; /* not currently used */
351 /* bits 36:29 */
352
353 /* bits 44:37 land in byte 14 */
354 unsigned int payload_3:8; /* not currently used */
355 /* bits 44:37 */
356
357 unsigned int rsvd_2:7; /* reserved */
358 /* bits 51:45 */
359 unsigned int swack_flag:1; /* software acknowledge flag */
360 /* bit 52 */
361 unsigned int rsvd_3a:3; /* must be zero */
362 unsigned int rsvd_3b:8; /* must be zero */
363 unsigned int rsvd_3c:8; /* must be zero */
364 unsigned int rsvd_3d:3; /* must be zero */
365 /* bits 74:53 */
366 unsigned int fairness:3; /* usually zero */
367 /* bits 77:75 */
368
369 unsigned int sequence:16; /* message sequence number */
370 /* bits 93:78 Suppl_A */
371 unsigned int chaining:1; /* next descriptor is part of
372 this activation*/
373 /* bit 94 */
374 unsigned int multilevel:1; /* multi-level multicast
375 format */
376 /* bit 95 */
377 unsigned int rsvd_4:24; /* ordered / source node /
378 source subnode / aging
379 must be zero */
380 /* bits 119:96 */
381 unsigned int command:8; /* message type */
382 /* bits 127:120 */
383 };
384
385 /*
386 * The activation descriptor:
387 * The format of the message to send, plus all accompanying control
388 * Should be 64 bytes
389 */
390 struct bau_desc {
391 struct pnmask distribution;
392 /*
393 * message template, consisting of header and payload:
394 */
395 union bau_msg_header {
396 struct uv1_bau_msg_header uv1_hdr;
397 struct uv2_bau_msg_header uv2_hdr;
398 } header;
399
400 struct bau_msg_payload payload;
401 };
402 /* UV1:
403 * -payload-- ---------header------
404 * bytes 0-11 bits 41-56 bits 58-81
405 * A B (2) C (3)
406 *
407 * A/B/C are moved to:
408 * A C B
409 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
410 * ------------payload queue-----------
411 */
412 /* UV2:
413 * -payload-- ---------header------
414 * bytes 0-11 bits 70-78 bits 21-44
415 * A B (2) C (3)
416 *
417 * A/B/C are moved to:
418 * A C B
419 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
420 * ------------payload queue-----------
421 */
422
423 /*
424 * The payload queue on the destination side is an array of these.
425 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
426 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
427 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
428 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
429 * swack_vec and payload_2)
430 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
431 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
432 * operation."
433 */
434 struct bau_pq_entry {
435 unsigned long address; /* signifies a page or all TLB's
436 of the cpu */
437 /* 64 bits, bytes 0-7 */
438 unsigned short sending_cpu; /* cpu that sent the message */
439 /* 16 bits, bytes 8-9 */
440 unsigned short acknowledge_count; /* filled in by destination */
441 /* 16 bits, bytes 10-11 */
442 /* these next 3 bytes come from bits 58-81 of the message header */
443 unsigned short replied_to:1; /* sent as 0 by the source */
444 unsigned short msg_type:3; /* software message type */
445 unsigned short canceled:1; /* sent as 0 by the source */
446 unsigned short unused1:3; /* not currently using */
447 /* byte 12 */
448 unsigned char unused2a; /* not currently using */
449 /* byte 13 */
450 unsigned char unused2; /* not currently using */
451 /* byte 14 */
452 unsigned char swack_vec; /* filled in by the hardware */
453 /* byte 15 (bits 127:120) */
454 unsigned short sequence; /* message sequence number */
455 /* bytes 16-17 */
456 unsigned char unused4[2]; /* not currently using bytes 18-19 */
457 /* bytes 18-19 */
458 int number_of_cpus; /* filled in at destination */
459 /* 32 bits, bytes 20-23 (aligned) */
460 unsigned char unused5[8]; /* not using */
461 /* bytes 24-31 */
462 };
463
464 struct msg_desc {
465 struct bau_pq_entry *msg;
466 int msg_slot;
467 struct bau_pq_entry *queue_first;
468 struct bau_pq_entry *queue_last;
469 };
470
471 struct reset_args {
472 int sender;
473 };
474
475 /*
476 * This structure is allocated per_cpu for UV TLB shootdown statistics.
477 */
478 struct ptc_stats {
479 /* sender statistics */
480 unsigned long s_giveup; /* number of fall backs to
481 IPI-style flushes */
482 unsigned long s_requestor; /* number of shootdown
483 requests */
484 unsigned long s_stimeout; /* source side timeouts */
485 unsigned long s_dtimeout; /* destination side timeouts */
486 unsigned long s_strongnacks; /* number of strong nack's */
487 unsigned long s_time; /* time spent in sending side */
488 unsigned long s_retriesok; /* successful retries */
489 unsigned long s_ntargcpu; /* total number of cpu's
490 targeted */
491 unsigned long s_ntargself; /* times the sending cpu was
492 targeted */
493 unsigned long s_ntarglocals; /* targets of cpus on the local
494 blade */
495 unsigned long s_ntargremotes; /* targets of cpus on remote
496 blades */
497 unsigned long s_ntarglocaluvhub; /* targets of the local hub */
498 unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
499 unsigned long s_ntarguvhub; /* total number of uvhubs
500 targeted */
501 unsigned long s_ntarguvhub16; /* number of times target
502 hubs >= 16*/
503 unsigned long s_ntarguvhub8; /* number of times target
504 hubs >= 8 */
505 unsigned long s_ntarguvhub4; /* number of times target
506 hubs >= 4 */
507 unsigned long s_ntarguvhub2; /* number of times target
508 hubs >= 2 */
509 unsigned long s_ntarguvhub1; /* number of times target
510 hubs == 1 */
511 unsigned long s_resets_plug; /* ipi-style resets from plug
512 state */
513 unsigned long s_resets_timeout; /* ipi-style resets from
514 timeouts */
515 unsigned long s_busy; /* status stayed busy past
516 s/w timer */
517 unsigned long s_throttles; /* waits in throttle */
518 unsigned long s_retry_messages; /* retry broadcasts */
519 unsigned long s_bau_reenabled; /* for bau enable/disable */
520 unsigned long s_bau_disabled; /* for bau enable/disable */
521 unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */
522 unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */
523 unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */
524 /* destination statistics */
525 unsigned long d_alltlb; /* times all tlb's on this
526 cpu were flushed */
527 unsigned long d_onetlb; /* times just one tlb on this
528 cpu was flushed */
529 unsigned long d_multmsg; /* interrupts with multiple
530 messages */
531 unsigned long d_nomsg; /* interrupts with no message */
532 unsigned long d_time; /* time spent on destination
533 side */
534 unsigned long d_requestee; /* number of messages
535 processed */
536 unsigned long d_retries; /* number of retry messages
537 processed */
538 unsigned long d_canceled; /* number of messages canceled
539 by retries */
540 unsigned long d_nocanceled; /* retries that found nothing
541 to cancel */
542 unsigned long d_resets; /* number of ipi-style requests
543 processed */
544 unsigned long d_rcanceled; /* number of messages canceled
545 by resets */
546 };
547
548 struct tunables {
549 int *tunp;
550 int deflt;
551 };
552
553 struct hub_and_pnode {
554 short uvhub;
555 short pnode;
556 };
557
558 struct socket_desc {
559 short num_cpus;
560 short cpu_number[MAX_CPUS_PER_SOCKET];
561 };
562
563 struct uvhub_desc {
564 unsigned short socket_mask;
565 short num_cpus;
566 short uvhub;
567 short pnode;
568 struct socket_desc socket[2];
569 };
570
571 /*
572 * one per-cpu; to locate the software tables
573 */
574 struct bau_control {
575 struct bau_desc *descriptor_base;
576 struct bau_pq_entry *queue_first;
577 struct bau_pq_entry *queue_last;
578 struct bau_pq_entry *bau_msg_head;
579 struct bau_control *uvhub_master;
580 struct bau_control *socket_master;
581 struct ptc_stats *statp;
582 cpumask_t *cpumask;
583 unsigned long timeout_interval;
584 unsigned long set_bau_on_time;
585 atomic_t active_descriptor_count;
586 int plugged_tries;
587 int timeout_tries;
588 int ipi_attempts;
589 int conseccompletes;
590 int baudisabled;
591 int set_bau_off;
592 short cpu;
593 short osnode;
594 short uvhub_cpu;
595 short uvhub;
596 short uvhub_version;
597 short cpus_in_socket;
598 short cpus_in_uvhub;
599 short partition_base_pnode;
600 short using_desc; /* an index, like uvhub_cpu */
601 unsigned int inuse_map;
602 unsigned short message_number;
603 unsigned short uvhub_quiesce;
604 short socket_acknowledge_count[DEST_Q_SIZE];
605 cycles_t send_message;
606 spinlock_t uvhub_lock;
607 spinlock_t queue_lock;
608 /* tunables */
609 int max_concurr;
610 int max_concurr_const;
611 int plugged_delay;
612 int plugsb4reset;
613 int timeoutsb4reset;
614 int ipi_reset_limit;
615 int complete_threshold;
616 int cong_response_us;
617 int cong_reps;
618 int cong_period;
619 unsigned long clocks_per_100_usec;
620 cycles_t period_time;
621 long period_requests;
622 struct hub_and_pnode *thp;
623 };
624
read_mmr_uv2_status(void)625 static inline unsigned long read_mmr_uv2_status(void)
626 {
627 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
628 }
629
write_mmr_data_broadcast(int pnode,unsigned long mmr_image)630 static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
631 {
632 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
633 }
634
write_mmr_descriptor_base(int pnode,unsigned long mmr_image)635 static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
636 {
637 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
638 }
639
write_mmr_activation(unsigned long index)640 static inline void write_mmr_activation(unsigned long index)
641 {
642 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
643 }
644
write_gmmr_activation(int pnode,unsigned long mmr_image)645 static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
646 {
647 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
648 }
649
write_mmr_payload_first(int pnode,unsigned long mmr_image)650 static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
651 {
652 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
653 }
654
write_mmr_payload_tail(int pnode,unsigned long mmr_image)655 static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
656 {
657 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
658 }
659
write_mmr_payload_last(int pnode,unsigned long mmr_image)660 static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
661 {
662 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
663 }
664
write_mmr_misc_control(int pnode,unsigned long mmr_image)665 static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
666 {
667 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
668 }
669
read_mmr_misc_control(int pnode)670 static inline unsigned long read_mmr_misc_control(int pnode)
671 {
672 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
673 }
674
write_mmr_sw_ack(unsigned long mr)675 static inline void write_mmr_sw_ack(unsigned long mr)
676 {
677 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
678 }
679
write_gmmr_sw_ack(int pnode,unsigned long mr)680 static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
681 {
682 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
683 }
684
read_mmr_sw_ack(void)685 static inline unsigned long read_mmr_sw_ack(void)
686 {
687 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
688 }
689
read_gmmr_sw_ack(int pnode)690 static inline unsigned long read_gmmr_sw_ack(int pnode)
691 {
692 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
693 }
694
write_mmr_data_config(int pnode,unsigned long mr)695 static inline void write_mmr_data_config(int pnode, unsigned long mr)
696 {
697 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
698 }
699
bau_uvhub_isset(int uvhub,struct pnmask * dstp)700 static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
701 {
702 return constant_test_bit(uvhub, &dstp->bits[0]);
703 }
bau_uvhub_set(int pnode,struct pnmask * dstp)704 static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
705 {
706 __set_bit(pnode, &dstp->bits[0]);
707 }
bau_uvhubs_clear(struct pnmask * dstp,int nbits)708 static inline void bau_uvhubs_clear(struct pnmask *dstp,
709 int nbits)
710 {
711 bitmap_zero(&dstp->bits[0], nbits);
712 }
bau_uvhub_weight(struct pnmask * dstp)713 static inline int bau_uvhub_weight(struct pnmask *dstp)
714 {
715 return bitmap_weight((unsigned long *)&dstp->bits[0],
716 UV_DISTRIBUTION_SIZE);
717 }
718
bau_cpubits_clear(struct bau_local_cpumask * dstp,int nbits)719 static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
720 {
721 bitmap_zero(&dstp->bits, nbits);
722 }
723
724 extern void uv_bau_message_intr1(void);
725 extern void uv_bau_timeout_intr1(void);
726
727 struct atomic_short {
728 short counter;
729 };
730
731 /*
732 * atomic_read_short - read a short atomic variable
733 * @v: pointer of type atomic_short
734 *
735 * Atomically reads the value of @v.
736 */
atomic_read_short(const struct atomic_short * v)737 static inline int atomic_read_short(const struct atomic_short *v)
738 {
739 return v->counter;
740 }
741
742 /*
743 * atom_asr - add and return a short int
744 * @i: short value to add
745 * @v: pointer of type atomic_short
746 *
747 * Atomically adds @i to @v and returns @i + @v
748 */
atom_asr(short i,struct atomic_short * v)749 static inline int atom_asr(short i, struct atomic_short *v)
750 {
751 return i + xadd(&v->counter, i);
752 }
753
754 /*
755 * conditionally add 1 to *v, unless *v is >= u
756 * return 0 if we cannot add 1 to *v because it is >= u
757 * return 1 if we can add 1 to *v because it is < u
758 * the add is atomic
759 *
760 * This is close to atomic_add_unless(), but this allows the 'u' value
761 * to be lowered below the current 'v'. atomic_add_unless can only stop
762 * on equal.
763 */
atomic_inc_unless_ge(spinlock_t * lock,atomic_t * v,int u)764 static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
765 {
766 spin_lock(lock);
767 if (atomic_read(v) >= u) {
768 spin_unlock(lock);
769 return 0;
770 }
771 atomic_inc(v);
772 spin_unlock(lock);
773 return 1;
774 }
775
776 #endif /* _ASM_X86_UV_UV_BAU_H */
777