1/* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 * 14 * Linux interrupt vectors. 15 */ 16 17#include <linux/linkage.h> 18#include <linux/errno.h> 19#include <linux/init.h> 20#include <linux/unistd.h> 21#include <asm/ptrace.h> 22#include <asm/thread_info.h> 23#include <asm/irqflags.h> 24#include <asm/atomic_32.h> 25#include <asm/asm-offsets.h> 26#include <hv/hypervisor.h> 27#include <arch/abi.h> 28#include <arch/interrupts.h> 29#include <arch/spr_def.h> 30 31#ifdef CONFIG_PREEMPT 32# error "No support for kernel preemption currently" 33#endif 34 35#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg) 36 37#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR) 38 39#if !CHIP_HAS_WH64() 40 /* By making this an empty macro, we can use wh64 in the code. */ 41 .macro wh64 reg 42 .endm 43#endif 44 45 .macro push_reg reg, ptr=sp, delta=-4 46 { 47 sw \ptr, \reg 48 addli \ptr, \ptr, \delta 49 } 50 .endm 51 52 .macro pop_reg reg, ptr=sp, delta=4 53 { 54 lw \reg, \ptr 55 addli \ptr, \ptr, \delta 56 } 57 .endm 58 59 .macro pop_reg_zero reg, zreg, ptr=sp, delta=4 60 { 61 move \zreg, zero 62 lw \reg, \ptr 63 addi \ptr, \ptr, \delta 64 } 65 .endm 66 67 .macro push_extra_callee_saves reg 68 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51)) 69 push_reg r51, \reg 70 push_reg r50, \reg 71 push_reg r49, \reg 72 push_reg r48, \reg 73 push_reg r47, \reg 74 push_reg r46, \reg 75 push_reg r45, \reg 76 push_reg r44, \reg 77 push_reg r43, \reg 78 push_reg r42, \reg 79 push_reg r41, \reg 80 push_reg r40, \reg 81 push_reg r39, \reg 82 push_reg r38, \reg 83 push_reg r37, \reg 84 push_reg r36, \reg 85 push_reg r35, \reg 86 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34) 87 .endm 88 89 .macro panic str 90 .pushsection .rodata, "a" 911: 92 .asciz "\str" 93 .popsection 94 { 95 moveli r0, lo16(1b) 96 } 97 { 98 auli r0, r0, ha16(1b) 99 jal panic 100 } 101 .endm 102 103#ifdef __COLLECT_LINKER_FEEDBACK__ 104 .pushsection .text.intvec_feedback,"ax" 105intvec_feedback: 106 .popsection 107#endif 108 109 /* 110 * Default interrupt handler. 111 * 112 * vecnum is where we'll put this code. 113 * c_routine is the C routine we'll call. 114 * 115 * The C routine is passed two arguments: 116 * - A pointer to the pt_regs state. 117 * - The interrupt vector number. 118 * 119 * The "processing" argument specifies the code for processing 120 * the interrupt. Defaults to "handle_interrupt". 121 */ 122 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt 123 .org (\vecnum << 8) 124intvec_\vecname: 125 .ifc \vecnum, INT_SWINT_1 126 blz TREG_SYSCALL_NR_NAME, sys_cmpxchg 127 .endif 128 129 /* Temporarily save a register so we have somewhere to work. */ 130 131 mtspr SPR_SYSTEM_SAVE_K_1, r0 132 mfspr r0, SPR_EX_CONTEXT_K_1 133 134 /* The cmpxchg code clears sp to force us to reset it here on fault. */ 135 { 136 bz sp, 2f 137 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 138 } 139 140 .ifc \vecnum, INT_DOUBLE_FAULT 141 /* 142 * For double-faults from user-space, fall through to the normal 143 * register save and stack setup path. Otherwise, it's the 144 * hypervisor giving us one last chance to dump diagnostics, and we 145 * branch to the kernel_double_fault routine to do so. 146 */ 147 bz r0, 1f 148 j _kernel_double_fault 1491: 150 .else 151 /* 152 * If we're coming from user-space, then set sp to the top of 153 * the kernel stack. Otherwise, assume sp is already valid. 154 */ 155 { 156 bnz r0, 0f 157 move r0, sp 158 } 159 .endif 160 161 .ifc \c_routine, do_page_fault 162 /* 163 * The page_fault handler may be downcalled directly by the 164 * hypervisor even when Linux is running and has ICS set. 165 * 166 * In this case the contents of EX_CONTEXT_K_1 reflect the 167 * previous fault and can't be relied on to choose whether or 168 * not to reinitialize the stack pointer. So we add a test 169 * to see whether SYSTEM_SAVE_K_2 has the high bit set, 170 * and if so we don't reinitialize sp, since we must be coming 171 * from Linux. (In fact the precise case is !(val & ~1), 172 * but any Linux PC has to have the high bit set.) 173 * 174 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for 175 * any path that turns into a downcall to one of our TLB handlers. 176 */ 177 mfspr r0, SPR_SYSTEM_SAVE_K_2 178 { 179 blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */ 180 move r0, sp 181 } 182 .endif 183 1842: 185 /* 186 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and 187 * the current stack top in the higher bits. So we recover 188 * our stack top by just masking off the low bits, then 189 * point sp at the top aligned address on the actual stack page. 190 */ 191 mfspr r0, SPR_SYSTEM_SAVE_K_0 192 mm r0, r0, zero, LOG2_THREAD_SIZE, 31 193 1940: 195 /* 196 * Align the stack mod 64 so we can properly predict what 197 * cache lines we need to write-hint to reduce memory fetch 198 * latency as we enter the kernel. The layout of memory is 199 * as follows, with cache line 0 at the lowest VA, and cache 200 * line 4 just below the r0 value this "andi" computes. 201 * Note that we never write to cache line 4, and we skip 202 * cache line 1 for syscalls. 203 * 204 * cache line 4: ptregs padding (two words) 205 * cache line 3: r46...lr, pc, ex1, faultnum, orig_r0, flags, pad 206 * cache line 2: r30...r45 207 * cache line 1: r14...r29 208 * cache line 0: 2 x frame, r0..r13 209 */ 210 andi r0, r0, -64 211 212 /* 213 * Push the first four registers on the stack, so that we can set 214 * them to vector-unique values before we jump to the common code. 215 * 216 * Registers are pushed on the stack as a struct pt_regs, 217 * with the sp initially just above the struct, and when we're 218 * done, sp points to the base of the struct, minus 219 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code. 220 * 221 * This routine saves just the first four registers, plus the 222 * stack context so we can do proper backtracing right away, 223 * and defers to handle_interrupt to save the rest. 224 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum. 225 */ 226 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP) 227 wh64 r0 /* cache line 3 */ 228 { 229 sw r0, lr 230 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR 231 } 232 { 233 sw r0, sp 234 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP 235 } 236 { 237 sw sp, r52 238 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52) 239 } 240 wh64 sp /* cache line 0 */ 241 { 242 sw sp, r1 243 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1) 244 } 245 { 246 sw sp, r2 247 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2) 248 } 249 { 250 sw sp, r3 251 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3) 252 } 253 mfspr r0, SPR_EX_CONTEXT_K_0 254 .ifc \processing,handle_syscall 255 /* 256 * Bump the saved PC by one bundle so that when we return, we won't 257 * execute the same swint instruction again. We need to do this while 258 * we're in the critical section. 259 */ 260 addi r0, r0, 8 261 .endif 262 { 263 sw sp, r0 264 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC 265 } 266 mfspr r0, SPR_EX_CONTEXT_K_1 267 { 268 sw sp, r0 269 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1 270 /* 271 * Use r0 for syscalls so it's a temporary; use r1 for interrupts 272 * so that it gets passed through unchanged to the handler routine. 273 * Note that the .if conditional confusingly spans bundles. 274 */ 275 .ifc \processing,handle_syscall 276 movei r0, \vecnum 277 } 278 { 279 sw sp, r0 280 .else 281 movei r1, \vecnum 282 } 283 { 284 sw sp, r1 285 .endif 286 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM 287 } 288 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */ 289 { 290 sw sp, r0 291 addi sp, sp, -PTREGS_OFFSET_REG(0) - 4 292 } 293 { 294 sw sp, zero /* write zero into "Next SP" frame pointer */ 295 addi sp, sp, -4 /* leave SP pointing at bottom of frame */ 296 } 297 .ifc \processing,handle_syscall 298 j handle_syscall 299 .else 300 /* 301 * Capture per-interrupt SPR context to registers. 302 * We overload the meaning of r3 on this path such that if its bit 31 303 * is set, we have to mask all interrupts including NMIs before 304 * clearing the interrupt critical section bit. 305 * See discussion below at "finish_interrupt_save". 306 */ 307 .ifc \c_routine, do_page_fault 308 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */ 309 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */ 310 .else 311 .ifc \vecnum, INT_DOUBLE_FAULT 312 { 313 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */ 314 movei r3, 0 315 } 316 .else 317 .ifc \c_routine, do_trap 318 { 319 mfspr r2, GPV_REASON 320 movei r3, 0 321 } 322 .else 323 .ifc \c_routine, op_handle_perf_interrupt 324 { 325 mfspr r2, PERF_COUNT_STS 326 movei r3, -1 /* not used, but set for consistency */ 327 } 328 .else 329#if CHIP_HAS_AUX_PERF_COUNTERS() 330 .ifc \c_routine, op_handle_aux_perf_interrupt 331 { 332 mfspr r2, AUX_PERF_COUNT_STS 333 movei r3, -1 /* not used, but set for consistency */ 334 } 335 .else 336#endif 337 movei r3, 0 338#if CHIP_HAS_AUX_PERF_COUNTERS() 339 .endif 340#endif 341 .endif 342 .endif 343 .endif 344 .endif 345 /* Put function pointer in r0 */ 346 moveli r0, lo16(\c_routine) 347 { 348 auli r0, r0, ha16(\c_routine) 349 j \processing 350 } 351 .endif 352 ENDPROC(intvec_\vecname) 353 354#ifdef __COLLECT_LINKER_FEEDBACK__ 355 .pushsection .text.intvec_feedback,"ax" 356 .org (\vecnum << 5) 357 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8) 358 jrp lr 359 .popsection 360#endif 361 362 .endm 363 364 365 /* 366 * Save the rest of the registers that we didn't save in the actual 367 * vector itself. We can't use r0-r10 inclusive here. 368 */ 369 .macro finish_interrupt_save, function 370 371 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */ 372 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0) 373 { 374 .ifc \function,handle_syscall 375 sw r52, r0 376 .else 377 sw r52, zero 378 .endif 379 PTREGS_PTR(r52, PTREGS_OFFSET_TP) 380 } 381 382 /* 383 * For ordinary syscalls, we save neither caller- nor callee- 384 * save registers, since the syscall invoker doesn't expect the 385 * caller-saves to be saved, and the called kernel functions will 386 * take care of saving the callee-saves for us. 387 * 388 * For interrupts we save just the caller-save registers. Saving 389 * them is required (since the "caller" can't save them). Again, 390 * the called kernel functions will restore the callee-save 391 * registers for us appropriately. 392 * 393 * On return, we normally restore nothing special for syscalls, 394 * and just the caller-save registers for interrupts. 395 * 396 * However, there are some important caveats to all this: 397 * 398 * - We always save a few callee-save registers to give us 399 * some scratchpad registers to carry across function calls. 400 * 401 * - fork/vfork/etc require us to save all the callee-save 402 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below. 403 * 404 * - We always save r0..r5 and r10 for syscalls, since we need 405 * to reload them a bit later for the actual kernel call, and 406 * since we might need them for -ERESTARTNOINTR, etc. 407 * 408 * - Before invoking a signal handler, we save the unsaved 409 * callee-save registers so they are visible to the 410 * signal handler or any ptracer. 411 * 412 * - If the unsaved callee-save registers are modified, we set 413 * a bit in pt_regs so we know to reload them from pt_regs 414 * and not just rely on the kernel function unwinding. 415 * (Done for ptrace register writes and SA_SIGINFO handler.) 416 */ 417 { 418 sw r52, tp 419 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33)) 420 } 421 wh64 r52 /* cache line 2 */ 422 push_reg r33, r52 423 push_reg r32, r52 424 push_reg r31, r52 425 .ifc \function,handle_syscall 426 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30) 427 push_reg TREG_SYSCALL_NR_NAME, r52, \ 428 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL 429 .else 430 431 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30) 432 wh64 r52 /* cache line 1 */ 433 push_reg r29, r52 434 push_reg r28, r52 435 push_reg r27, r52 436 push_reg r26, r52 437 push_reg r25, r52 438 push_reg r24, r52 439 push_reg r23, r52 440 push_reg r22, r52 441 push_reg r21, r52 442 push_reg r20, r52 443 push_reg r19, r52 444 push_reg r18, r52 445 push_reg r17, r52 446 push_reg r16, r52 447 push_reg r15, r52 448 push_reg r14, r52 449 push_reg r13, r52 450 push_reg r12, r52 451 push_reg r11, r52 452 push_reg r10, r52 453 push_reg r9, r52 454 push_reg r8, r52 455 push_reg r7, r52 456 push_reg r6, r52 457 458 .endif 459 460 push_reg r5, r52 461 sw r52, r4 462 463 /* Load tp with our per-cpu offset. */ 464#ifdef CONFIG_SMP 465 { 466 mfspr r20, SPR_SYSTEM_SAVE_K_0 467 moveli r21, lo16(__per_cpu_offset) 468 } 469 { 470 auli r21, r21, ha16(__per_cpu_offset) 471 mm r20, r20, zero, 0, LOG2_THREAD_SIZE-1 472 } 473 s2a r20, r20, r21 474 lw tp, r20 475#else 476 move tp, zero 477#endif 478 479 /* 480 * If we will be returning to the kernel, we will need to 481 * reset the interrupt masks to the state they had before. 482 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled. 483 * We load flags in r32 here so we can jump to .Lrestore_regs 484 * directly after do_page_fault_ics() if necessary. 485 */ 486 mfspr r32, SPR_EX_CONTEXT_K_1 487 { 488 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 489 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) 490 } 491 bzt r32, 1f /* zero if from user space */ 492 IRQS_DISABLED(r32) /* zero if irqs enabled */ 493#if PT_FLAGS_DISABLE_IRQ != 1 494# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix 495#endif 4961: 497 .ifnc \function,handle_syscall 498 /* Record the fact that we saved the caller-save registers above. */ 499 ori r32, r32, PT_FLAGS_CALLER_SAVES 500 .endif 501 sw r21, r32 502 503#ifdef __COLLECT_LINKER_FEEDBACK__ 504 /* 505 * Notify the feedback routines that we were in the 506 * appropriate fixed interrupt vector area. Note that we 507 * still have ICS set at this point, so we can't invoke any 508 * atomic operations or we will panic. The feedback 509 * routines internally preserve r0..r10 and r30 up. 510 */ 511 .ifnc \function,handle_syscall 512 shli r20, r1, 5 513 .else 514 moveli r20, INT_SWINT_1 << 5 515 .endif 516 addli r20, r20, lo16(intvec_feedback) 517 auli r20, r20, ha16(intvec_feedback) 518 jalr r20 519 520 /* And now notify the feedback routines that we are here. */ 521 FEEDBACK_ENTER(\function) 522#endif 523 524 /* 525 * we've captured enough state to the stack (including in 526 * particular our EX_CONTEXT state) that we can now release 527 * the interrupt critical section and replace it with our 528 * standard "interrupts disabled" mask value. This allows 529 * synchronous interrupts (and profile interrupts) to punch 530 * through from this point onwards. 531 * 532 * If bit 31 of r3 is set during a non-NMI interrupt, we know we 533 * are on the path where the hypervisor has punched through our 534 * ICS with a page fault, so we call out to do_page_fault_ics() 535 * to figure out what to do with it. If the fault was in 536 * an atomic op, we unlock the atomic lock, adjust the 537 * saved register state a little, and return "zero" in r4, 538 * falling through into the normal page-fault interrupt code. 539 * If the fault was in a kernel-space atomic operation, then 540 * do_page_fault_ics() resolves it itself, returns "one" in r4, 541 * and as a result goes directly to restoring registers and iret, 542 * without trying to adjust the interrupt masks at all. 543 * The do_page_fault_ics() API involves passing and returning 544 * a five-word struct (in registers) to avoid writing the 545 * save and restore code here. 546 */ 547 .ifc \function,handle_nmi 548 IRQ_DISABLE_ALL(r20) 549 .else 550 .ifnc \function,handle_syscall 551 bgezt r3, 1f 552 { 553 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 554 jal do_page_fault_ics 555 } 556 FEEDBACK_REENTER(\function) 557 bzt r4, 1f 558 j .Lrestore_regs 5591: 560 .endif 561 IRQ_DISABLE(r20, r21) 562 .endif 563 mtspr INTERRUPT_CRITICAL_SECTION, zero 564 565#if CHIP_HAS_WH64() 566 /* 567 * Prepare the first 256 stack bytes to be rapidly accessible 568 * without having to fetch the background data. We don't really 569 * know how far to write-hint, but kernel stacks generally 570 * aren't that big, and write-hinting here does take some time. 571 */ 572 addi r52, sp, -64 573 { 574 wh64 r52 575 addi r52, r52, -64 576 } 577 { 578 wh64 r52 579 addi r52, r52, -64 580 } 581 { 582 wh64 r52 583 addi r52, r52, -64 584 } 585 wh64 r52 586#endif 587 588#ifdef CONFIG_TRACE_IRQFLAGS 589 .ifnc \function,handle_nmi 590 /* 591 * We finally have enough state set up to notify the irq 592 * tracing code that irqs were disabled on entry to the handler. 593 * The TRACE_IRQS_OFF call clobbers registers r0-r29. 594 * For syscalls, we already have the register state saved away 595 * on the stack, so we don't bother to do any register saves here, 596 * and later we pop the registers back off the kernel stack. 597 * For interrupt handlers, save r0-r3 in callee-saved registers. 598 */ 599 .ifnc \function,handle_syscall 600 { move r30, r0; move r31, r1 } 601 { move r32, r2; move r33, r3 } 602 .endif 603 TRACE_IRQS_OFF 604 .ifnc \function,handle_syscall 605 { move r0, r30; move r1, r31 } 606 { move r2, r32; move r3, r33 } 607 .endif 608 .endif 609#endif 610 611 .endm 612 613 .macro check_single_stepping, kind, not_single_stepping 614 /* 615 * Check for single stepping in user-level priv 616 * kind can be "normal", "ill", or "syscall" 617 * At end, if fall-thru 618 * r29: thread_info->step_state 619 * r28: &pt_regs->pc 620 * r27: pt_regs->pc 621 * r26: thread_info->step_state->buffer 622 */ 623 624 /* Check for single stepping */ 625 GET_THREAD_INFO(r29) 626 { 627 /* Get pointer to field holding step state */ 628 addi r29, r29, THREAD_INFO_STEP_STATE_OFFSET 629 630 /* Get pointer to EX1 in register state */ 631 PTREGS_PTR(r27, PTREGS_OFFSET_EX1) 632 } 633 { 634 /* Get pointer to field holding PC */ 635 PTREGS_PTR(r28, PTREGS_OFFSET_PC) 636 637 /* Load the pointer to the step state */ 638 lw r29, r29 639 } 640 /* Load EX1 */ 641 lw r27, r27 642 { 643 /* Points to flags */ 644 addi r23, r29, SINGLESTEP_STATE_FLAGS_OFFSET 645 646 /* No single stepping if there is no step state structure */ 647 bzt r29, \not_single_stepping 648 } 649 { 650 /* mask off ICS and any other high bits */ 651 andi r27, r27, SPR_EX_CONTEXT_1_1__PL_MASK 652 653 /* Load pointer to single step instruction buffer */ 654 lw r26, r29 655 } 656 /* Check priv state */ 657 bnz r27, \not_single_stepping 658 659 /* Get flags */ 660 lw r22, r23 661 { 662 /* Branch if single-step mode not enabled */ 663 bbnst r22, \not_single_stepping 664 665 /* Clear enabled flag */ 666 andi r22, r22, ~SINGLESTEP_STATE_MASK_IS_ENABLED 667 } 668 .ifc \kind,normal 669 { 670 /* Load PC */ 671 lw r27, r28 672 673 /* Point to the entry containing the original PC */ 674 addi r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET 675 } 676 { 677 /* Disable single stepping flag */ 678 sw r23, r22 679 } 680 { 681 /* Get the original pc */ 682 lw r24, r24 683 684 /* See if the PC is at the start of the single step buffer */ 685 seq r25, r26, r27 686 } 687 /* 688 * NOTE: it is really expected that the PC be in the single step buffer 689 * at this point 690 */ 691 bzt r25, \not_single_stepping 692 693 /* Restore the original PC */ 694 sw r28, r24 695 .else 696 .ifc \kind,syscall 697 { 698 /* Load PC */ 699 lw r27, r28 700 701 /* Point to the entry containing the next PC */ 702 addi r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET 703 } 704 { 705 /* Increment the stopped PC by the bundle size */ 706 addi r26, r26, 8 707 708 /* Disable single stepping flag */ 709 sw r23, r22 710 } 711 { 712 /* Get the next pc */ 713 lw r24, r24 714 715 /* 716 * See if the PC is one bundle past the start of the 717 * single step buffer 718 */ 719 seq r25, r26, r27 720 } 721 { 722 /* 723 * NOTE: it is really expected that the PC be in the 724 * single step buffer at this point 725 */ 726 bzt r25, \not_single_stepping 727 } 728 /* Set to the next PC */ 729 sw r28, r24 730 .else 731 { 732 /* Point to 3rd bundle in buffer */ 733 addi r25, r26, 16 734 735 /* Load PC */ 736 lw r27, r28 737 } 738 { 739 /* Disable single stepping flag */ 740 sw r23, r22 741 742 /* See if the PC is in the single step buffer */ 743 slte_u r24, r26, r27 744 } 745 { 746 slte_u r25, r27, r25 747 748 /* 749 * NOTE: it is really expected that the PC be in the 750 * single step buffer at this point 751 */ 752 bzt r24, \not_single_stepping 753 } 754 bzt r25, \not_single_stepping 755 .endif 756 .endif 757 .endm 758 759 /* 760 * Redispatch a downcall. 761 */ 762 .macro dc_dispatch vecnum, vecname 763 .org (\vecnum << 8) 764intvec_\vecname: 765 j hv_downcall_dispatch 766 ENDPROC(intvec_\vecname) 767 .endm 768 769 /* 770 * Common code for most interrupts. The C function we're eventually 771 * going to is in r0, and the faultnum is in r1; the original 772 * values for those registers are on the stack. 773 */ 774 .pushsection .text.handle_interrupt,"ax" 775handle_interrupt: 776 finish_interrupt_save handle_interrupt 777 778 /* 779 * Check for if we are single stepping in user level. If so, then 780 * we need to restore the PC. 781 */ 782 783 check_single_stepping normal, .Ldispatch_interrupt 784.Ldispatch_interrupt: 785 786 /* Jump to the C routine; it should enable irqs as soon as possible. */ 787 { 788 jalr r0 789 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 790 } 791 FEEDBACK_REENTER(handle_interrupt) 792 { 793 movei r30, 0 /* not an NMI */ 794 j interrupt_return 795 } 796 STD_ENDPROC(handle_interrupt) 797 798/* 799 * This routine takes a boolean in r30 indicating if this is an NMI. 800 * If so, we also expect a boolean in r31 indicating whether to 801 * re-enable the oprofile interrupts. 802 */ 803STD_ENTRY(interrupt_return) 804 /* If we're resuming to kernel space, don't check thread flags. */ 805 { 806 bnz r30, .Lrestore_all /* NMIs don't special-case user-space */ 807 PTREGS_PTR(r29, PTREGS_OFFSET_EX1) 808 } 809 lw r29, r29 810 andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 811 { 812 bzt r29, .Lresume_userspace 813 PTREGS_PTR(r29, PTREGS_OFFSET_PC) 814 } 815 816 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */ 817 { 818 lw r28, r29 819 moveli r27, lo16(_cpu_idle_nap) 820 } 821 { 822 auli r27, r27, ha16(_cpu_idle_nap) 823 } 824 { 825 seq r27, r27, r28 826 } 827 { 828 bbns r27, .Lrestore_all 829 addi r28, r28, 8 830 } 831 sw r29, r28 832 j .Lrestore_all 833 834.Lresume_userspace: 835 FEEDBACK_REENTER(interrupt_return) 836 837 /* 838 * Disable interrupts so as to make sure we don't 839 * miss an interrupt that sets any of the thread flags (like 840 * need_resched or sigpending) between sampling and the iret. 841 * Routines like schedule() or do_signal() may re-enable 842 * interrupts before returning. 843 */ 844 IRQ_DISABLE(r20, r21) 845 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */ 846 847 /* Get base of stack in r32; note r30/31 are used as arguments here. */ 848 GET_THREAD_INFO(r32) 849 850 851 /* Check to see if there is any work to do before returning to user. */ 852 { 853 addi r29, r32, THREAD_INFO_FLAGS_OFFSET 854 moveli r1, lo16(_TIF_ALLWORK_MASK) 855 } 856 { 857 lw r29, r29 858 auli r1, r1, ha16(_TIF_ALLWORK_MASK) 859 } 860 and r1, r29, r1 861 bzt r1, .Lrestore_all 862 863 /* 864 * Make sure we have all the registers saved for signal 865 * handling or single-step. Call out to C code to figure out 866 * exactly what we need to do for each flag bit, then if 867 * necessary, reload the flags and recheck. 868 */ 869 push_extra_callee_saves r0 870 { 871 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 872 jal do_work_pending 873 } 874 bnz r0, .Lresume_userspace 875 876 /* 877 * In the NMI case we 878 * omit the call to single_process_check_nohz, which normally checks 879 * to see if we should start or stop the scheduler tick, because 880 * we can't call arbitrary Linux code from an NMI context. 881 * We always call the homecache TLB deferral code to re-trigger 882 * the deferral mechanism. 883 * 884 * The other chunk of responsibility this code has is to reset the 885 * interrupt masks appropriately to reset irqs and NMIs. We have 886 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the 887 * lockdep-type stuff, but we can't set ICS until afterwards, since 888 * ICS can only be used in very tight chunks of code to avoid 889 * tripping over various assertions that it is off. 890 * 891 * (There is what looks like a window of vulnerability here since 892 * we might take a profile interrupt between the two SPR writes 893 * that set the mask, but since we write the low SPR word first, 894 * and our interrupt entry code checks the low SPR word, any 895 * profile interrupt will actually disable interrupts in both SPRs 896 * before returning, which is OK.) 897 */ 898.Lrestore_all: 899 PTREGS_PTR(r0, PTREGS_OFFSET_EX1) 900 { 901 lw r0, r0 902 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS) 903 } 904 { 905 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK 906 lw r32, r32 907 } 908 bnz r0, 1f 909 j 2f 910#if PT_FLAGS_DISABLE_IRQ != 1 911# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use bbnst below 912#endif 9131: bbnst r32, 2f 914 IRQ_DISABLE(r20,r21) 915 TRACE_IRQS_OFF 916 movei r0, 1 917 mtspr INTERRUPT_CRITICAL_SECTION, r0 918 bzt r30, .Lrestore_regs 919 j 3f 9202: TRACE_IRQS_ON 921 movei r0, 1 922 mtspr INTERRUPT_CRITICAL_SECTION, r0 923 IRQ_ENABLE(r20, r21) 924 bzt r30, .Lrestore_regs 9253: 926 927 928 /* 929 * We now commit to returning from this interrupt, since we will be 930 * doing things like setting EX_CONTEXT SPRs and unwinding the stack 931 * frame. No calls should be made to any other code after this point. 932 * This code should only be entered with ICS set. 933 * r32 must still be set to ptregs.flags. 934 * We launch loads to each cache line separately first, so we can 935 * get some parallelism out of the memory subsystem. 936 * We start zeroing caller-saved registers throughout, since 937 * that will save some cycles if this turns out to be a syscall. 938 */ 939.Lrestore_regs: 940 FEEDBACK_REENTER(interrupt_return) /* called from elsewhere */ 941 942 /* 943 * Rotate so we have one high bit and one low bit to test. 944 * - low bit says whether to restore all the callee-saved registers, 945 * or just r30-r33, and r52 up. 946 * - high bit (i.e. sign bit) says whether to restore all the 947 * caller-saved registers, or just r0. 948 */ 949#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4 950# error Rotate trick does not work :-) 951#endif 952 { 953 rli r20, r32, 30 954 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0)) 955 } 956 957 /* 958 * Load cache lines 0, 2, and 3 in that order, then use 959 * the last loaded value, which makes it likely that the other 960 * cache lines have also loaded, at which point we should be 961 * able to safely read all the remaining words on those cache 962 * lines without waiting for the memory subsystem. 963 */ 964 pop_reg_zero r0, r28, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0) 965 pop_reg_zero r30, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(30) 966 pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC 967 pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1 968 { 969 mtspr SPR_EX_CONTEXT_K_0, r21 970 move r5, zero 971 } 972 { 973 mtspr SPR_EX_CONTEXT_K_1, lr 974 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 975 } 976 977 /* Restore callee-saveds that we actually use. */ 978 pop_reg_zero r52, r6, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_REG(52) 979 pop_reg_zero r31, r7 980 pop_reg_zero r32, r8 981 pop_reg_zero r33, r9, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33) 982 983 /* 984 * If we modified other callee-saveds, restore them now. 985 * This is rare, but could be via ptrace or signal handler. 986 */ 987 { 988 move r10, zero 989 bbs r20, .Lrestore_callees 990 } 991.Lcontinue_restore_regs: 992 993 /* Check if we're returning from a syscall. */ 994 { 995 move r11, zero 996 blzt r20, 1f /* no, so go restore callee-save registers */ 997 } 998 999 /* 1000 * Check if we're returning to userspace. 1001 * Note that if we're not, we don't worry about zeroing everything. 1002 */ 1003 { 1004 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29) 1005 bnz lr, .Lkernel_return 1006 } 1007 1008 /* 1009 * On return from syscall, we've restored r0 from pt_regs, but we 1010 * clear the remainder of the caller-saved registers. We could 1011 * restore the syscall arguments, but there's not much point, 1012 * and it ensures user programs aren't trying to use the 1013 * caller-saves if we clear them, as well as avoiding leaking 1014 * kernel pointers into userspace. 1015 */ 1016 pop_reg_zero lr, r12, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR 1017 pop_reg_zero tp, r13, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP 1018 { 1019 lw sp, sp 1020 move r14, zero 1021 move r15, zero 1022 } 1023 { move r16, zero; move r17, zero } 1024 { move r18, zero; move r19, zero } 1025 { move r20, zero; move r21, zero } 1026 { move r22, zero; move r23, zero } 1027 { move r24, zero; move r25, zero } 1028 { move r26, zero; move r27, zero } 1029 1030 /* Set r1 to errno if we are returning an error, otherwise zero. */ 1031 { 1032 moveli r29, 4096 1033 sub r1, zero, r0 1034 } 1035 slt_u r29, r1, r29 1036 { 1037 mnz r1, r29, r1 1038 move r29, zero 1039 } 1040 iret 1041 1042 /* 1043 * Not a syscall, so restore caller-saved registers. 1044 * First kick off a load for cache line 1, which we're touching 1045 * for the first time here. 1046 */ 1047 .align 64 10481: pop_reg r29, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(29) 1049 pop_reg r1 1050 pop_reg r2 1051 pop_reg r3 1052 pop_reg r4 1053 pop_reg r5 1054 pop_reg r6 1055 pop_reg r7 1056 pop_reg r8 1057 pop_reg r9 1058 pop_reg r10 1059 pop_reg r11 1060 pop_reg r12 1061 pop_reg r13 1062 pop_reg r14 1063 pop_reg r15 1064 pop_reg r16 1065 pop_reg r17 1066 pop_reg r18 1067 pop_reg r19 1068 pop_reg r20 1069 pop_reg r21 1070 pop_reg r22 1071 pop_reg r23 1072 pop_reg r24 1073 pop_reg r25 1074 pop_reg r26 1075 pop_reg r27 1076 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28) 1077 /* r29 already restored above */ 1078 bnz lr, .Lkernel_return 1079 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR 1080 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP 1081 lw sp, sp 1082 iret 1083 1084 /* 1085 * We can't restore tp when in kernel mode, since a thread might 1086 * have migrated from another cpu and brought a stale tp value. 1087 */ 1088.Lkernel_return: 1089 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR 1090 lw sp, sp 1091 iret 1092 1093 /* Restore callee-saved registers from r34 to r51. */ 1094.Lrestore_callees: 1095 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29) 1096 pop_reg r34 1097 pop_reg r35 1098 pop_reg r36 1099 pop_reg r37 1100 pop_reg r38 1101 pop_reg r39 1102 pop_reg r40 1103 pop_reg r41 1104 pop_reg r42 1105 pop_reg r43 1106 pop_reg r44 1107 pop_reg r45 1108 pop_reg r46 1109 pop_reg r47 1110 pop_reg r48 1111 pop_reg r49 1112 pop_reg r50 1113 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51) 1114 j .Lcontinue_restore_regs 1115 STD_ENDPROC(interrupt_return) 1116 1117 /* 1118 * Some interrupts don't check for single stepping 1119 */ 1120 .pushsection .text.handle_interrupt_no_single_step,"ax" 1121handle_interrupt_no_single_step: 1122 finish_interrupt_save handle_interrupt_no_single_step 1123 { 1124 jalr r0 1125 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1126 } 1127 FEEDBACK_REENTER(handle_interrupt_no_single_step) 1128 { 1129 movei r30, 0 /* not an NMI */ 1130 j interrupt_return 1131 } 1132 STD_ENDPROC(handle_interrupt_no_single_step) 1133 1134 /* 1135 * "NMI" interrupts mask ALL interrupts before calling the 1136 * handler, and don't check thread flags, etc., on the way 1137 * back out. In general, the only things we do here for NMIs 1138 * are the register save/restore, fixing the PC if we were 1139 * doing single step, and the dataplane kernel-TLB management. 1140 * We don't (for example) deal with start/stop of the sched tick. 1141 */ 1142 .pushsection .text.handle_nmi,"ax" 1143handle_nmi: 1144 finish_interrupt_save handle_nmi 1145 check_single_stepping normal, .Ldispatch_nmi 1146.Ldispatch_nmi: 1147 { 1148 jalr r0 1149 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1150 } 1151 FEEDBACK_REENTER(handle_nmi) 1152 j interrupt_return 1153 STD_ENDPROC(handle_nmi) 1154 1155 /* 1156 * Parallel code for syscalls to handle_interrupt. 1157 */ 1158 .pushsection .text.handle_syscall,"ax" 1159handle_syscall: 1160 finish_interrupt_save handle_syscall 1161 1162 /* 1163 * Check for if we are single stepping in user level. If so, then 1164 * we need to restore the PC. 1165 */ 1166 check_single_stepping syscall, .Ldispatch_syscall 1167.Ldispatch_syscall: 1168 1169 /* Enable irqs. */ 1170 TRACE_IRQS_ON 1171 IRQ_ENABLE(r20, r21) 1172 1173 /* Bump the counter for syscalls made on this tile. */ 1174 moveli r20, lo16(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) 1175 auli r20, r20, ha16(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) 1176 add r20, r20, tp 1177 lw r21, r20 1178 addi r21, r21, 1 1179 sw r20, r21 1180 1181 /* Trace syscalls, if requested. */ 1182 GET_THREAD_INFO(r31) 1183 addi r31, r31, THREAD_INFO_FLAGS_OFFSET 1184 lw r30, r31 1185 andi r30, r30, _TIF_SYSCALL_TRACE 1186 bzt r30, .Lrestore_syscall_regs 1187 jal do_syscall_trace 1188 FEEDBACK_REENTER(handle_syscall) 1189 1190 /* 1191 * We always reload our registers from the stack at this 1192 * point. They might be valid, if we didn't build with 1193 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not 1194 * doing syscall tracing, but there are enough cases now that it 1195 * seems simplest just to do the reload unconditionally. 1196 */ 1197.Lrestore_syscall_regs: 1198 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0)) 1199 pop_reg r0, r11 1200 pop_reg r1, r11 1201 pop_reg r2, r11 1202 pop_reg r3, r11 1203 pop_reg r4, r11 1204 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5) 1205 pop_reg TREG_SYSCALL_NR_NAME, r11 1206 1207 /* Ensure that the syscall number is within the legal range. */ 1208 moveli r21, __NR_syscalls 1209 { 1210 slt_u r21, TREG_SYSCALL_NR_NAME, r21 1211 moveli r20, lo16(sys_call_table) 1212 } 1213 { 1214 bbns r21, .Linvalid_syscall 1215 auli r20, r20, ha16(sys_call_table) 1216 } 1217 s2a r20, TREG_SYSCALL_NR_NAME, r20 1218 lw r20, r20 1219 1220 /* Jump to syscall handler. */ 1221 jalr r20 1222.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */ 1223 1224 /* 1225 * Write our r0 onto the stack so it gets restored instead 1226 * of whatever the user had there before. 1227 */ 1228 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) 1229 sw r29, r0 1230 1231.Lsyscall_sigreturn_skip: 1232 FEEDBACK_REENTER(handle_syscall) 1233 1234 /* Do syscall trace again, if requested. */ 1235 lw r30, r31 1236 andi r30, r30, _TIF_SYSCALL_TRACE 1237 bzt r30, 1f 1238 jal do_syscall_trace 1239 FEEDBACK_REENTER(handle_syscall) 12401: j .Lresume_userspace /* jump into middle of interrupt_return */ 1241 1242.Linvalid_syscall: 1243 /* Report an invalid syscall back to the user program */ 1244 { 1245 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) 1246 movei r28, -ENOSYS 1247 } 1248 sw r29, r28 1249 j .Lresume_userspace /* jump into middle of interrupt_return */ 1250 STD_ENDPROC(handle_syscall) 1251 1252 /* Return the address for oprofile to suppress in backtraces. */ 1253STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall) 1254 lnk r0 1255 { 1256 addli r0, r0, .Lhandle_syscall_link - . 1257 jrp lr 1258 } 1259 STD_ENDPROC(handle_syscall_link_address) 1260 1261STD_ENTRY(ret_from_fork) 1262 jal sim_notify_fork 1263 jal schedule_tail 1264 FEEDBACK_REENTER(ret_from_fork) 1265 j .Lresume_userspace /* jump into middle of interrupt_return */ 1266 STD_ENDPROC(ret_from_fork) 1267 1268 /* 1269 * Code for ill interrupt. 1270 */ 1271 .pushsection .text.handle_ill,"ax" 1272handle_ill: 1273 finish_interrupt_save handle_ill 1274 1275 /* 1276 * Check for if we are single stepping in user level. If so, then 1277 * we need to restore the PC. 1278 */ 1279 check_single_stepping ill, .Ldispatch_normal_ill 1280 1281 { 1282 /* See if the PC is the 1st bundle in the buffer */ 1283 seq r25, r27, r26 1284 1285 /* Point to the 2nd bundle in the buffer */ 1286 addi r26, r26, 8 1287 } 1288 { 1289 /* Point to the original pc */ 1290 addi r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET 1291 1292 /* Branch if the PC is the 1st bundle in the buffer */ 1293 bnz r25, 3f 1294 } 1295 { 1296 /* See if the PC is the 2nd bundle of the buffer */ 1297 seq r25, r27, r26 1298 1299 /* Set PC to next instruction */ 1300 addi r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET 1301 } 1302 { 1303 /* Point to flags */ 1304 addi r25, r29, SINGLESTEP_STATE_FLAGS_OFFSET 1305 1306 /* Branch if PC is in the second bundle */ 1307 bz r25, 2f 1308 } 1309 /* Load flags */ 1310 lw r25, r25 1311 { 1312 /* 1313 * Get the offset for the register to restore 1314 * Note: the lower bound is 2, so we have implicit scaling by 4. 1315 * No multiplication of the register number by the size of a register 1316 * is needed. 1317 */ 1318 mm r27, r25, zero, SINGLESTEP_STATE_TARGET_LB, \ 1319 SINGLESTEP_STATE_TARGET_UB 1320 1321 /* Mask Rewrite_LR */ 1322 andi r25, r25, SINGLESTEP_STATE_MASK_UPDATE 1323 } 1324 { 1325 addi r29, r29, SINGLESTEP_STATE_UPDATE_VALUE_OFFSET 1326 1327 /* Don't rewrite temp register */ 1328 bz r25, 3f 1329 } 1330 { 1331 /* Get the temp value */ 1332 lw r29, r29 1333 1334 /* Point to where the register is stored */ 1335 add r27, r27, sp 1336 } 1337 1338 /* Add in the C ABI save area size to the register offset */ 1339 addi r27, r27, C_ABI_SAVE_AREA_SIZE 1340 1341 /* Restore the user's register with the temp value */ 1342 sw r27, r29 1343 j 3f 1344 13452: 1346 /* Must be in the third bundle */ 1347 addi r24, r29, SINGLESTEP_STATE_BRANCH_NEXT_PC_OFFSET 1348 13493: 1350 /* set PC and continue */ 1351 lw r26, r24 1352 sw r28, r26 1353 1354 /* 1355 * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill. 1356 * The normal non-arch flow redundantly clears TIF_SINGLESTEP, but we 1357 * need to clear it here and can't really impose on all other arches. 1358 * So what's another write between friends? 1359 */ 1360 GET_THREAD_INFO(r0) 1361 1362 addi r1, r0, THREAD_INFO_FLAGS_OFFSET 1363 { 1364 lw r2, r1 1365 addi r0, r0, THREAD_INFO_TASK_OFFSET /* currently a no-op */ 1366 } 1367 andi r2, r2, ~_TIF_SINGLESTEP 1368 sw r1, r2 1369 1370 /* Issue a sigtrap */ 1371 { 1372 lw r0, r0 /* indirect thru thread_info to get task_info*/ 1373 addi r1, sp, C_ABI_SAVE_AREA_SIZE /* put ptregs pointer into r1 */ 1374 move r2, zero /* load error code into r2 */ 1375 } 1376 1377 jal send_sigtrap /* issue a SIGTRAP */ 1378 FEEDBACK_REENTER(handle_ill) 1379 j .Lresume_userspace /* jump into middle of interrupt_return */ 1380 1381.Ldispatch_normal_ill: 1382 { 1383 jalr r0 1384 PTREGS_PTR(r0, PTREGS_OFFSET_BASE) 1385 } 1386 FEEDBACK_REENTER(handle_ill) 1387 { 1388 movei r30, 0 /* not an NMI */ 1389 j interrupt_return 1390 } 1391 STD_ENDPROC(handle_ill) 1392 1393/* Various stub interrupt handlers and syscall handlers */ 1394 1395STD_ENTRY_LOCAL(_kernel_double_fault) 1396 mfspr r1, SPR_EX_CONTEXT_K_0 1397 move r2, lr 1398 move r3, sp 1399 move r4, r52 1400 addi sp, sp, -C_ABI_SAVE_AREA_SIZE 1401 j kernel_double_fault 1402 STD_ENDPROC(_kernel_double_fault) 1403 1404STD_ENTRY_LOCAL(bad_intr) 1405 mfspr r2, SPR_EX_CONTEXT_K_0 1406 panic "Unhandled interrupt %#x: PC %#lx" 1407 STD_ENDPROC(bad_intr) 1408 1409/* Put address of pt_regs in reg and jump. */ 1410#define PTREGS_SYSCALL(x, reg) \ 1411 STD_ENTRY(_##x); \ 1412 { \ 1413 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \ 1414 j x \ 1415 }; \ 1416 STD_ENDPROC(_##x) 1417 1418/* 1419 * Special-case sigreturn to not write r0 to the stack on return. 1420 * This is technically more efficient, but it also avoids difficulties 1421 * in the 64-bit OS when handling 32-bit compat code, since we must not 1422 * sign-extend r0 for the sigreturn return-value case. 1423 */ 1424#define PTREGS_SYSCALL_SIGRETURN(x, reg) \ 1425 STD_ENTRY(_##x); \ 1426 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \ 1427 { \ 1428 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \ 1429 j x \ 1430 }; \ 1431 STD_ENDPROC(_##x) 1432 1433PTREGS_SYSCALL(sys_execve, r3) 1434PTREGS_SYSCALL(sys_sigaltstack, r2) 1435PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0) 1436PTREGS_SYSCALL(sys_cmpxchg_badaddr, r1) 1437 1438/* Save additional callee-saves to pt_regs, put address in r4 and jump. */ 1439STD_ENTRY(_sys_clone) 1440 push_extra_callee_saves r4 1441 j sys_clone 1442 STD_ENDPROC(_sys_clone) 1443 1444/* 1445 * This entrypoint is taken for the cmpxchg and atomic_update fast 1446 * swints. We may wish to generalize it to other fast swints at some 1447 * point, but for now there are just two very similar ones, which 1448 * makes it faster. 1449 * 1450 * The fast swint code is designed to have a small footprint. It does 1451 * not save or restore any GPRs, counting on the caller-save registers 1452 * to be available to it on entry. It does not modify any callee-save 1453 * registers (including "lr"). It does not check what PL it is being 1454 * called at, so you'd better not call it other than at PL0. 1455 * The <atomic.h> wrapper assumes it only clobbers r20-r29, so if 1456 * it ever is necessary to use more registers, be aware. 1457 * 1458 * It does not use the stack, but since it might be re-interrupted by 1459 * a page fault which would assume the stack was valid, it does 1460 * save/restore the stack pointer and zero it out to make sure it gets reset. 1461 * Since we always keep interrupts disabled, the hypervisor won't 1462 * clobber our EX_CONTEXT_K_x registers, so we don't save/restore them 1463 * (other than to advance the PC on return). 1464 * 1465 * We have to manually validate the user vs kernel address range 1466 * (since at PL1 we can read/write both), and for performance reasons 1467 * we don't allow cmpxchg on the fc000000 memory region, since we only 1468 * validate that the user address is below PAGE_OFFSET. 1469 * 1470 * We place it in the __HEAD section to ensure it is relatively 1471 * near to the intvec_SWINT_1 code (reachable by a conditional branch). 1472 * 1473 * Our use of ATOMIC_LOCK_REG here must match do_page_fault_ics(). 1474 * 1475 * As we do in lib/atomic_asm_32.S, we bypass a store if the value we 1476 * would store is the same as the value we just loaded. 1477 */ 1478 __HEAD 1479 .align 64 1480 /* Align much later jump on the start of a cache line. */ 1481#if !ATOMIC_LOCKS_FOUND_VIA_TABLE() 1482 nop 1483#if PAGE_SIZE >= 0x10000 1484 nop 1485#endif 1486#endif 1487ENTRY(sys_cmpxchg) 1488 1489 /* 1490 * Save "sp" and set it zero for any possible page fault. 1491 * 1492 * HACK: We want to both zero sp and check r0's alignment, 1493 * so we do both at once. If "sp" becomes nonzero we 1494 * know r0 is unaligned and branch to the error handler that 1495 * restores sp, so this is OK. 1496 * 1497 * ICS is disabled right now so having a garbage but nonzero 1498 * sp is OK, since we won't execute any faulting instructions 1499 * when it is nonzero. 1500 */ 1501 { 1502 move r27, sp 1503 andi sp, r0, 3 1504 } 1505 1506 /* 1507 * Get the lock address in ATOMIC_LOCK_REG, and also validate that the 1508 * address is less than PAGE_OFFSET, since that won't trap at PL1. 1509 * We only use bits less than PAGE_SHIFT to avoid having to worry 1510 * about aliasing among multiple mappings of the same physical page, 1511 * and we ignore the low 3 bits so we have one lock that covers 1512 * both a cmpxchg64() and a cmpxchg() on either its low or high word. 1513 * NOTE: this must match __atomic_hashed_lock() in lib/atomic_32.c. 1514 */ 1515 1516#if (PAGE_OFFSET & 0xffff) != 0 1517# error Code here assumes PAGE_OFFSET can be loaded with just hi16() 1518#endif 1519 1520#if ATOMIC_LOCKS_FOUND_VIA_TABLE() 1521 { 1522 /* Check for unaligned input. */ 1523 bnz sp, .Lcmpxchg_badaddr 1524 mm r25, r0, zero, 3, PAGE_SHIFT-1 1525 } 1526 { 1527 crc32_32 r25, zero, r25 1528 moveli r21, lo16(atomic_lock_ptr) 1529 } 1530 { 1531 auli r21, r21, ha16(atomic_lock_ptr) 1532 auli r23, zero, hi16(PAGE_OFFSET) /* hugepage-aligned */ 1533 } 1534 { 1535 shri r20, r25, 32 - ATOMIC_HASH_L1_SHIFT 1536 slt_u r23, r0, r23 1537 lw r26, r0 /* see comment in the "#else" for the "lw r26". */ 1538 } 1539 { 1540 s2a r21, r20, r21 1541 bbns r23, .Lcmpxchg_badaddr 1542 } 1543 { 1544 lw r21, r21 1545 seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_cmpxchg64 1546 andi r25, r25, ATOMIC_HASH_L2_SIZE - 1 1547 } 1548 { 1549 /* Branch away at this point if we're doing a 64-bit cmpxchg. */ 1550 bbs r23, .Lcmpxchg64 1551 andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */ 1552 } 1553 { 1554 s2a ATOMIC_LOCK_REG_NAME, r25, r21 1555 j .Lcmpxchg32_tns /* see comment in the #else for the jump. */ 1556 } 1557 1558#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 1559 { 1560 /* Check for unaligned input. */ 1561 bnz sp, .Lcmpxchg_badaddr 1562 auli r23, zero, hi16(PAGE_OFFSET) /* hugepage-aligned */ 1563 } 1564 { 1565 /* 1566 * Slide bits into position for 'mm'. We want to ignore 1567 * the low 3 bits of r0, and consider only the next 1568 * ATOMIC_HASH_SHIFT bits. 1569 * Because of C pointer arithmetic, we want to compute this: 1570 * 1571 * ((char*)atomic_locks + 1572 * (((r0 >> 3) & (1 << (ATOMIC_HASH_SIZE - 1))) << 2)) 1573 * 1574 * Instead of two shifts we just ">> 1", and use 'mm' 1575 * to ignore the low and high bits we don't want. 1576 */ 1577 shri r25, r0, 1 1578 1579 slt_u r23, r0, r23 1580 1581 /* 1582 * Ensure that the TLB is loaded before we take out the lock. 1583 * On tilepro, this will start fetching the value all the way 1584 * into our L1 as well (and if it gets modified before we 1585 * grab the lock, it will be invalidated from our cache 1586 * before we reload it). On tile64, we'll start fetching it 1587 * into our L1 if we're the home, and if we're not, we'll 1588 * still at least start fetching it into the home's L2. 1589 */ 1590 lw r26, r0 1591 } 1592 { 1593 auli r21, zero, ha16(atomic_locks) 1594 1595 bbns r23, .Lcmpxchg_badaddr 1596 } 1597#if PAGE_SIZE < 0x10000 1598 /* atomic_locks is page-aligned so for big pages we don't need this. */ 1599 addli r21, r21, lo16(atomic_locks) 1600#endif 1601 { 1602 /* 1603 * Insert the hash bits into the page-aligned pointer. 1604 * ATOMIC_HASH_SHIFT is so big that we don't actually hash 1605 * the unmasked address bits, as that may cause unnecessary 1606 * collisions. 1607 */ 1608 mm ATOMIC_LOCK_REG_NAME, r25, r21, 2, (ATOMIC_HASH_SHIFT + 2) - 1 1609 1610 seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_cmpxchg64 1611 } 1612 { 1613 /* Branch away at this point if we're doing a 64-bit cmpxchg. */ 1614 bbs r23, .Lcmpxchg64 1615 andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */ 1616 } 1617 { 1618 /* 1619 * We very carefully align the code that actually runs with 1620 * the lock held (twelve bundles) so that we know it is all in 1621 * the icache when we start. This instruction (the jump) is 1622 * at the start of the first cache line, address zero mod 64; 1623 * we jump to the very end of the second cache line to get that 1624 * line loaded in the icache, then fall through to issue the tns 1625 * in the third cache line, at which point it's all cached. 1626 * Note that is for performance, not correctness. 1627 */ 1628 j .Lcmpxchg32_tns 1629 } 1630 1631#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 1632 1633/* Symbol for do_page_fault_ics() to use to compare against the PC. */ 1634.global __sys_cmpxchg_grab_lock 1635__sys_cmpxchg_grab_lock: 1636 1637 /* 1638 * Perform the actual cmpxchg or atomic_update. 1639 */ 1640.Ldo_cmpxchg32: 1641 { 1642 lw r21, r0 1643 seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_atomic_update 1644 move r24, r2 1645 } 1646 { 1647 seq r22, r21, r1 /* See if cmpxchg matches. */ 1648 and r25, r21, r1 /* If atomic_update, compute (*mem & mask) */ 1649 } 1650 { 1651 or r22, r22, r23 /* Skip compare branch for atomic_update. */ 1652 add r25, r25, r2 /* Compute (*mem & mask) + addend. */ 1653 } 1654 { 1655 mvnz r24, r23, r25 /* Use atomic_update value if appropriate. */ 1656 bbns r22, .Lcmpxchg32_nostore 1657 } 1658 seq r22, r24, r21 /* Are we storing the value we loaded? */ 1659 bbs r22, .Lcmpxchg32_nostore 1660 sw r0, r24 1661 1662 /* The following instruction is the start of the second cache line. */ 1663 /* Do slow mtspr here so the following "mf" waits less. */ 1664 { 1665 move sp, r27 1666 mtspr SPR_EX_CONTEXT_K_0, r28 1667 } 1668 mf 1669 1670 { 1671 move r0, r21 1672 sw ATOMIC_LOCK_REG_NAME, zero 1673 } 1674 iret 1675 1676 /* Duplicated code here in the case where we don't overlap "mf" */ 1677.Lcmpxchg32_nostore: 1678 { 1679 move r0, r21 1680 sw ATOMIC_LOCK_REG_NAME, zero 1681 } 1682 { 1683 move sp, r27 1684 mtspr SPR_EX_CONTEXT_K_0, r28 1685 } 1686 iret 1687 1688 /* 1689 * The locking code is the same for 32-bit cmpxchg/atomic_update, 1690 * and for 64-bit cmpxchg. We provide it as a macro and put 1691 * it into both versions. We can't share the code literally 1692 * since it depends on having the right branch-back address. 1693 */ 1694 .macro cmpxchg_lock, bitwidth 1695 1696 /* Lock; if we succeed, jump back up to the read-modify-write. */ 1697#ifdef CONFIG_SMP 1698 tns r21, ATOMIC_LOCK_REG_NAME 1699#else 1700 /* 1701 * Non-SMP preserves all the lock infrastructure, to keep the 1702 * code simpler for the interesting (SMP) case. However, we do 1703 * one small optimization here and in atomic_asm.S, which is 1704 * to fake out acquiring the actual lock in the atomic_lock table. 1705 */ 1706 movei r21, 0 1707#endif 1708 1709 /* Issue the slow SPR here while the tns result is in flight. */ 1710 mfspr r28, SPR_EX_CONTEXT_K_0 1711 1712 { 1713 addi r28, r28, 8 /* return to the instruction after the swint1 */ 1714 bzt r21, .Ldo_cmpxchg\bitwidth 1715 } 1716 /* 1717 * The preceding instruction is the last thing that must be 1718 * hot in the icache before we do the "tns" above. 1719 */ 1720 1721#ifdef CONFIG_SMP 1722 /* 1723 * We failed to acquire the tns lock on our first try. Now use 1724 * bounded exponential backoff to retry, like __atomic_spinlock(). 1725 */ 1726 { 1727 moveli r23, 2048 /* maximum backoff time in cycles */ 1728 moveli r25, 32 /* starting backoff time in cycles */ 1729 } 17301: mfspr r26, CYCLE_LOW /* get start point for this backoff */ 17312: mfspr r22, CYCLE_LOW /* test to see if we've backed off enough */ 1732 sub r22, r22, r26 1733 slt r22, r22, r25 1734 bbst r22, 2b 1735 { 1736 shli r25, r25, 1 /* double the backoff; retry the tns */ 1737 tns r21, ATOMIC_LOCK_REG_NAME 1738 } 1739 slt r26, r23, r25 /* is the proposed backoff too big? */ 1740 { 1741 mvnz r25, r26, r23 1742 bzt r21, .Ldo_cmpxchg\bitwidth 1743 } 1744 j 1b 1745#endif /* CONFIG_SMP */ 1746 .endm 1747 1748.Lcmpxchg32_tns: 1749 /* 1750 * This is the last instruction on the second cache line. 1751 * The nop here loads the second line, then we fall through 1752 * to the tns to load the third line before we take the lock. 1753 */ 1754 nop 1755 cmpxchg_lock 32 1756 1757 /* 1758 * This code is invoked from sys_cmpxchg after most of the 1759 * preconditions have been checked. We still need to check 1760 * that r0 is 8-byte aligned, since if it's not we won't 1761 * actually be atomic. However, ATOMIC_LOCK_REG has the atomic 1762 * lock pointer and r27/r28 have the saved SP/PC. 1763 * r23 is holding "r0 & 7" so we can test for alignment. 1764 * The compare value is in r2/r3; the new value is in r4/r5. 1765 * On return, we must put the old value in r0/r1. 1766 */ 1767 .align 64 1768.Lcmpxchg64: 1769 { 1770#if ATOMIC_LOCKS_FOUND_VIA_TABLE() 1771 s2a ATOMIC_LOCK_REG_NAME, r25, r21 1772#endif 1773 bzt r23, .Lcmpxchg64_tns 1774 } 1775 j .Lcmpxchg_badaddr 1776 1777.Ldo_cmpxchg64: 1778 { 1779 lw r21, r0 1780 addi r25, r0, 4 1781 } 1782 { 1783 lw r1, r25 1784 } 1785 seq r26, r21, r2 1786 { 1787 bz r26, .Lcmpxchg64_mismatch 1788 seq r26, r1, r3 1789 } 1790 { 1791 bz r26, .Lcmpxchg64_mismatch 1792 } 1793 sw r0, r4 1794 sw r25, r5 1795 1796 /* 1797 * The 32-bit path provides optimized "match" and "mismatch" 1798 * iret paths, but we don't have enough bundles in this cache line 1799 * to do that, so we just make even the "mismatch" path do an "mf". 1800 */ 1801.Lcmpxchg64_mismatch: 1802 { 1803 move sp, r27 1804 mtspr SPR_EX_CONTEXT_K_0, r28 1805 } 1806 mf 1807 { 1808 move r0, r21 1809 sw ATOMIC_LOCK_REG_NAME, zero 1810 } 1811 iret 1812 1813.Lcmpxchg64_tns: 1814 cmpxchg_lock 64 1815 1816 1817 /* 1818 * Reset sp and revector to sys_cmpxchg_badaddr(), which will 1819 * just raise the appropriate signal and exit. Doing it this 1820 * way means we don't have to duplicate the code in intvec.S's 1821 * int_hand macro that locates the top of the stack. 1822 */ 1823.Lcmpxchg_badaddr: 1824 { 1825 moveli TREG_SYSCALL_NR_NAME, __NR_cmpxchg_badaddr 1826 move sp, r27 1827 } 1828 j intvec_SWINT_1 1829 ENDPROC(sys_cmpxchg) 1830 ENTRY(__sys_cmpxchg_end) 1831 1832 1833/* The single-step support may need to read all the registers. */ 1834int_unalign: 1835 push_extra_callee_saves r0 1836 j do_trap 1837 1838/* Include .intrpt1 array of interrupt vectors */ 1839 .section ".intrpt1", "ax" 1840 1841#define op_handle_perf_interrupt bad_intr 1842#define op_handle_aux_perf_interrupt bad_intr 1843 1844#ifndef CONFIG_HARDWALL 1845#define do_hardwall_trap bad_intr 1846#endif 1847 1848 int_hand INT_ITLB_MISS, ITLB_MISS, \ 1849 do_page_fault, handle_interrupt_no_single_step 1850 int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr 1851 int_hand INT_ILL, ILL, do_trap, handle_ill 1852 int_hand INT_GPV, GPV, do_trap 1853 int_hand INT_SN_ACCESS, SN_ACCESS, do_trap 1854 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap 1855 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap 1856 int_hand INT_IDN_REFILL, IDN_REFILL, bad_intr 1857 int_hand INT_UDN_REFILL, UDN_REFILL, bad_intr 1858 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr 1859 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr 1860 int_hand INT_SWINT_3, SWINT_3, do_trap 1861 int_hand INT_SWINT_2, SWINT_2, do_trap 1862 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall 1863 int_hand INT_SWINT_0, SWINT_0, do_trap 1864 int_hand INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign 1865 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault 1866 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault 1867 int_hand INT_DMATLB_MISS, DMATLB_MISS, do_page_fault 1868 int_hand INT_DMATLB_ACCESS, DMATLB_ACCESS, do_page_fault 1869 int_hand INT_SNITLB_MISS, SNITLB_MISS, do_page_fault 1870 int_hand INT_SN_NOTIFY, SN_NOTIFY, bad_intr 1871 int_hand INT_SN_FIREWALL, SN_FIREWALL, do_hardwall_trap 1872 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr 1873 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap 1874 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt 1875 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr 1876 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr 1877 int_hand INT_DMA_NOTIFY, DMA_NOTIFY, bad_intr 1878 int_hand INT_IDN_CA, IDN_CA, bad_intr 1879 int_hand INT_UDN_CA, UDN_CA, bad_intr 1880 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr 1881 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr 1882 int_hand INT_PERF_COUNT, PERF_COUNT, \ 1883 op_handle_perf_interrupt, handle_nmi 1884 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr 1885#if CONFIG_KERNEL_PL == 2 1886 dc_dispatch INT_INTCTRL_2, INTCTRL_2 1887 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr 1888#else 1889 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr 1890 dc_dispatch INT_INTCTRL_1, INTCTRL_1 1891#endif 1892 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr 1893 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \ 1894 hv_message_intr 1895 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, \ 1896 tile_dev_intr 1897 int_hand INT_I_ASID, I_ASID, bad_intr 1898 int_hand INT_D_ASID, D_ASID, bad_intr 1899 int_hand INT_DMATLB_MISS_DWNCL, DMATLB_MISS_DWNCL, \ 1900 do_page_fault 1901 int_hand INT_SNITLB_MISS_DWNCL, SNITLB_MISS_DWNCL, \ 1902 do_page_fault 1903 int_hand INT_DMATLB_ACCESS_DWNCL, DMATLB_ACCESS_DWNCL, \ 1904 do_page_fault 1905 int_hand INT_SN_CPL, SN_CPL, bad_intr 1906 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap 1907#if CHIP_HAS_AUX_PERF_COUNTERS() 1908 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \ 1909 op_handle_aux_perf_interrupt, handle_nmi 1910#endif 1911 1912 /* Synthetic interrupt delivered only by the simulator */ 1913 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint 1914