1 /* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _ASM_TILE_CACHE_H 16 #define _ASM_TILE_CACHE_H 17 18 #include <arch/chip.h> 19 20 /* bytes per L1 data cache line */ 21 #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE() 22 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 23 24 /* bytes per L2 cache line */ 25 #define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE() 26 #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) 27 #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) 28 29 /* 30 * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN. 31 */ 32 #ifndef __tilegx__ 33 #define ARCH_DMA_MINALIGN L2_CACHE_BYTES 34 #endif 35 36 /* use the cache line size for the L2, which is where it counts */ 37 #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT 38 #define SMP_CACHE_BYTES L2_CACHE_BYTES 39 #define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT 40 #define INTERNODE_CACHE_BYTES L2_CACHE_BYTES 41 42 /* Group together read-mostly things to avoid cache false sharing */ 43 #define __read_mostly __attribute__((__section__(".data..read_mostly"))) 44 45 /* 46 * Attribute for data that is kept read/write coherent until the end of 47 * initialization, then bumped to read/only incoherent for performance. 48 */ 49 #define __write_once __attribute__((__section__(".w1data"))) 50 51 #endif /* _ASM_TILE_CACHE_H */ 52