1 /*
2 * SH7723 Setup
3 *
4 * Copyright (C) 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/mm.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/r8a66597.h>
17 #include <linux/sh_timer.h>
18 #include <linux/io.h>
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
21 #include <cpu/sh7723.h>
22
23 /* Serial */
24 static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000,
26 .port_reg = 0xa4050160,
27 .flags = UPF_BOOT_AUTOCONF,
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 .scbrr_algo_id = SCBRR_ALGO_2,
30 .type = PORT_SCIF,
31 .irqs = { 80, 80, 80, 80 },
32 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
33 };
34
35 static struct platform_device scif0_device = {
36 .name = "sh-sci",
37 .id = 0,
38 .dev = {
39 .platform_data = &scif0_platform_data,
40 },
41 };
42
43 static struct plat_sci_port scif1_platform_data = {
44 .mapbase = 0xffe10000,
45 .port_reg = SCIx_NOT_SUPPORTED,
46 .flags = UPF_BOOT_AUTOCONF,
47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
48 .scbrr_algo_id = SCBRR_ALGO_2,
49 .type = PORT_SCIF,
50 .irqs = { 81, 81, 81, 81 },
51 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
52 };
53
54 static struct platform_device scif1_device = {
55 .name = "sh-sci",
56 .id = 1,
57 .dev = {
58 .platform_data = &scif1_platform_data,
59 },
60 };
61
62 static struct plat_sci_port scif2_platform_data = {
63 .mapbase = 0xffe20000,
64 .port_reg = SCIx_NOT_SUPPORTED,
65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF,
69 .irqs = { 82, 82, 82, 82 },
70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
71 };
72
73 static struct platform_device scif2_device = {
74 .name = "sh-sci",
75 .id = 2,
76 .dev = {
77 .platform_data = &scif2_platform_data,
78 },
79 };
80
81 static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xa4e30000,
83 .flags = UPF_BOOT_AUTOCONF,
84 .port_reg = SCIx_NOT_SUPPORTED,
85 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
86 .scbrr_algo_id = SCBRR_ALGO_3,
87 .type = PORT_SCIFA,
88 .irqs = { 56, 56, 56, 56 },
89 };
90
91 static struct platform_device scif3_device = {
92 .name = "sh-sci",
93 .id = 3,
94 .dev = {
95 .platform_data = &scif3_platform_data,
96 },
97 };
98
99 static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xa4e40000,
101 .port_reg = SCIx_NOT_SUPPORTED,
102 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
104 .scbrr_algo_id = SCBRR_ALGO_3,
105 .type = PORT_SCIFA,
106 .irqs = { 88, 88, 88, 88 },
107 };
108
109 static struct platform_device scif4_device = {
110 .name = "sh-sci",
111 .id = 4,
112 .dev = {
113 .platform_data = &scif4_platform_data,
114 },
115 };
116
117 static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xa4e50000,
119 .port_reg = SCIx_NOT_SUPPORTED,
120 .flags = UPF_BOOT_AUTOCONF,
121 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
122 .scbrr_algo_id = SCBRR_ALGO_3,
123 .type = PORT_SCIFA,
124 .irqs = { 109, 109, 109, 109 },
125 };
126
127 static struct platform_device scif5_device = {
128 .name = "sh-sci",
129 .id = 5,
130 .dev = {
131 .platform_data = &scif5_platform_data,
132 },
133 };
134
135 static struct uio_info vpu_platform_data = {
136 .name = "VPU5",
137 .version = "0",
138 .irq = 60,
139 };
140
141 static struct resource vpu_resources[] = {
142 [0] = {
143 .name = "VPU",
144 .start = 0xfe900000,
145 .end = 0xfe902807,
146 .flags = IORESOURCE_MEM,
147 },
148 [1] = {
149 /* place holder for contiguous memory */
150 },
151 };
152
153 static struct platform_device vpu_device = {
154 .name = "uio_pdrv_genirq",
155 .id = 0,
156 .dev = {
157 .platform_data = &vpu_platform_data,
158 },
159 .resource = vpu_resources,
160 .num_resources = ARRAY_SIZE(vpu_resources),
161 };
162
163 static struct uio_info veu0_platform_data = {
164 .name = "VEU2H",
165 .version = "0",
166 .irq = 54,
167 };
168
169 static struct resource veu0_resources[] = {
170 [0] = {
171 .name = "VEU2H0",
172 .start = 0xfe920000,
173 .end = 0xfe92027b,
174 .flags = IORESOURCE_MEM,
175 },
176 [1] = {
177 /* place holder for contiguous memory */
178 },
179 };
180
181 static struct platform_device veu0_device = {
182 .name = "uio_pdrv_genirq",
183 .id = 1,
184 .dev = {
185 .platform_data = &veu0_platform_data,
186 },
187 .resource = veu0_resources,
188 .num_resources = ARRAY_SIZE(veu0_resources),
189 };
190
191 static struct uio_info veu1_platform_data = {
192 .name = "VEU2H",
193 .version = "0",
194 .irq = 27,
195 };
196
197 static struct resource veu1_resources[] = {
198 [0] = {
199 .name = "VEU2H1",
200 .start = 0xfe924000,
201 .end = 0xfe92427b,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 /* place holder for contiguous memory */
206 },
207 };
208
209 static struct platform_device veu1_device = {
210 .name = "uio_pdrv_genirq",
211 .id = 2,
212 .dev = {
213 .platform_data = &veu1_platform_data,
214 },
215 .resource = veu1_resources,
216 .num_resources = ARRAY_SIZE(veu1_resources),
217 };
218
219 static struct sh_timer_config cmt_platform_data = {
220 .channel_offset = 0x60,
221 .timer_bit = 5,
222 .clockevent_rating = 125,
223 .clocksource_rating = 125,
224 };
225
226 static struct resource cmt_resources[] = {
227 [0] = {
228 .start = 0x044a0060,
229 .end = 0x044a006b,
230 .flags = IORESOURCE_MEM,
231 },
232 [1] = {
233 .start = 104,
234 .flags = IORESOURCE_IRQ,
235 },
236 };
237
238 static struct platform_device cmt_device = {
239 .name = "sh_cmt",
240 .id = 0,
241 .dev = {
242 .platform_data = &cmt_platform_data,
243 },
244 .resource = cmt_resources,
245 .num_resources = ARRAY_SIZE(cmt_resources),
246 };
247
248 static struct sh_timer_config tmu0_platform_data = {
249 .channel_offset = 0x04,
250 .timer_bit = 0,
251 .clockevent_rating = 200,
252 };
253
254 static struct resource tmu0_resources[] = {
255 [0] = {
256 .start = 0xffd80008,
257 .end = 0xffd80013,
258 .flags = IORESOURCE_MEM,
259 },
260 [1] = {
261 .start = 16,
262 .flags = IORESOURCE_IRQ,
263 },
264 };
265
266 static struct platform_device tmu0_device = {
267 .name = "sh_tmu",
268 .id = 0,
269 .dev = {
270 .platform_data = &tmu0_platform_data,
271 },
272 .resource = tmu0_resources,
273 .num_resources = ARRAY_SIZE(tmu0_resources),
274 };
275
276 static struct sh_timer_config tmu1_platform_data = {
277 .channel_offset = 0x10,
278 .timer_bit = 1,
279 .clocksource_rating = 200,
280 };
281
282 static struct resource tmu1_resources[] = {
283 [0] = {
284 .start = 0xffd80014,
285 .end = 0xffd8001f,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = 17,
290 .flags = IORESOURCE_IRQ,
291 },
292 };
293
294 static struct platform_device tmu1_device = {
295 .name = "sh_tmu",
296 .id = 1,
297 .dev = {
298 .platform_data = &tmu1_platform_data,
299 },
300 .resource = tmu1_resources,
301 .num_resources = ARRAY_SIZE(tmu1_resources),
302 };
303
304 static struct sh_timer_config tmu2_platform_data = {
305 .channel_offset = 0x1c,
306 .timer_bit = 2,
307 };
308
309 static struct resource tmu2_resources[] = {
310 [0] = {
311 .start = 0xffd80020,
312 .end = 0xffd8002b,
313 .flags = IORESOURCE_MEM,
314 },
315 [1] = {
316 .start = 18,
317 .flags = IORESOURCE_IRQ,
318 },
319 };
320
321 static struct platform_device tmu2_device = {
322 .name = "sh_tmu",
323 .id = 2,
324 .dev = {
325 .platform_data = &tmu2_platform_data,
326 },
327 .resource = tmu2_resources,
328 .num_resources = ARRAY_SIZE(tmu2_resources),
329 };
330
331 static struct sh_timer_config tmu3_platform_data = {
332 .channel_offset = 0x04,
333 .timer_bit = 0,
334 };
335
336 static struct resource tmu3_resources[] = {
337 [0] = {
338 .start = 0xffd90008,
339 .end = 0xffd90013,
340 .flags = IORESOURCE_MEM,
341 },
342 [1] = {
343 .start = 57,
344 .flags = IORESOURCE_IRQ,
345 },
346 };
347
348 static struct platform_device tmu3_device = {
349 .name = "sh_tmu",
350 .id = 3,
351 .dev = {
352 .platform_data = &tmu3_platform_data,
353 },
354 .resource = tmu3_resources,
355 .num_resources = ARRAY_SIZE(tmu3_resources),
356 };
357
358 static struct sh_timer_config tmu4_platform_data = {
359 .channel_offset = 0x10,
360 .timer_bit = 1,
361 };
362
363 static struct resource tmu4_resources[] = {
364 [0] = {
365 .start = 0xffd90014,
366 .end = 0xffd9001f,
367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
370 .start = 58,
371 .flags = IORESOURCE_IRQ,
372 },
373 };
374
375 static struct platform_device tmu4_device = {
376 .name = "sh_tmu",
377 .id = 4,
378 .dev = {
379 .platform_data = &tmu4_platform_data,
380 },
381 .resource = tmu4_resources,
382 .num_resources = ARRAY_SIZE(tmu4_resources),
383 };
384
385 static struct sh_timer_config tmu5_platform_data = {
386 .channel_offset = 0x1c,
387 .timer_bit = 2,
388 };
389
390 static struct resource tmu5_resources[] = {
391 [0] = {
392 .start = 0xffd90020,
393 .end = 0xffd9002b,
394 .flags = IORESOURCE_MEM,
395 },
396 [1] = {
397 .start = 57,
398 .flags = IORESOURCE_IRQ,
399 },
400 };
401
402 static struct platform_device tmu5_device = {
403 .name = "sh_tmu",
404 .id = 5,
405 .dev = {
406 .platform_data = &tmu5_platform_data,
407 },
408 .resource = tmu5_resources,
409 .num_resources = ARRAY_SIZE(tmu5_resources),
410 };
411
412 static struct resource rtc_resources[] = {
413 [0] = {
414 .start = 0xa465fec0,
415 .end = 0xa465fec0 + 0x58 - 1,
416 .flags = IORESOURCE_IO,
417 },
418 [1] = {
419 /* Period IRQ */
420 .start = 69,
421 .flags = IORESOURCE_IRQ,
422 },
423 [2] = {
424 /* Carry IRQ */
425 .start = 70,
426 .flags = IORESOURCE_IRQ,
427 },
428 [3] = {
429 /* Alarm IRQ */
430 .start = 68,
431 .flags = IORESOURCE_IRQ,
432 },
433 };
434
435 static struct platform_device rtc_device = {
436 .name = "sh-rtc",
437 .id = -1,
438 .num_resources = ARRAY_SIZE(rtc_resources),
439 .resource = rtc_resources,
440 };
441
442 static struct r8a66597_platdata r8a66597_data = {
443 .on_chip = 1,
444 };
445
446 static struct resource sh7723_usb_host_resources[] = {
447 [0] = {
448 .start = 0xa4d80000,
449 .end = 0xa4d800ff,
450 .flags = IORESOURCE_MEM,
451 },
452 [1] = {
453 .start = 65,
454 .end = 65,
455 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
456 },
457 };
458
459 static struct platform_device sh7723_usb_host_device = {
460 .name = "r8a66597_hcd",
461 .id = 0,
462 .dev = {
463 .dma_mask = NULL, /* not use dma */
464 .coherent_dma_mask = 0xffffffff,
465 .platform_data = &r8a66597_data,
466 },
467 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
468 .resource = sh7723_usb_host_resources,
469 };
470
471 static struct resource iic_resources[] = {
472 [0] = {
473 .name = "IIC",
474 .start = 0x04470000,
475 .end = 0x04470017,
476 .flags = IORESOURCE_MEM,
477 },
478 [1] = {
479 .start = 96,
480 .end = 99,
481 .flags = IORESOURCE_IRQ,
482 },
483 };
484
485 static struct platform_device iic_device = {
486 .name = "i2c-sh_mobile",
487 .id = 0, /* "i2c0" clock */
488 .num_resources = ARRAY_SIZE(iic_resources),
489 .resource = iic_resources,
490 };
491
492 static struct platform_device *sh7723_devices[] __initdata = {
493 &scif0_device,
494 &scif1_device,
495 &scif2_device,
496 &scif3_device,
497 &scif4_device,
498 &scif5_device,
499 &cmt_device,
500 &tmu0_device,
501 &tmu1_device,
502 &tmu2_device,
503 &tmu3_device,
504 &tmu4_device,
505 &tmu5_device,
506 &rtc_device,
507 &iic_device,
508 &sh7723_usb_host_device,
509 &vpu_device,
510 &veu0_device,
511 &veu1_device,
512 };
513
sh7723_devices_setup(void)514 static int __init sh7723_devices_setup(void)
515 {
516 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
517 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
518 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
519
520 return platform_add_devices(sh7723_devices,
521 ARRAY_SIZE(sh7723_devices));
522 }
523 arch_initcall(sh7723_devices_setup);
524
525 static struct platform_device *sh7723_early_devices[] __initdata = {
526 &scif0_device,
527 &scif1_device,
528 &scif2_device,
529 &scif3_device,
530 &scif4_device,
531 &scif5_device,
532 &cmt_device,
533 &tmu0_device,
534 &tmu1_device,
535 &tmu2_device,
536 &tmu3_device,
537 &tmu4_device,
538 &tmu5_device,
539 };
540
plat_early_device_setup(void)541 void __init plat_early_device_setup(void)
542 {
543 early_platform_add_devices(sh7723_early_devices,
544 ARRAY_SIZE(sh7723_early_devices));
545 }
546
547 #define RAMCR_CACHE_L2FC 0x0002
548 #define RAMCR_CACHE_L2E 0x0001
549 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
550
l2_cache_init(void)551 void l2_cache_init(void)
552 {
553 /* Enable L2 cache */
554 __raw_writel(L2_CACHE_ENABLE, RAMCR);
555 }
556
557 enum {
558 UNUSED=0,
559 ENABLED,
560 DISABLED,
561
562 /* interrupt sources */
563 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
564 HUDI,
565 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
566 _2DG_TRI,_2DG_INI,_2DG_CEI,
567 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
568 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
569 SCIFA_SCIFA0,
570 VPU_VPUI,
571 TPU_TPUI,
572 ADC_ADI,
573 USB_USI0,
574 RTC_ATI,RTC_PRI,RTC_CUI,
575 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
576 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
577 KEYSC_KEYI,
578 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
579 MSIOF_MSIOFI0,MSIOF_MSIOFI1,
580 SCIFA_SCIFA1,
581 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
582 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
583 CMT_CMTI,
584 TSIF_TSIFI,
585 SIU_SIUI,
586 SCIFA_SCIFA2,
587 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
588 IRDA_IRDAI,
589 ATAPI_ATAPII,
590 VEU2H1_VEU2HI,
591 LCDC_LCDCI,
592 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
593
594 /* interrupt groups */
595 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
596 SDHI1, RTC, DMAC1B, SDHI0,
597 };
598
599 static struct intc_vect vectors[] __initdata = {
600 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
601 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
602 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
603 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
604
605 INTC_VECT(DMAC1A_DEI0,0x700),
606 INTC_VECT(DMAC1A_DEI1,0x720),
607 INTC_VECT(DMAC1A_DEI2,0x740),
608 INTC_VECT(DMAC1A_DEI3,0x760),
609
610 INTC_VECT(_2DG_TRI, 0x780),
611 INTC_VECT(_2DG_INI, 0x7A0),
612 INTC_VECT(_2DG_CEI, 0x7C0),
613
614 INTC_VECT(DMAC0A_DEI0,0x800),
615 INTC_VECT(DMAC0A_DEI1,0x820),
616 INTC_VECT(DMAC0A_DEI2,0x840),
617 INTC_VECT(DMAC0A_DEI3,0x860),
618
619 INTC_VECT(VIO_CEUI,0x880),
620 INTC_VECT(VIO_BEUI,0x8A0),
621 INTC_VECT(VIO_VEU2HI,0x8C0),
622 INTC_VECT(VIO_VOUI,0x8E0),
623
624 INTC_VECT(SCIFA_SCIFA0,0x900),
625 INTC_VECT(VPU_VPUI,0x980),
626 INTC_VECT(TPU_TPUI,0x9A0),
627 INTC_VECT(ADC_ADI,0x9E0),
628 INTC_VECT(USB_USI0,0xA20),
629
630 INTC_VECT(RTC_ATI,0xA80),
631 INTC_VECT(RTC_PRI,0xAA0),
632 INTC_VECT(RTC_CUI,0xAC0),
633
634 INTC_VECT(DMAC1B_DEI4,0xB00),
635 INTC_VECT(DMAC1B_DEI5,0xB20),
636 INTC_VECT(DMAC1B_DADERR,0xB40),
637
638 INTC_VECT(DMAC0B_DEI4,0xB80),
639 INTC_VECT(DMAC0B_DEI5,0xBA0),
640 INTC_VECT(DMAC0B_DADERR,0xBC0),
641
642 INTC_VECT(KEYSC_KEYI,0xBE0),
643 INTC_VECT(SCIF_SCIF0,0xC00),
644 INTC_VECT(SCIF_SCIF1,0xC20),
645 INTC_VECT(SCIF_SCIF2,0xC40),
646 INTC_VECT(MSIOF_MSIOFI0,0xC80),
647 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
648 INTC_VECT(SCIFA_SCIFA1,0xD00),
649
650 INTC_VECT(FLCTL_FLSTEI,0xD80),
651 INTC_VECT(FLCTL_FLTENDI,0xDA0),
652 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
653 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
654
655 INTC_VECT(I2C_ALI,0xE00),
656 INTC_VECT(I2C_TACKI,0xE20),
657 INTC_VECT(I2C_WAITI,0xE40),
658 INTC_VECT(I2C_DTEI,0xE60),
659
660 INTC_VECT(SDHI0, 0xE80),
661 INTC_VECT(SDHI0, 0xEA0),
662 INTC_VECT(SDHI0, 0xEC0),
663
664 INTC_VECT(CMT_CMTI,0xF00),
665 INTC_VECT(TSIF_TSIFI,0xF20),
666 INTC_VECT(SIU_SIUI,0xF80),
667 INTC_VECT(SCIFA_SCIFA2,0xFA0),
668
669 INTC_VECT(TMU0_TUNI0,0x400),
670 INTC_VECT(TMU0_TUNI1,0x420),
671 INTC_VECT(TMU0_TUNI2,0x440),
672
673 INTC_VECT(IRDA_IRDAI,0x480),
674 INTC_VECT(ATAPI_ATAPII,0x4A0),
675
676 INTC_VECT(SDHI1, 0x4E0),
677 INTC_VECT(SDHI1, 0x500),
678 INTC_VECT(SDHI1, 0x520),
679
680 INTC_VECT(VEU2H1_VEU2HI,0x560),
681 INTC_VECT(LCDC_LCDCI,0x580),
682
683 INTC_VECT(TMU1_TUNI0,0x920),
684 INTC_VECT(TMU1_TUNI1,0x940),
685 INTC_VECT(TMU1_TUNI2,0x960),
686
687 };
688
689 static struct intc_group groups[] __initdata = {
690 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
691 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
692 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
693 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
694 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
695 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
696 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
697 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
698 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
699 };
700
701 static struct intc_mask_reg mask_registers[] __initdata = {
702 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
703 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
704 0, ENABLED, ENABLED, ENABLED } },
705 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
706 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
707 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
708 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
709 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
710 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
711 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
712 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
713 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
714 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
715 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
716 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
717 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
718 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
719 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
720 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
721 { 0, ENABLED, ENABLED, ENABLED,
722 0, 0, SCIFA_SCIFA2, SIU_SIUI } },
723 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
724 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
725 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
726 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
727 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
728 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
729 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
730 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
731 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
732 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
733 };
734
735 static struct intc_prio_reg prio_registers[] __initdata = {
736 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
737 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
738 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
739 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
740 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
741 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
742 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
743 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
744 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
745 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
746 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
747 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
748 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
749 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
750 };
751
752 static struct intc_sense_reg sense_registers[] __initdata = {
753 { 0xa414001c, 16, 2, /* ICR1 */
754 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
755 };
756
757 static struct intc_mask_reg ack_registers[] __initdata = {
758 { 0xa4140024, 0, 8, /* INTREQ00 */
759 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
760 };
761
762 static struct intc_desc intc_desc __initdata = {
763 .name = "sh7723",
764 .force_enable = ENABLED,
765 .force_disable = DISABLED,
766 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
767 prio_registers, sense_registers, ack_registers),
768 };
769
plat_irq_setup(void)770 void __init plat_irq_setup(void)
771 {
772 register_intc_controller(&intc_desc);
773 }
774