1 #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H 2 #define __ASM_SH_CPU_SH4_DMA_SH7780_H 3 4 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 5 defined(CONFIG_CPU_SUBTYPE_SH7730) 6 #define DMTE0_IRQ 48 7 #define DMTE4_IRQ 76 8 #define DMAE0_IRQ 78 /* DMA Error IRQ*/ 9 #define SH_DMAC_BASE0 0xFE008020 10 #define SH_DMARS_BASE0 0xFE009000 11 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 12 #define DMTE0_IRQ 48 13 #define DMTE4_IRQ 76 14 #define DMAE0_IRQ 78 /* DMA Error IRQ*/ 15 #define SH_DMAC_BASE0 0xFE008020 16 #define SH_DMARS_BASE0 0xFE009000 17 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 18 defined(CONFIG_CPU_SUBTYPE_SH7764) 19 #define DMTE0_IRQ 34 20 #define DMTE4_IRQ 44 21 #define DMAE0_IRQ 38 22 #define SH_DMAC_BASE0 0xFF608020 23 #define SH_DMARS_BASE0 0xFF609000 24 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) 25 #define DMTE0_IRQ 48 /* DMAC0A*/ 26 #define DMTE4_IRQ 76 /* DMAC0B */ 27 #define DMTE6_IRQ 40 28 #define DMTE8_IRQ 42 /* DMAC1A */ 29 #define DMTE9_IRQ 43 30 #define DMTE10_IRQ 72 /* DMAC1B */ 31 #define DMTE11_IRQ 73 32 #define DMAE0_IRQ 78 /* DMA Error IRQ*/ 33 #define DMAE1_IRQ 74 /* DMA Error IRQ*/ 34 #define SH_DMAC_BASE0 0xFE008020 35 #define SH_DMAC_BASE1 0xFDC08020 36 #define SH_DMARS_BASE0 0xFDC09000 37 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) 38 #define DMTE0_IRQ 48 /* DMAC0A*/ 39 #define DMTE4_IRQ 76 /* DMAC0B */ 40 #define DMTE6_IRQ 40 41 #define DMTE8_IRQ 42 /* DMAC1A */ 42 #define DMTE9_IRQ 43 43 #define DMTE10_IRQ 72 /* DMAC1B */ 44 #define DMTE11_IRQ 73 45 #define DMAE0_IRQ 78 /* DMA Error IRQ*/ 46 #define DMAE1_IRQ 74 /* DMA Error IRQ*/ 47 #define SH_DMAC_BASE0 0xFE008020 48 #define SH_DMAC_BASE1 0xFDC08020 49 #define SH_DMARS_BASE0 0xFE009000 50 #define SH_DMARS_BASE1 0xFDC09000 51 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 52 #define DMTE0_IRQ 34 53 #define DMTE4_IRQ 44 54 #define DMTE6_IRQ 46 55 #define DMTE8_IRQ 92 56 #define DMTE9_IRQ 93 57 #define DMTE10_IRQ 94 58 #define DMTE11_IRQ 95 59 #define DMAE0_IRQ 38 /* DMA Error IRQ */ 60 #define SH_DMAC_BASE0 0xFC808020 61 #define SH_DMAC_BASE1 0xFC818020 62 #define SH_DMARS_BASE0 0xFC809000 63 #else /* SH7785 */ 64 #define DMTE0_IRQ 33 65 #define DMTE4_IRQ 37 66 #define DMTE6_IRQ 52 67 #define DMTE8_IRQ 54 68 #define DMTE9_IRQ 55 69 #define DMTE10_IRQ 56 70 #define DMTE11_IRQ 57 71 #define DMAE0_IRQ 39 /* DMA Error IRQ0 */ 72 #define DMAE1_IRQ 58 /* DMA Error IRQ1 */ 73 #define SH_DMAC_BASE0 0xFC808020 74 #define SH_DMAC_BASE1 0xFCC08020 75 #define SH_DMARS_BASE0 0xFC809000 76 #endif 77 78 #define REQ_HE 0x000000C0 79 #define REQ_H 0x00000080 80 #define REQ_LE 0x00000040 81 #define TM_BURST 0x00000020 82 83 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ 84