1 /* 2 * Copyright 2001 Mike Corrigan, IBM Corp 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 #include <linux/types.h> 10 #include <linux/threads.h> 11 #include <linux/bitops.h> 12 #include <asm/processor.h> 13 #include <asm/ptrace.h> 14 #include <asm/abs_addr.h> 15 #include <asm/lppaca.h> 16 #include <asm/paca.h> 17 #include <asm/iseries/lpar_map.h> 18 #include <asm/iseries/it_lp_queue.h> 19 #include <asm/iseries/alpaca.h> 20 21 #include "naca.h" 22 #include "vpd_areas.h" 23 #include "spcomm_area.h" 24 #include "ipl_parms.h" 25 #include "processor_vpd.h" 26 #include "release_data.h" 27 #include "it_exp_vpd_panel.h" 28 #include "it_lp_naca.h" 29 30 /* The HvReleaseData is the root of the information shared between 31 * the hypervisor and Linux. 32 */ 33 const struct HvReleaseData hvReleaseData = { 34 .xDesc = 0xc8a5d9c4, /* "HvRD" ebcdic */ 35 .xSize = sizeof(struct HvReleaseData), 36 .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas), 37 .xSlicNacaAddr = &naca, /* 64-bit Naca address */ 38 .xMsNucDataOffset = LPARMAP_PHYS, 39 .xFlags = HVREL_TAGSINACTIVE /* tags inactive */ 40 /* 64 bit */ 41 /* shared processors */ 42 /* HMT allowed */ 43 | 6, /* TEMP: This allows non-GA driver */ 44 .xVrmIndex = 4, /* We are v5r2m0 */ 45 .xMinSupportedPlicVrmIndex = 3, /* v5r1m0 */ 46 .xMinCompatablePlicVrmIndex = 3, /* v5r1m0 */ 47 .xVrmName = { 0xd3, 0x89, 0x95, 0xa4, /* "Linux 2.4.64" ebcdic */ 48 0xa7, 0x40, 0xf2, 0x4b, 49 0xf4, 0x4b, 0xf6, 0xf4 }, 50 }; 51 52 /* 53 * The NACA. The first dword of the naca is required by the iSeries 54 * hypervisor to point to itVpdAreas. The hypervisor finds the NACA 55 * through the pointer in hvReleaseData. 56 */ 57 struct naca_struct naca = { 58 .xItVpdAreas = &itVpdAreas, 59 .xRamDisk = 0, 60 .xRamDiskSize = 0, 61 }; 62 63 struct ItLpRegSave { 64 u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003 65 u16 xSize; // Size of this class 004-005 66 u8 xInUse; // Area is live 006-007 67 u8 xRsvd1[9]; // Reserved 007-00F 68 69 u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F 70 u32 xCTRL; // Control Register 170-173 71 u32 xDEC; // Decrementer 174-177 72 u32 xFPSCR; // FP Status and Control Reg 178-17B 73 u32 xPVR; // Processor Version Number 17C-17F 74 75 u64 xMMCR0; // Monitor Mode Control Reg 0 180-187 76 u32 xPMC1; // Perf Monitor Counter 1 188-18B 77 u32 xPMC2; // Perf Monitor Counter 2 18C-18F 78 u32 xPMC3; // Perf Monitor Counter 3 190-193 79 u32 xPMC4; // Perf Monitor Counter 4 194-197 80 u32 xPIR; // Processor ID Reg 198-19B 81 82 u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F 83 u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3 84 u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7 85 u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB 86 u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF 87 u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3 88 u32 xTSC; // Thread Switch Control 1B4-1B7 89 u32 xTST; // Thread Switch Timeout 1B8-1BB 90 u32 xRsvd; // Reserved 1BC-1BF 91 92 u64 xACCR; // Address Compare Control Reg 1C0-1C7 93 u64 xIMR; // Instruction Match Register 1C8-1CF 94 u64 xSDR1; // Storage Description Reg 1 1D0-1D7 95 u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF 96 u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7 97 u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF 98 u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7 99 u64 xTB; // Time Base Register 1F8-1FF 100 101 u64 xFPR[32]; // Floating Point Registers 200-2FF 102 103 u64 xMSR; // Machine State Register 300-307 104 u64 xNIA; // Next Instruction Address 308-30F 105 106 u64 xDABR; // Data Address Breakpoint Reg 310-317 107 u64 xIABR; // Inst Address Breakpoint Reg 318-31F 108 109 u64 xHID0; // HW Implementation Dependent0 320-327 110 111 u64 xHID4; // HW Implementation Dependent4 328-32F 112 u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337 113 u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F 114 u64 xSDAR; // Sample Data Address Register 340-347 115 u64 xSIAR; // Sample Inst Address Register 348-34F 116 117 u8 xRsvd3[176]; // Reserved 350-3FF 118 }; 119 120 extern void system_reset_iSeries(void); 121 extern void machine_check_iSeries(void); 122 extern void data_access_iSeries(void); 123 extern void instruction_access_iSeries(void); 124 extern void hardware_interrupt_iSeries(void); 125 extern void alignment_iSeries(void); 126 extern void program_check_iSeries(void); 127 extern void fp_unavailable_iSeries(void); 128 extern void decrementer_iSeries(void); 129 extern void trap_0a_iSeries(void); 130 extern void trap_0b_iSeries(void); 131 extern void system_call_iSeries(void); 132 extern void single_step_iSeries(void); 133 extern void trap_0e_iSeries(void); 134 extern void performance_monitor_iSeries(void); 135 extern void data_access_slb_iSeries(void); 136 extern void instruction_access_slb_iSeries(void); 137 138 struct ItLpNaca itLpNaca = { 139 .xDesc = 0xd397d581, /* "LpNa" ebcdic */ 140 .xSize = 0x0400, /* size of ItLpNaca */ 141 .xIntHdlrOffset = 0x0300, /* offset to int array */ 142 .xMaxIntHdlrEntries = 19, /* # ents */ 143 .xPrimaryLpIndex = 0, /* Part # of primary */ 144 .xServiceLpIndex = 0, /* Part # of serv */ 145 .xLpIndex = 0, /* Part # of me */ 146 .xMaxLpQueues = 0, /* # of LP queues */ 147 .xLpQueueOffset = 0x100, /* offset of start of LP queues */ 148 .xPirEnvironMode = 0, /* Piranha stuff */ 149 .xPirConsoleMode = 0, 150 .xPirDasdMode = 0, 151 .flags = 0, 152 .xSpVpdFormat = 0, 153 .xIntProcRatio = 0, 154 .xPlicVrmIndex = 0, /* VRM index of PLIC */ 155 .xMinSupportedSlicVrmInd = 0, /* min supported SLIC */ 156 .xMinCompatableSlicVrmInd = 0, /* min compat SLIC */ 157 .xLoadAreaAddr = 0, /* 64-bit addr of load area */ 158 .xLoadAreaChunks = 0, /* chunks for load area */ 159 .xPaseSysCallCRMask = 0, /* PASE mask */ 160 .xSlicSegmentTablePtr = 0, /* seg table */ 161 .xOldLpQueue = { 0 }, /* Old LP Queue */ 162 .xInterruptHdlr = { 163 (u64)system_reset_iSeries, /* 0x100 System Reset */ 164 (u64)machine_check_iSeries, /* 0x200 Machine Check */ 165 (u64)data_access_iSeries, /* 0x300 Data Access */ 166 (u64)instruction_access_iSeries, /* 0x400 Instruction Access */ 167 (u64)hardware_interrupt_iSeries, /* 0x500 External */ 168 (u64)alignment_iSeries, /* 0x600 Alignment */ 169 (u64)program_check_iSeries, /* 0x700 Program Check */ 170 (u64)fp_unavailable_iSeries, /* 0x800 FP Unavailable */ 171 (u64)decrementer_iSeries, /* 0x900 Decrementer */ 172 (u64)trap_0a_iSeries, /* 0xa00 Trap 0A */ 173 (u64)trap_0b_iSeries, /* 0xb00 Trap 0B */ 174 (u64)system_call_iSeries, /* 0xc00 System Call */ 175 (u64)single_step_iSeries, /* 0xd00 Single Step */ 176 (u64)trap_0e_iSeries, /* 0xe00 Trap 0E */ 177 (u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */ 178 0, /* int 0x1000 */ 179 0, /* int 0x1010 */ 180 0, /* int 0x1020 CPU ctls */ 181 (u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */ 182 (u64)data_access_slb_iSeries, /* 0x380 D-SLB */ 183 (u64)instruction_access_slb_iSeries /* 0x480 I-SLB */ 184 } 185 }; 186 187 /* May be filled in by the hypervisor so cannot end up in the BSS */ 188 static struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data"))); 189 190 /* May be filled in by the hypervisor so cannot end up in the BSS */ 191 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data"))); 192 193 #define maxPhysicalProcessors 32 194 195 struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = { 196 { 197 .xInstCacheOperandSize = 32, 198 .xDataCacheOperandSize = 32, 199 .xProcFreq = 50000000, 200 .xTimeBaseFreq = 50000000, 201 .xPVR = 0x3600 202 } 203 }; 204 205 /* Space for Main Store Vpd 27,200 bytes */ 206 /* May be filled in by the hypervisor so cannot end up in the BSS */ 207 u64 xMsVpd[3400] __attribute__((__section__(".data"))); 208 209 /* Space for Recovery Log Buffer */ 210 /* May be filled in by the hypervisor so cannot end up in the BSS */ 211 static u64 xRecoveryLogBuffer[32] __attribute__((__section__(".data"))); 212 213 static const struct SpCommArea xSpCommArea = { 214 .xDesc = 0xE2D7C3C2, 215 .xFormat = 1, 216 }; 217 218 static const struct ItLpRegSave iseries_reg_save[] = { 219 [0 ... (NR_CPUS-1)] = { 220 .xDesc = 0xd397d9e2, /* "LpRS" */ 221 .xSize = sizeof(struct ItLpRegSave), 222 }, 223 }; 224 225 #define ALPACA_INIT(number) \ 226 { \ 227 .lppaca_ptr = &lppaca[number], \ 228 .reg_save_ptr = &iseries_reg_save[number], \ 229 } 230 231 const struct alpaca alpaca[] = { 232 ALPACA_INIT( 0), 233 #if NR_CPUS > 1 234 ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3), 235 #if NR_CPUS > 4 236 ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7), 237 #if NR_CPUS > 8 238 ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11), 239 ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15), 240 ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19), 241 ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23), 242 ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27), 243 ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31), 244 #if NR_CPUS > 32 245 ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35), 246 ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39), 247 ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43), 248 ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47), 249 ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51), 250 ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55), 251 ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59), 252 ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63), 253 #endif 254 #endif 255 #endif 256 #endif 257 }; 258 259 /* The LparMap data is now located at offset 0x6000 in head.S 260 * It was put there so that the HvReleaseData could address it 261 * with a 32-bit offset as required by the iSeries hypervisor 262 * 263 * The Naca has a pointer to the ItVpdAreas. The hypervisor finds 264 * the Naca via the HvReleaseData area. The HvReleaseData has the 265 * offset into the Naca of the pointer to the ItVpdAreas. 266 */ 267 const struct ItVpdAreas itVpdAreas = { 268 .xSlicDesc = 0xc9a3e5c1, /* "ItVA" */ 269 .xSlicSize = sizeof(struct ItVpdAreas), 270 .xSlicVpdEntries = ItVpdMaxEntries, /* # VPD array entries */ 271 .xSlicDmaEntries = ItDmaMaxEntries, /* # DMA array entries */ 272 .xSlicMaxLogicalProcs = NR_CPUS * 2, /* Max logical procs */ 273 .xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */ 274 .xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks), 275 .xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs), 276 .xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens), 277 .xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens), 278 .xSlicMaxSlotLabels = 0, /* max slot labels */ 279 .xSlicMaxLpQueues = 1, /* max LP queues */ 280 .xPlicDmaLens = { 0 }, /* DMA lengths */ 281 .xPlicDmaToks = { 0 }, /* DMA tokens */ 282 .xSlicVpdLens = { /* VPD lengths */ 283 0,0,0, /* 0 - 2 */ 284 sizeof(xItExtVpdPanel), /* 3 Extended VPD */ 285 sizeof(struct alpaca), /* 4 length of (fake) Paca */ 286 0, /* 5 */ 287 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */ 288 26992, /* 7 length of MS VPD */ 289 0, /* 8 */ 290 sizeof(struct ItLpNaca),/* 9 length of LP Naca */ 291 0, /* 10 */ 292 256, /* 11 length of Recovery Log Buf */ 293 sizeof(struct SpCommArea), /* 12 length of SP Comm Area */ 294 0,0,0, /* 13 - 15 */ 295 sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */ 296 0,0,0,0,0,0, /* 17 - 22 */ 297 sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */ 298 0,0 /* 24 - 25 */ 299 }, 300 .xSlicVpdAdrs = { /* VPD addresses */ 301 0,0,0, /* 0 - 2 */ 302 &xItExtVpdPanel, /* 3 Extended VPD */ 303 &alpaca[0], /* 4 first (fake) Paca */ 304 0, /* 5 */ 305 &xItIplParmsReal, /* 6 IPL parms */ 306 &xMsVpd, /* 7 MS Vpd */ 307 0, /* 8 */ 308 &itLpNaca, /* 9 LpNaca */ 309 0, /* 10 */ 310 &xRecoveryLogBuffer, /* 11 Recovery Log Buffer */ 311 &xSpCommArea, /* 12 SP Comm Area */ 312 0,0,0, /* 13 - 15 */ 313 &xIoHriProcessorVpd, /* 16 Proc Vpd */ 314 0,0,0,0,0,0, /* 17 - 22 */ 315 &hvlpevent_queue, /* 23 Lp Queue */ 316 0,0 317 } 318 }; 319