1 /*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3 *
4 * Author: Li Yang <LeoLi@freescale.com>
5 * Yin Olivia <Hong-hua.Yin@freescale.com>
6 *
7 * Description:
8 * MPC8360E MDS board specific routines.
9 *
10 * Changelog:
11 * Jun 21, 2006 Initial version
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/compiler.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/reboot.h>
25 #include <linux/pci.h>
26 #include <linux/kdev_t.h>
27 #include <linux/major.h>
28 #include <linux/console.h>
29 #include <linux/delay.h>
30 #include <linux/seq_file.h>
31 #include <linux/root_dev.h>
32 #include <linux/initrd.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
35
36 #include <asm/system.h>
37 #include <linux/atomic.h>
38 #include <asm/time.h>
39 #include <asm/io.h>
40 #include <asm/machdep.h>
41 #include <asm/ipic.h>
42 #include <asm/irq.h>
43 #include <asm/prom.h>
44 #include <asm/udbg.h>
45 #include <sysdev/fsl_soc.h>
46 #include <sysdev/fsl_pci.h>
47 #include <sysdev/simple_gpio.h>
48 #include <asm/qe.h>
49 #include <asm/qe_ic.h>
50
51 #include "mpc83xx.h"
52
53 #undef DEBUG
54 #ifdef DEBUG
55 #define DBG(fmt...) udbg_printf(fmt)
56 #else
57 #define DBG(fmt...)
58 #endif
59
60 /* ************************************************************************
61 *
62 * Setup the architecture
63 *
64 */
mpc836x_mds_setup_arch(void)65 static void __init mpc836x_mds_setup_arch(void)
66 {
67 struct device_node *np;
68 u8 __iomem *bcsr_regs = NULL;
69
70 if (ppc_md.progress)
71 ppc_md.progress("mpc836x_mds_setup_arch()", 0);
72
73 /* Map BCSR area */
74 np = of_find_node_by_name(NULL, "bcsr");
75 if (np) {
76 struct resource res;
77
78 of_address_to_resource(np, 0, &res);
79 bcsr_regs = ioremap(res.start, resource_size(&res));
80 of_node_put(np);
81 }
82
83 mpc83xx_setup_pci();
84
85 #ifdef CONFIG_QUICC_ENGINE
86 qe_reset();
87
88 if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
89 par_io_init(np);
90 of_node_put(np);
91
92 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
93 par_io_of_config(np);
94 #ifdef CONFIG_QE_USB
95 /* Must fixup Par IO before QE GPIO chips are registered. */
96 par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
97 par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
98 par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
99 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
100 par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
101 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
102 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
103 #endif /* CONFIG_QE_USB */
104 }
105
106 if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
107 != NULL){
108 uint svid;
109
110 /* Reset the Ethernet PHY */
111 #define BCSR9_GETHRST 0x20
112 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
113 udelay(1000);
114 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
115
116 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
117 svid = mfspr(SPRN_SVR);
118 if (svid == 0x80480021) {
119 void __iomem *immap;
120
121 immap = ioremap(get_immrbase() + 0x14a8, 8);
122
123 /*
124 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
125 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
126 */
127 setbits32(immap, 0x0c003000);
128
129 /*
130 * IMMR + 0x14AC[20:27] = 10101010
131 * (data delay for both UCC's)
132 */
133 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
134
135 iounmap(immap);
136 }
137
138 iounmap(bcsr_regs);
139 of_node_put(np);
140 }
141 #endif /* CONFIG_QUICC_ENGINE */
142 }
143
144 machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
145
146 #ifdef CONFIG_QE_USB
mpc836x_usb_cfg(void)147 static int __init mpc836x_usb_cfg(void)
148 {
149 u8 __iomem *bcsr;
150 struct device_node *np;
151 const char *mode;
152 int ret = 0;
153
154 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
155 if (!np)
156 return -ENODEV;
157
158 bcsr = of_iomap(np, 0);
159 of_node_put(np);
160 if (!bcsr)
161 return -ENOMEM;
162
163 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
164 if (!np) {
165 ret = -ENODEV;
166 goto err;
167 }
168
169 #define BCSR8_TSEC1M_MASK (0x3 << 6)
170 #define BCSR8_TSEC1M_RGMII (0x0 << 6)
171 #define BCSR8_TSEC2M_MASK (0x3 << 4)
172 #define BCSR8_TSEC2M_RGMII (0x0 << 4)
173 /*
174 * Default is GMII (2), but we should set it to RGMII (0) if we use
175 * USB (Eth PHY is in RGMII mode anyway).
176 */
177 clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
178 BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
179
180 #define BCSR13_USBMASK 0x0f
181 #define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
182 #define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
183 #define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
184 #define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
185
186 clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
187
188 mode = of_get_property(np, "mode", NULL);
189 if (mode && !strcmp(mode, "peripheral")) {
190 setbits8(&bcsr[13], BCSR13_nUSBVCC);
191 qe_usb_clock_set(QE_CLK21, 48000000);
192 } else {
193 setbits8(&bcsr[13], BCSR13_USBMODE);
194 /*
195 * The BCSR GPIOs are used to control power and
196 * speed of the USB transceiver. This is needed for
197 * the USB Host only.
198 */
199 simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
200 }
201
202 of_node_put(np);
203 err:
204 iounmap(bcsr);
205 return ret;
206 }
207 machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
208 #endif /* CONFIG_QE_USB */
209
210 /*
211 * Called very early, MMU is off, device-tree isn't unflattened
212 */
mpc836x_mds_probe(void)213 static int __init mpc836x_mds_probe(void)
214 {
215 unsigned long root = of_get_flat_dt_root();
216
217 return of_flat_dt_is_compatible(root, "MPC836xMDS");
218 }
219
define_machine(mpc836x_mds)220 define_machine(mpc836x_mds) {
221 .name = "MPC836x MDS",
222 .probe = mpc836x_mds_probe,
223 .setup_arch = mpc836x_mds_setup_arch,
224 .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
225 .get_irq = ipic_get_irq,
226 .restart = mpc83xx_restart,
227 .time_init = mpc83xx_time_init,
228 .calibrate_decr = generic_calibrate_decr,
229 .progress = udbg_progress,
230 };
231