1 #ifndef _ASM_POWERPC_MMU_BOOK3E_H_ 2 #define _ASM_POWERPC_MMU_BOOK3E_H_ 3 /* 4 * Freescale Book-E/Book-3e (ISA 2.06+) MMU support 5 */ 6 7 /* Book-3e defined page sizes */ 8 #define BOOK3E_PAGESZ_1K 0 9 #define BOOK3E_PAGESZ_2K 1 10 #define BOOK3E_PAGESZ_4K 2 11 #define BOOK3E_PAGESZ_8K 3 12 #define BOOK3E_PAGESZ_16K 4 13 #define BOOK3E_PAGESZ_32K 5 14 #define BOOK3E_PAGESZ_64K 6 15 #define BOOK3E_PAGESZ_128K 7 16 #define BOOK3E_PAGESZ_256K 8 17 #define BOOK3E_PAGESZ_512K 9 18 #define BOOK3E_PAGESZ_1M 10 19 #define BOOK3E_PAGESZ_2M 11 20 #define BOOK3E_PAGESZ_4M 12 21 #define BOOK3E_PAGESZ_8M 13 22 #define BOOK3E_PAGESZ_16M 14 23 #define BOOK3E_PAGESZ_32M 15 24 #define BOOK3E_PAGESZ_64M 16 25 #define BOOK3E_PAGESZ_128M 17 26 #define BOOK3E_PAGESZ_256M 18 27 #define BOOK3E_PAGESZ_512M 19 28 #define BOOK3E_PAGESZ_1GB 20 29 #define BOOK3E_PAGESZ_2GB 21 30 #define BOOK3E_PAGESZ_4GB 22 31 #define BOOK3E_PAGESZ_8GB 23 32 #define BOOK3E_PAGESZ_16GB 24 33 #define BOOK3E_PAGESZ_32GB 25 34 #define BOOK3E_PAGESZ_64GB 26 35 #define BOOK3E_PAGESZ_128GB 27 36 #define BOOK3E_PAGESZ_256GB 28 37 #define BOOK3E_PAGESZ_512GB 29 38 #define BOOK3E_PAGESZ_1TB 30 39 #define BOOK3E_PAGESZ_2TB 31 40 41 /* MAS registers bit definitions */ 42 43 #define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) 44 #define MAS0_ESEL(x) (((x) << 16) & 0x0FFF0000) 45 #define MAS0_NV(x) ((x) & 0x00000FFF) 46 #define MAS0_ESEL_MASK 0x0FFF0000 47 #define MAS0_HES 0x00004000 48 #define MAS0_WQ_ALLWAYS 0x00000000 49 #define MAS0_WQ_COND 0x00001000 50 #define MAS0_WQ_CLR_RSRV 0x00002000 51 52 #define MAS1_VALID 0x80000000 53 #define MAS1_IPROT 0x40000000 54 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000) 55 #define MAS1_IND 0x00002000 56 #define MAS1_TS 0x00001000 57 #define MAS1_TSIZE_MASK 0x00000f80 58 #define MAS1_TSIZE_SHIFT 7 59 #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) 60 61 #define MAS2_EPN 0xFFFFF000 62 #define MAS2_X0 0x00000040 63 #define MAS2_X1 0x00000020 64 #define MAS2_W 0x00000010 65 #define MAS2_I 0x00000008 66 #define MAS2_M 0x00000004 67 #define MAS2_G 0x00000002 68 #define MAS2_E 0x00000001 69 #define MAS2_WIMGE_MASK 0x0000001f 70 #define MAS2_EPN_MASK(size) (~0 << (size + 10)) 71 #define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) 72 73 #define MAS3_RPN 0xFFFFF000 74 #define MAS3_U0 0x00000200 75 #define MAS3_U1 0x00000100 76 #define MAS3_U2 0x00000080 77 #define MAS3_U3 0x00000040 78 #define MAS3_UX 0x00000020 79 #define MAS3_SX 0x00000010 80 #define MAS3_UW 0x00000008 81 #define MAS3_SW 0x00000004 82 #define MAS3_UR 0x00000002 83 #define MAS3_SR 0x00000001 84 #define MAS3_BAP_MASK 0x0000003f 85 #define MAS3_SPSIZE 0x0000003e 86 #define MAS3_SPSIZE_SHIFT 1 87 88 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) 89 #define MAS4_INDD 0x00008000 /* Default IND */ 90 #define MAS4_TSIZED(x) MAS1_TSIZE(x) 91 #define MAS4_X0D 0x00000040 92 #define MAS4_X1D 0x00000020 93 #define MAS4_WD 0x00000010 94 #define MAS4_ID 0x00000008 95 #define MAS4_MD 0x00000004 96 #define MAS4_GD 0x00000002 97 #define MAS4_ED 0x00000001 98 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ 99 #define MAS4_WIMGED_SHIFT 0 100 #define MAS4_VLED MAS4_X1D /* Default VLE */ 101 #define MAS4_ACMD 0x000000c0 /* Default ACM */ 102 #define MAS4_ACMD_SHIFT 6 103 #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */ 104 #define MAS4_TSIZED_SHIFT 7 105 106 #define MAS6_SPID0 0x3FFF0000 107 #define MAS6_SPID1 0x00007FFE 108 #define MAS6_ISIZE(x) MAS1_TSIZE(x) 109 #define MAS6_SAS 0x00000001 110 #define MAS6_SPID MAS6_SPID0 111 #define MAS6_SIND 0x00000002 /* Indirect page */ 112 #define MAS6_SIND_SHIFT 1 113 #define MAS6_SPID_MASK 0x3fff0000 114 #define MAS6_SPID_SHIFT 16 115 #define MAS6_ISIZE_MASK 0x00000f80 116 #define MAS6_ISIZE_SHIFT 7 117 118 #define MAS7_RPN 0xFFFFFFFF 119 120 /* Bit definitions for MMUCFG */ 121 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 122 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ 123 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ 124 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ 125 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ 126 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ 127 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ 128 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ 129 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ 130 131 /* Bit definitions for MMUCSR0 */ 132 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 133 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 134 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 135 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ 136 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ 137 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) 138 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ 139 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ 140 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 141 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 142 143 /* MMUCFG bits */ 144 #define MMUCFG_MAVN_NASK 0x00000003 145 #define MMUCFG_MAVN_V1_0 0x00000000 146 #define MMUCFG_MAVN_V2_0 0x00000001 147 #define MMUCFG_NTLB_MASK 0x0000000c 148 #define MMUCFG_NTLB_SHIFT 2 149 #define MMUCFG_PIDSIZE_MASK 0x000007c0 150 #define MMUCFG_PIDSIZE_SHIFT 6 151 #define MMUCFG_TWC 0x00008000 152 #define MMUCFG_LRAT 0x00010000 153 #define MMUCFG_RASIZE_MASK 0x00fe0000 154 #define MMUCFG_RASIZE_SHIFT 17 155 #define MMUCFG_LPIDSIZE_MASK 0x0f000000 156 #define MMUCFG_LPIDSIZE_SHIFT 24 157 158 /* TLBnCFG encoding */ 159 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 160 #define TLBnCFG_HES 0x00002000 /* HW select supported */ 161 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ 162 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 163 #define TLBnCFG_IND 0x00020000 /* IND entries supported */ 164 #define TLBnCFG_PT 0x00040000 /* Can load from page table */ 165 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ 166 #define TLBnCFG_MINSIZE_SHIFT 20 167 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ 168 #define TLBnCFG_MAXSIZE_SHIFT 16 169 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 170 171 /* TLBnPS encoding */ 172 #define TLBnPS_4K 0x00000004 173 #define TLBnPS_8K 0x00000008 174 #define TLBnPS_16K 0x00000010 175 #define TLBnPS_32K 0x00000020 176 #define TLBnPS_64K 0x00000040 177 #define TLBnPS_128K 0x00000080 178 #define TLBnPS_256K 0x00000100 179 #define TLBnPS_512K 0x00000200 180 #define TLBnPS_1M 0x00000400 181 #define TLBnPS_2M 0x00000800 182 #define TLBnPS_4M 0x00001000 183 #define TLBnPS_8M 0x00002000 184 #define TLBnPS_16M 0x00004000 185 #define TLBnPS_32M 0x00008000 186 #define TLBnPS_64M 0x00010000 187 #define TLBnPS_128M 0x00020000 188 #define TLBnPS_256M 0x00040000 189 #define TLBnPS_512M 0x00080000 190 #define TLBnPS_1G 0x00100000 191 #define TLBnPS_2G 0x00200000 192 #define TLBnPS_4G 0x00400000 193 #define TLBnPS_8G 0x00800000 194 #define TLBnPS_16G 0x01000000 195 #define TLBnPS_32G 0x02000000 196 #define TLBnPS_64G 0x04000000 197 #define TLBnPS_128G 0x08000000 198 #define TLBnPS_256G 0x10000000 199 200 /* tlbilx action encoding */ 201 #define TLBILX_T_ALL 0 202 #define TLBILX_T_TID 1 203 #define TLBILX_T_FULLMATCH 3 204 #define TLBILX_T_CLASS0 4 205 #define TLBILX_T_CLASS1 5 206 #define TLBILX_T_CLASS2 6 207 #define TLBILX_T_CLASS3 7 208 209 #ifndef __ASSEMBLY__ 210 211 extern unsigned int tlbcam_index; 212 213 typedef struct { 214 unsigned int id; 215 unsigned int active; 216 unsigned long vdso_base; 217 #ifdef CONFIG_PPC_ICSWX 218 struct spinlock *cop_lockp; /* guard cop related stuff */ 219 unsigned long acop; /* mask of enabled coprocessor types */ 220 #endif /* CONFIG_PPC_ICSWX */ 221 #ifdef CONFIG_PPC_MM_SLICES 222 u64 low_slices_psize; /* SLB page size encodings */ 223 u64 high_slices_psize; /* 4 bits per slice for now */ 224 u16 user_psize; /* page size index */ 225 #endif 226 } mm_context_t; 227 228 /* Page size definitions, common between 32 and 64-bit 229 * 230 * shift : is the "PAGE_SHIFT" value for that page size 231 * penc : is the pte encoding mask 232 * 233 */ 234 struct mmu_psize_def 235 { 236 unsigned int shift; /* number of bits */ 237 unsigned int enc; /* PTE encoding */ 238 unsigned int ind; /* Corresponding indirect page size shift */ 239 unsigned int flags; 240 #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ 241 #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ 242 }; 243 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 244 245 /* The page sizes use the same names as 64-bit hash but are 246 * constants 247 */ 248 #if defined(CONFIG_PPC_4K_PAGES) 249 #define mmu_virtual_psize MMU_PAGE_4K 250 #elif defined(CONFIG_PPC_64K_PAGES) 251 #define mmu_virtual_psize MMU_PAGE_64K 252 #else 253 #error Unsupported page size 254 #endif 255 256 extern int mmu_linear_psize; 257 extern int mmu_vmemmap_psize; 258 259 #ifdef CONFIG_PPC64 260 extern unsigned long linear_map_top; 261 262 /* 263 * 64-bit booke platforms don't load the tlb in the tlb miss handler code. 264 * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to 265 * return 1, indicating that the tlb requires preloading. 266 */ 267 #define HUGETLB_NEED_PRELOAD 268 #endif 269 270 #endif /* !__ASSEMBLY__ */ 271 272 #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ 273