1/*
2 * P1022 DS 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "fsl/p1022si-pre.dtsi"
12/ {
13	model = "fsl,P1022DS";
14	compatible = "fsl,P1022DS";
15
16	memory {
17		device_type = "memory";
18	};
19
20	lbc: localbus@fffe05000 {
21		reg = <0xf 0xffe05000 0 0x1000>;
22		ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
23			  0x1 0x0 0xf 0xe0000000 0x08000000
24			  0x2 0x0 0xf 0xff800000 0x00040000
25			  0x3 0x0 0xf 0xffdf0000 0x00008000>;
26
27		/*
28		 * This node is used to access the pixis via "indirect" mode,
29		 * which is done by writing the pixis register index to chip
30		 * select 0 and the value to/from chip select 1.  Indirect
31		 * mode is the only way to access the pixis when DIU video
32		 * is enabled.  Note that this assumes that the first column
33		 * of the 'ranges' property above is the chip select number.
34		 */
35		board-control@0,0 {
36			compatible = "fsl,p1022ds-indirect-pixis";
37			reg = <0x0 0x0 1	/* CS0 */
38			       0x1 0x0 1>;	/* CS1 */
39		};
40
41		nor@0,0 {
42			#address-cells = <1>;
43			#size-cells = <1>;
44			compatible = "cfi-flash";
45			reg = <0x0 0x0 0x8000000>;
46			bank-width = <2>;
47			device-width = <1>;
48
49			partition@0 {
50				reg = <0x0 0x03000000>;
51				label = "ramdisk-nor";
52				read-only;
53			};
54
55			partition@3000000 {
56				reg = <0x03000000 0x00e00000>;
57				label = "diagnostic-nor";
58				read-only;
59			};
60
61			partition@3e00000 {
62				reg = <0x03e00000 0x00200000>;
63				label = "dink-nor";
64				read-only;
65			};
66
67			partition@4000000 {
68				reg = <0x04000000 0x00400000>;
69				label = "kernel-nor";
70				read-only;
71			};
72
73			partition@4400000 {
74				reg = <0x04400000 0x03b00000>;
75				label = "jffs2-nor";
76			};
77
78			partition@7f00000 {
79				reg = <0x07f00000 0x00080000>;
80				label = "dtb-nor";
81				read-only;
82			};
83
84			partition@7f80000 {
85				reg = <0x07f80000 0x00080000>;
86				label = "u-boot-nor";
87				read-only;
88			};
89		};
90
91		nand@2,0 {
92			#address-cells = <1>;
93			#size-cells = <1>;
94			compatible = "fsl,elbc-fcm-nand";
95			reg = <0x2 0x0 0x40000>;
96
97			partition@0 {
98				reg = <0x0 0x02000000>;
99				label = "u-boot-nand";
100				read-only;
101			};
102
103			partition@2000000 {
104				reg = <0x02000000 0x10000000>;
105				label = "jffs2-nand";
106			};
107
108			partition@12000000 {
109				reg = <0x12000000 0x10000000>;
110				label = "ramdisk-nand";
111				read-only;
112			};
113
114			partition@22000000 {
115				reg = <0x22000000 0x04000000>;
116				label = "kernel-nand";
117			};
118
119			partition@26000000 {
120				reg = <0x26000000 0x01000000>;
121				label = "dtb-nand";
122				read-only;
123			};
124
125			partition@27000000 {
126				reg = <0x27000000 0x19000000>;
127				label = "reserved-nand";
128			};
129		};
130
131		board-control@3,0 {
132			compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
133			reg = <3 0 0x30>;
134			interrupt-parent = <&mpic>;
135			/*
136			 * IRQ8 is generated if the "EVENT" switch is pressed
137			 * and PX_CTL[EVESEL] is set to 00.
138			 */
139			interrupts = <8 8 0 0>;
140		};
141	};
142
143	soc: soc@fffe00000 {
144		ranges = <0x0 0xf 0xffe00000 0x100000>;
145
146		i2c@3100 {
147			wm8776:codec@1a {
148				compatible = "wlf,wm8776";
149				reg = <0x1a>;
150				/*
151				 * clock-frequency will be set by U-Boot if
152				 * the clock is enabled.
153				 */
154			};
155		};
156
157		spi@7000 {
158			flash@0 {
159				#address-cells = <1>;
160				#size-cells = <1>;
161				compatible = "spansion,s25sl12801";
162				reg = <0>;
163				spi-max-frequency = <40000000>; /* input clock */
164
165				partition@0 {
166					label = "u-boot-spi";
167					reg = <0x00000000 0x00100000>;
168					read-only;
169				};
170				partition@100000 {
171					label = "kernel-spi";
172					reg = <0x00100000 0x00500000>;
173					read-only;
174				};
175				partition@600000 {
176					label = "dtb-spi";
177					reg = <0x00600000 0x00100000>;
178					read-only;
179				};
180				partition@700000 {
181					label = "file system-spi";
182					reg = <0x00700000 0x00900000>;
183				};
184			};
185		};
186
187		ssi@15000 {
188			fsl,mode = "i2s-slave";
189			codec-handle = <&wm8776>;
190			fsl,ssi-asynchronous;
191		};
192
193		usb@22000 {
194			phy_type = "ulpi";
195		};
196
197		usb@23000 {
198			status = "disabled";
199		};
200
201		mdio@24000 {
202			phy0: ethernet-phy@0 {
203				interrupts = <3 1 0 0>;
204				reg = <0x1>;
205			};
206			phy1: ethernet-phy@1 {
207				interrupts = <9 1 0 0>;
208				reg = <0x2>;
209			};
210			tbi-phy@2 {
211				device_type = "tbi-phy";
212				reg = <0x2>;
213			};
214		};
215
216		ethernet@b0000 {
217			phy-handle = <&phy0>;
218			phy-connection-type = "rgmii-id";
219		};
220
221		ethernet@b1000 {
222			phy-handle = <&phy1>;
223			phy-connection-type = "rgmii-id";
224		};
225	};
226
227	pci0: pcie@fffe09000 {
228		reg = <0xf 0xffe09000 0 0x1000>;
229		ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
230			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
231		pcie@0 {
232			ranges = <0x2000000 0x0 0xe0000000
233				  0x2000000 0x0 0xe0000000
234				  0x0 0x20000000
235
236				  0x1000000 0x0 0x0
237				  0x1000000 0x0 0x0
238				  0x0 0x100000>;
239		};
240	};
241
242	pci1: pcie@fffe0a000 {
243		reg = <0xf 0xffe0a000 0 0x1000>;
244		ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
245			  0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
246		pcie@0 {
247			reg = <0x0 0x0 0x0 0x0 0x0>;
248			ranges = <0x2000000 0x0 0xe0000000
249				  0x2000000 0x0 0xe0000000
250				  0x0 0x20000000
251
252				  0x1000000 0x0 0x0
253				  0x1000000 0x0 0x0
254				  0x0 0x100000>;
255		};
256	};
257
258	pci2: pcie@fffe0b000 {
259		reg = <0xf 0xffe0b000 0 0x1000>;
260		ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
261			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
262		pcie@0 {
263			ranges = <0x2000000 0x0 0xe0000000
264				  0x2000000 0x0 0xe0000000
265				  0x0 0x20000000
266
267				  0x1000000 0x0 0x0
268				  0x1000000 0x0 0x0
269				  0x0 0x100000>;
270		};
271	};
272};
273
274/include/ "fsl/p1022si-post.dtsi"
275