1/*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8569si-pre.dtsi"
13
14/ {
15	model = "MPC8569EMDS";
16	compatible = "fsl,MPC8569EMDS";
17	#address-cells = <2>;
18	#size-cells = <2>;
19	interrupt-parent = <&mpic>;
20
21	aliases {
22		ethernet2 = &enet2;
23		ethernet3 = &enet3;
24		ethernet5 = &enet5;
25		ethernet7 = &enet7;
26		rapidio0 = &rio;
27	};
28
29	memory {
30		device_type = "memory";
31	};
32
33	lbc: localbus@e0005000 {
34		reg = <0x0 0xe0005000 0x0 0x1000>;
35
36		ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
37			  0x1 0x0 0x0 0xf8000000 0x00008000
38			  0x2 0x0 0x0 0xf0000000 0x04000000
39			  0x3 0x0 0x0 0xfc000000 0x00008000
40			  0x4 0x0 0x0 0xf8008000 0x00008000
41			  0x5 0x0 0x0 0xf8010000 0x00008000>;
42
43		nor@0,0 {
44			#address-cells = <1>;
45			#size-cells = <1>;
46			compatible = "cfi-flash";
47			reg = <0x0 0x0 0x02000000>;
48			bank-width = <1>;
49			device-width = <1>;
50			partition@0 {
51				label = "ramdisk";
52				reg = <0x00000000 0x01c00000>;
53			};
54			partition@1c00000 {
55				label = "kernel";
56				reg = <0x01c00000 0x002e0000>;
57			};
58			partiton@1ee0000 {
59				label = "dtb";
60				reg = <0x01ee0000 0x00020000>;
61			};
62			partition@1f00000 {
63				label = "firmware";
64				reg = <0x01f00000 0x00080000>;
65				read-only;
66			};
67			partition@1f80000 {
68				label = "u-boot";
69				reg = <0x01f80000 0x00080000>;
70				read-only;
71			};
72		};
73
74		bcsr@1,0 {
75			#address-cells = <1>;
76			#size-cells = <1>;
77			compatible = "fsl,mpc8569mds-bcsr";
78			reg = <1 0 0x8000>;
79			ranges = <0 1 0 0x8000>;
80
81			bcsr17: gpio-controller@11 {
82				#gpio-cells = <2>;
83				compatible = "fsl,mpc8569mds-bcsr-gpio";
84				reg = <0x11 0x1>;
85				gpio-controller;
86			};
87		};
88
89		nand@3,0 {
90			compatible = "fsl,mpc8569-fcm-nand",
91				     "fsl,elbc-fcm-nand";
92			reg = <3 0 0x8000>;
93		};
94
95		pib@4,0 {
96			compatible = "fsl,mpc8569mds-pib";
97			reg = <4 0 0x8000>;
98		};
99
100		pib@5,0 {
101			compatible = "fsl,mpc8569mds-pib";
102			reg = <5 0 0x8000>;
103		};
104	};
105
106	soc: soc@e0000000 {
107		ranges = <0x0 0x0 0xe0000000 0x100000>;
108
109		i2c-sleep-nexus {
110			i2c@3000 {
111				rtc@68 {
112					compatible = "dallas,ds1374";
113					reg = <0x68>;
114					interrupts = <3 1 0 0>;
115				};
116			};
117		};
118
119		sdhc@2e000 {
120			status = "disabled";
121			sdhci,1-bit-only;
122		};
123
124		par_io@e0100 {
125			num-ports = <7>;
126
127			qe_pio_e: gpio-controller@80 {
128				#gpio-cells = <2>;
129				compatible = "fsl,mpc8569-qe-pario-bank",
130					     "fsl,mpc8323-qe-pario-bank";
131				reg = <0x80 0x18>;
132				gpio-controller;
133			};
134
135			qe_pio_f: gpio-controller@a0 {
136				#gpio-cells = <2>;
137				compatible = "fsl,mpc8569-qe-pario-bank",
138					     "fsl,mpc8323-qe-pario-bank";
139				reg = <0xa0 0x18>;
140				gpio-controller;
141			};
142
143			pio1: ucc_pin@01 {
144				pio-map = <
145			/* port  pin  dir  open_drain  assignment  has_irq */
146					0x2  0x1f 0x1  0x0  0x1  0x0	/* QE_MUX_MDC */
147					0x2  0x1e 0x3  0x0  0x2  0x0	/* QE_MUX_MDIO */
148					0x2  0x0b 0x2  0x0  0x1  0x0	/* CLK12*/
149					0x0  0x0  0x1  0x0  0x3  0x0	/* ENET1_TXD0_SER1_TXD0 */
150					0x0  0x1  0x1  0x0  0x3  0x0	/* ENET1_TXD1_SER1_TXD1 */
151					0x0  0x2  0x1  0x0  0x1  0x0	/* ENET1_TXD2_SER1_TXD2 */
152					0x0  0x3  0x1  0x0  0x2  0x0	/* ENET1_TXD3_SER1_TXD3 */
153					0x0  0x6  0x2  0x0  0x3  0x0	/* ENET1_RXD0_SER1_RXD0	*/
154					0x0  0x7  0x2  0x0  0x1  0x0	/* ENET1_RXD1_SER1_RXD1	*/
155					0x0  0x8  0x2  0x0  0x2  0x0	/* ENET1_RXD2_SER1_RXD2	*/
156					0x0  0x9  0x2  0x0  0x2  0x0	/* ENET1_RXD3_SER1_RXD3	*/
157					0x0  0x4  0x1  0x0  0x2  0x0	/* ENET1_TX_EN_SER1_RTS_B */
158					0x0  0xc  0x2  0x0  0x3  0x0	/* ENET1_RX_DV_SER1_CTS_B */
159					0x2  0x8  0x2  0x0  0x1  0x0	/* ENET1_GRXCLK	*/
160					0x2  0x14 0x1  0x0  0x2  0x0>;	/* ENET1_GTXCLK	*/
161			};
162
163			pio2: ucc_pin@02 {
164				pio-map = <
165			/* port  pin  dir  open_drain  assignment  has_irq */
166					0x2  0x1f 0x1  0x0  0x1  0x0	/* QE_MUX_MDC */
167					0x2  0x1e 0x3  0x0  0x2  0x0	/* QE_MUX_MDIO */
168					0x2  0x10 0x2  0x0  0x3  0x0	/* CLK17 */
169					0x0  0xe  0x1  0x0  0x2  0x0	/* ENET2_TXD0_SER2_TXD0 */
170					0x0  0xf  0x1  0x0  0x2  0x0	/* ENET2_TXD1_SER2_TXD1 */
171					0x0  0x10 0x1  0x0  0x1  0x0	/* ENET2_TXD2_SER2_TXD2 */
172					0x0  0x11 0x1  0x0  0x1  0x0	/* ENET2_TXD3_SER2_TXD3 */
173					0x0  0x14 0x2  0x0  0x2  0x0	/* ENET2_RXD0_SER2_RXD0	*/
174					0x0  0x15 0x2  0x0  0x1  0x0	/* ENET2_RXD1_SER2_RXD1	*/
175					0x0  0x16 0x2  0x0  0x1  0x0	/* ENET2_RXD2_SER2_RXD2	*/
176					0x0  0x17 0x2  0x0  0x1  0x0	/* ENET2_RXD3_SER2_RXD3	*/
177					0x0  0x12 0x1  0x0  0x2  0x0	/* ENET2_TX_EN_SER2_RTS_B */
178					0x0  0x1a 0x2  0x0  0x3  0x0	/* ENET2_RX_DV_SER2_CTS_B */
179					0x2  0x3  0x2  0x0  0x1  0x0	/* ENET2_GRXCLK	*/
180					0x2  0x2 0x1  0x0  0x2  0x0>;	/* ENET2_GTXCLK	*/
181			};
182
183			pio3: ucc_pin@03 {
184				pio-map = <
185			/* port  pin  dir  open_drain  assignment  has_irq */
186					0x2  0x1f 0x1  0x0  0x1  0x0	/* QE_MUX_MDC */
187					0x2  0x1e 0x3  0x0  0x2  0x0	/* QE_MUX_MDIO */
188					0x2  0x0b 0x2  0x0  0x1  0x0	/* CLK12*/
189					0x0  0x1d 0x1  0x0  0x2  0x0	/* ENET3_TXD0_SER3_TXD0 */
190					0x0  0x1e 0x1  0x0  0x3  0x0	/* ENET3_TXD1_SER3_TXD1 */
191					0x0  0x1f 0x1  0x0  0x2  0x0	/* ENET3_TXD2_SER3_TXD2 */
192					0x1  0x0  0x1  0x0  0x3  0x0	/* ENET3_TXD3_SER3_TXD3 */
193					0x1  0x3  0x2  0x0  0x3  0x0	/* ENET3_RXD0_SER3_RXD0	*/
194					0x1  0x4  0x2  0x0  0x1  0x0	/* ENET3_RXD1_SER3_RXD1	*/
195					0x1  0x5  0x2  0x0  0x2  0x0	/* ENET3_RXD2_SER3_RXD2	*/
196					0x1  0x6  0x2  0x0  0x3  0x0	/* ENET3_RXD3_SER3_RXD3	*/
197					0x1  0x1  0x1  0x0  0x1  0x0	/* ENET3_TX_EN_SER3_RTS_B */
198					0x1  0x9  0x2  0x0  0x3  0x0	/* ENET3_RX_DV_SER3_CTS_B */
199					0x2  0x9  0x2  0x0  0x2  0x0	/* ENET3_GRXCLK	*/
200					0x2  0x19 0x1  0x0  0x2  0x0>;	/* ENET3_GTXCLK	*/
201			};
202
203			pio4: ucc_pin@04 {
204				pio-map = <
205			/* port  pin  dir  open_drain  assignment  has_irq */
206					0x2  0x1f 0x1  0x0  0x1  0x0	/* QE_MUX_MDC */
207					0x2  0x1e 0x3  0x0  0x2  0x0	/* QE_MUX_MDIO */
208					0x2  0x10 0x2  0x0  0x3  0x0	/* CLK17 */
209					0x1  0xc  0x1  0x0  0x2  0x0	/* ENET4_TXD0_SER4_TXD0 */
210					0x1  0xd  0x1  0x0  0x2  0x0	/* ENET4_TXD1_SER4_TXD1 */
211					0x1  0xe  0x1  0x0  0x1  0x0	/* ENET4_TXD2_SER4_TXD2 */
212					0x1  0xf  0x1  0x0  0x2  0x0	/* ENET4_TXD3_SER4_TXD3 */
213					0x1  0x12 0x2  0x0  0x2  0x0	/* ENET4_RXD0_SER4_RXD0	*/
214					0x1  0x13 0x2  0x0  0x1  0x0	/* ENET4_RXD1_SER4_RXD1	*/
215					0x1  0x14 0x2  0x0  0x1  0x0	/* ENET4_RXD2_SER4_RXD2	*/
216					0x1  0x15 0x2  0x0  0x2  0x0	/* ENET4_RXD3_SER4_RXD3	*/
217					0x1  0x10 0x1  0x0  0x2  0x0	/* ENET4_TX_EN_SER4_RTS_B */
218					0x1  0x18 0x2  0x0  0x3  0x0	/* ENET4_RX_DV_SER4_CTS_B */
219					0x2  0x11 0x2  0x0  0x2  0x0	/* ENET4_GRXCLK	*/
220					0x2  0x18 0x1  0x0  0x2  0x0>;	/* ENET4_GTXCLK	*/
221			};
222		};
223	};
224
225	qe: qe@e0080000 {
226		ranges = <0x0 0x0 0xe0080000 0x40000>;
227		reg = <0x0 0xe0080000 0x0 0x480>;
228
229		spi@4c0 {
230			gpios = <&qe_pio_e 30 0>;
231			mode = "cpu-qe";
232
233			serial-flash@0 {
234				compatible = "stm,m25p40";
235				reg = <0>;
236				spi-max-frequency = <25000000>;
237			};
238		};
239
240		spi@500 {
241			mode = "cpu";
242		};
243
244		usb@6c0 {
245			fsl,fullspeed-clock = "clk5";
246			fsl,lowspeed-clock = "brg10";
247			gpios = <&qe_pio_f 3 0   /* USBOE */
248				 &qe_pio_f 4 0   /* USBTP */
249				 &qe_pio_f 5 0   /* USBTN */
250				 &qe_pio_f 6 0   /* USBRP */
251				 &qe_pio_f 8 0   /* USBRN */
252				 &bcsr17   1 0   /* SPEED */
253				 &bcsr17   2 0>; /* POWER */
254		};
255
256		enet0: ucc@2000 {
257			device_type = "network";
258			compatible = "ucc_geth";
259			local-mac-address = [ 00 00 00 00 00 00 ];
260			rx-clock-name = "none";
261			tx-clock-name = "clk12";
262			pio-handle = <&pio1>;
263			tbi-handle = <&tbi1>;
264			phy-handle = <&qe_phy0>;
265			phy-connection-type = "rgmii-id";
266		};
267
268		mdio@2120 {
269			#address-cells = <1>;
270			#size-cells = <0>;
271			reg = <0x2120 0x18>;
272			compatible = "fsl,ucc-mdio";
273
274			qe_phy0: ethernet-phy@07 {
275				interrupt-parent = <&mpic>;
276				interrupts = <1 1 0 0>;
277				reg = <0x7>;
278				device_type = "ethernet-phy";
279			};
280			qe_phy1: ethernet-phy@01 {
281				interrupt-parent = <&mpic>;
282				interrupts = <2 1 0 0>;
283				reg = <0x1>;
284				device_type = "ethernet-phy";
285			};
286			qe_phy2: ethernet-phy@02 {
287				interrupt-parent = <&mpic>;
288				interrupts = <3 1 0 0>;
289				reg = <0x2>;
290				device_type = "ethernet-phy";
291			};
292			qe_phy3: ethernet-phy@03 {
293				interrupt-parent = <&mpic>;
294				interrupts = <4 1 0 0>;
295				reg = <0x3>;
296				device_type = "ethernet-phy";
297			};
298			qe_phy5: ethernet-phy@04 {
299				reg = <0x04>;
300				device_type = "ethernet-phy";
301			};
302			qe_phy7: ethernet-phy@06 {
303				reg = <0x6>;
304				device_type = "ethernet-phy";
305			};
306			tbi1: tbi-phy@11 {
307				reg = <0x11>;
308				device_type = "tbi-phy";
309			};
310		};
311		mdio@3520 {
312			#address-cells = <1>;
313			#size-cells = <0>;
314			reg = <0x3520 0x18>;
315			compatible = "fsl,ucc-mdio";
316
317			tbi6: tbi-phy@15 {
318			reg = <0x15>;
319			device_type = "tbi-phy";
320			};
321		};
322		mdio@3720 {
323			#address-cells = <1>;
324			#size-cells = <0>;
325			reg = <0x3720 0x38>;
326			compatible = "fsl,ucc-mdio";
327			tbi8: tbi-phy@17 {
328				reg = <0x17>;
329				device_type = "tbi-phy";
330			};
331		};
332
333		enet2: ucc@2200 {
334			device_type = "network";
335			compatible = "ucc_geth";
336			local-mac-address = [ 00 00 00 00 00 00 ];
337			rx-clock-name = "none";
338			tx-clock-name = "clk12";
339			pio-handle = <&pio3>;
340			tbi-handle = <&tbi3>;
341			phy-handle = <&qe_phy2>;
342			phy-connection-type = "rgmii-id";
343		};
344
345		mdio@2320 {
346			#address-cells = <1>;
347			#size-cells = <0>;
348			reg = <0x2320 0x18>;
349			compatible = "fsl,ucc-mdio";
350			tbi3: tbi-phy@11 {
351				reg = <0x11>;
352				device_type = "tbi-phy";
353			};
354		};
355
356		enet1: ucc@3000 {
357			device_type = "network";
358			compatible = "ucc_geth";
359			local-mac-address = [ 00 00 00 00 00 00 ];
360			rx-clock-name = "none";
361			tx-clock-name = "clk17";
362			pio-handle = <&pio2>;
363			tbi-handle = <&tbi2>;
364			phy-handle = <&qe_phy1>;
365			phy-connection-type = "rgmii-id";
366		};
367
368		mdio@3120 {
369			#address-cells = <1>;
370			#size-cells = <0>;
371			reg = <0x3120 0x18>;
372			compatible = "fsl,ucc-mdio";
373			tbi2: tbi-phy@11 {
374				reg = <0x11>;
375				device_type = "tbi-phy";
376			};
377		};
378
379		enet3: ucc@3200 {
380			device_type = "network";
381			compatible = "ucc_geth";
382			local-mac-address = [ 00 00 00 00 00 00 ];
383			rx-clock-name = "none";
384			tx-clock-name = "clk17";
385			pio-handle = <&pio4>;
386			tbi-handle = <&tbi4>;
387			phy-handle = <&qe_phy3>;
388			phy-connection-type = "rgmii-id";
389		};
390
391		mdio@3320 {
392			#address-cells = <1>;
393			#size-cells = <0>;
394			reg = <0x3320 0x18>;
395			compatible = "fsl,ucc-mdio";
396			tbi4: tbi-phy@11 {
397				reg = <0x11>;
398				device_type = "tbi-phy";
399			};
400		};
401
402		enet5: ucc@3400 {
403			device_type = "network";
404			compatible = "ucc_geth";
405			local-mac-address = [ 00 00 00 00 00 00 ];
406			rx-clock-name = "none";
407			tx-clock-name = "none";
408			tbi-handle = <&tbi6>;
409			phy-handle = <&qe_phy5>;
410			phy-connection-type = "sgmii";
411		};
412
413		enet7: ucc@3600 {
414			device_type = "network";
415			compatible = "ucc_geth";
416			local-mac-address = [ 00 00 00 00 00 00 ];
417			rx-clock-name = "none";
418			tx-clock-name = "none";
419			tbi-handle = <&tbi8>;
420			phy-handle = <&qe_phy7>;
421			phy-connection-type = "sgmii";
422		};
423	};
424
425	/* PCI Express */
426	pci1: pcie@e000a000 {
427		reg = <0x0 0xe000a000 0x0 0x1000>;
428		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
429			  0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
430		pcie@0 {
431			ranges = <0x2000000 0x0 0xa0000000
432				  0x2000000 0x0 0xa0000000
433				  0x0 0x10000000
434
435				  0x1000000 0x0 0x0
436				  0x1000000 0x0 0x0
437				  0x0 0x800000>;
438		};
439	};
440
441	rio: rapidio@e00c00000 {
442		reg = <0x0 0xe00c0000 0x0 0x20000>;
443		port1 {
444			ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
445		};
446		port2 {
447			status = "disabled";
448		};
449	};
450};
451
452/include/ "fsl/mpc8569si-post.dtsi"
453