1 /*
2 * Interrupt handing routines for NEC VR4100 series.
3 *
4 * Copyright (C) 2005-2007 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/irq.h>
23
24 #include <asm/irq_cpu.h>
25 #include <asm/system.h>
26 #include <asm/vr41xx/irq.h>
27
28 typedef struct irq_cascade {
29 int (*get_irq)(unsigned int);
30 } irq_cascade_t;
31
32 static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
33
34 static struct irqaction cascade_irqaction = {
35 .handler = no_action,
36 .name = "cascade",
37 .flags = IRQF_NO_THREAD,
38 };
39
cascade_irq(unsigned int irq,int (* get_irq)(unsigned int))40 int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
41 {
42 int retval = 0;
43
44 if (irq >= NR_IRQS)
45 return -EINVAL;
46
47 if (irq_cascade[irq].get_irq != NULL)
48 free_irq(irq, NULL);
49
50 irq_cascade[irq].get_irq = get_irq;
51
52 if (get_irq != NULL) {
53 retval = setup_irq(irq, &cascade_irqaction);
54 if (retval < 0)
55 irq_cascade[irq].get_irq = NULL;
56 }
57
58 return retval;
59 }
60
61 EXPORT_SYMBOL_GPL(cascade_irq);
62
irq_dispatch(unsigned int irq)63 static void irq_dispatch(unsigned int irq)
64 {
65 irq_cascade_t *cascade;
66
67 if (irq >= NR_IRQS) {
68 atomic_inc(&irq_err_count);
69 return;
70 }
71
72 cascade = irq_cascade + irq;
73 if (cascade->get_irq != NULL) {
74 struct irq_desc *desc = irq_to_desc(irq);
75 struct irq_data *idata = irq_desc_get_irq_data(desc);
76 struct irq_chip *chip = irq_desc_get_chip(desc);
77 int ret;
78
79 if (chip->irq_mask_ack)
80 chip->irq_mask_ack(idata);
81 else {
82 chip->irq_mask(idata);
83 chip->irq_ack(idata);
84 }
85 ret = cascade->get_irq(irq);
86 irq = ret;
87 if (ret < 0)
88 atomic_inc(&irq_err_count);
89 else
90 irq_dispatch(irq);
91 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
92 chip->irq_unmask(idata);
93 } else
94 do_IRQ(irq);
95 }
96
plat_irq_dispatch(void)97 asmlinkage void plat_irq_dispatch(void)
98 {
99 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
100
101 if (pending & CAUSEF_IP7)
102 do_IRQ(TIMER_IRQ);
103 else if (pending & 0x7800) {
104 if (pending & CAUSEF_IP3)
105 irq_dispatch(INT1_IRQ);
106 else if (pending & CAUSEF_IP4)
107 irq_dispatch(INT2_IRQ);
108 else if (pending & CAUSEF_IP5)
109 irq_dispatch(INT3_IRQ);
110 else if (pending & CAUSEF_IP6)
111 irq_dispatch(INT4_IRQ);
112 } else if (pending & CAUSEF_IP2)
113 irq_dispatch(INT0_IRQ);
114 else if (pending & CAUSEF_IP0)
115 do_IRQ(MIPS_SOFTINT0_IRQ);
116 else if (pending & CAUSEF_IP1)
117 do_IRQ(MIPS_SOFTINT1_IRQ);
118 else
119 spurious_interrupt();
120 }
121
arch_init_irq(void)122 void __init arch_init_irq(void)
123 {
124 mips_cpu_irq_init();
125 }
126