1 /*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/linkage.h>
21 #include <linux/interrupt.h>
22 #include <linux/spinlock.h>
23 #include <linux/smp.h>
24 #include <linux/mm.h>
25 #include <linux/kernel_stat.h>
26
27 #include <asm/errno.h>
28 #include <asm/signal.h>
29 #include <asm/system.h>
30 #include <asm/time.h>
31 #include <asm/io.h>
32
33 #include <asm/sibyte/sb1250_regs.h>
34 #include <asm/sibyte/sb1250_int.h>
35 #include <asm/sibyte/sb1250_uart.h>
36 #include <asm/sibyte/sb1250_scd.h>
37 #include <asm/sibyte/sb1250.h>
38
39 /*
40 * These are the routines that handle all the low level interrupt stuff.
41 * Actions handled here are: initialization of the interrupt map, requesting of
42 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
43 * for interrupt lines
44 */
45
46 #ifdef CONFIG_SIBYTE_HAS_LDT
47 extern unsigned long ldt_eoi_space;
48 #endif
49
50 /* Store the CPU id (not the logical number) */
51 int sb1250_irq_owner[SB1250_NR_IRQS];
52
53 static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
54
sb1250_mask_irq(int cpu,int irq)55 void sb1250_mask_irq(int cpu, int irq)
56 {
57 unsigned long flags;
58 u64 cur_ints;
59
60 raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
61 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
62 R_IMR_INTERRUPT_MASK));
63 cur_ints |= (((u64) 1) << irq);
64 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65 R_IMR_INTERRUPT_MASK));
66 raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
67 }
68
sb1250_unmask_irq(int cpu,int irq)69 void sb1250_unmask_irq(int cpu, int irq)
70 {
71 unsigned long flags;
72 u64 cur_ints;
73
74 raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
75 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
76 R_IMR_INTERRUPT_MASK));
77 cur_ints &= ~(((u64) 1) << irq);
78 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
79 R_IMR_INTERRUPT_MASK));
80 raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
81 }
82
83 #ifdef CONFIG_SMP
sb1250_set_affinity(struct irq_data * d,const struct cpumask * mask,bool force)84 static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
85 bool force)
86 {
87 int i = 0, old_cpu, cpu, int_on;
88 unsigned int irq = d->irq;
89 u64 cur_ints;
90 unsigned long flags;
91
92 i = cpumask_first(mask);
93
94 /* Convert logical CPU to physical CPU */
95 cpu = cpu_logical_map(i);
96
97 /* Protect against other affinity changers and IMR manipulation */
98 raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
99
100 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
101 old_cpu = sb1250_irq_owner[irq];
102 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
103 R_IMR_INTERRUPT_MASK));
104 int_on = !(cur_ints & (((u64) 1) << irq));
105 if (int_on) {
106 /* If it was on, mask it */
107 cur_ints |= (((u64) 1) << irq);
108 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
109 R_IMR_INTERRUPT_MASK));
110 }
111 sb1250_irq_owner[irq] = cpu;
112 if (int_on) {
113 /* unmask for the new CPU */
114 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
115 R_IMR_INTERRUPT_MASK));
116 cur_ints &= ~(((u64) 1) << irq);
117 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
118 R_IMR_INTERRUPT_MASK));
119 }
120 raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
121
122 return 0;
123 }
124 #endif
125
disable_sb1250_irq(struct irq_data * d)126 static void disable_sb1250_irq(struct irq_data *d)
127 {
128 unsigned int irq = d->irq;
129
130 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
131 }
132
enable_sb1250_irq(struct irq_data * d)133 static void enable_sb1250_irq(struct irq_data *d)
134 {
135 unsigned int irq = d->irq;
136
137 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
138 }
139
140
ack_sb1250_irq(struct irq_data * d)141 static void ack_sb1250_irq(struct irq_data *d)
142 {
143 unsigned int irq = d->irq;
144 #ifdef CONFIG_SIBYTE_HAS_LDT
145 u64 pending;
146
147 /*
148 * If the interrupt was an HT interrupt, now is the time to
149 * clear it. NOTE: we assume the HT bridge was set up to
150 * deliver the interrupts to all CPUs (which makes affinity
151 * changing easier for us)
152 */
153 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
154 R_IMR_LDT_INTERRUPT)));
155 pending &= ((u64)1 << (irq));
156 if (pending) {
157 int i;
158 for (i=0; i<NR_CPUS; i++) {
159 int cpu;
160 #ifdef CONFIG_SMP
161 cpu = cpu_logical_map(i);
162 #else
163 cpu = i;
164 #endif
165 /*
166 * Clear for all CPUs so an affinity switch
167 * doesn't find an old status
168 */
169 __raw_writeq(pending,
170 IOADDR(A_IMR_REGISTER(cpu,
171 R_IMR_LDT_INTERRUPT_CLR)));
172 }
173
174 /*
175 * Generate EOI. For Pass 1 parts, EOI is a nop. For
176 * Pass 2, the LDT world may be edge-triggered, but
177 * this EOI shouldn't hurt. If they are
178 * level-sensitive, the EOI is required.
179 */
180 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
181 }
182 #endif
183 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
184 }
185
186 static struct irq_chip sb1250_irq_type = {
187 .name = "SB1250-IMR",
188 .irq_mask_ack = ack_sb1250_irq,
189 .irq_unmask = enable_sb1250_irq,
190 .irq_mask = disable_sb1250_irq,
191 #ifdef CONFIG_SMP
192 .irq_set_affinity = sb1250_set_affinity
193 #endif
194 };
195
init_sb1250_irqs(void)196 void __init init_sb1250_irqs(void)
197 {
198 int i;
199
200 for (i = 0; i < SB1250_NR_IRQS; i++) {
201 irq_set_chip_and_handler(i, &sb1250_irq_type,
202 handle_level_irq);
203 sb1250_irq_owner[i] = 0;
204 }
205 }
206
207
208 /*
209 * arch_init_irq is called early in the boot sequence from init/main.c via
210 * init_IRQ. It is responsible for setting up the interrupt mapper and
211 * installing the handler that will be responsible for dispatching interrupts
212 * to the "right" place.
213 */
214 /*
215 * For now, map all interrupts to IP[2]. We could save
216 * some cycles by parceling out system interrupts to different
217 * IP lines, but keep it simple for bringup. We'll also direct
218 * all interrupts to a single CPU; we should probably route
219 * PCI and LDT to one cpu and everything else to the other
220 * to balance the load a bit.
221 *
222 * On the second cpu, everything is set to IP5, which is
223 * ignored, EXCEPT the mailbox interrupt. That one is
224 * set to IP[2] so it is handled. This is needed so we
225 * can do cross-cpu function calls, as required by SMP
226 */
227
228 #define IMR_IP2_VAL K_INT_MAP_I0
229 #define IMR_IP3_VAL K_INT_MAP_I1
230 #define IMR_IP4_VAL K_INT_MAP_I2
231 #define IMR_IP5_VAL K_INT_MAP_I3
232 #define IMR_IP6_VAL K_INT_MAP_I4
233
arch_init_irq(void)234 void __init arch_init_irq(void)
235 {
236
237 unsigned int i;
238 u64 tmp;
239 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
240 STATUSF_IP1 | STATUSF_IP0;
241
242 /* Default everything to IP2 */
243 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
244 __raw_writeq(IMR_IP2_VAL,
245 IOADDR(A_IMR_REGISTER(0,
246 R_IMR_INTERRUPT_MAP_BASE) +
247 (i << 3)));
248 __raw_writeq(IMR_IP2_VAL,
249 IOADDR(A_IMR_REGISTER(1,
250 R_IMR_INTERRUPT_MAP_BASE) +
251 (i << 3)));
252 }
253
254 init_sb1250_irqs();
255
256 /*
257 * Map the high 16 bits of the mailbox registers to IP[3], for
258 * inter-cpu messages
259 */
260 /* Was I1 */
261 __raw_writeq(IMR_IP3_VAL,
262 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
263 (K_INT_MBOX_0 << 3)));
264 __raw_writeq(IMR_IP3_VAL,
265 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
266 (K_INT_MBOX_0 << 3)));
267
268 /* Clear the mailboxes. The firmware may leave them dirty */
269 __raw_writeq(0xffffffffffffffffULL,
270 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
271 __raw_writeq(0xffffffffffffffffULL,
272 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
273
274 /* Mask everything except the mailbox registers for both cpus */
275 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
276 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
277 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
278
279 /*
280 * Note that the timer interrupts are also mapped, but this is
281 * done in sb1250_time_init(). Also, the profiling driver
282 * does its own management of IP7.
283 */
284
285 /* Enable necessary IPs, disable the rest */
286 change_c0_status(ST0_IM, imask);
287 }
288
289 extern void sb1250_mailbox_interrupt(void);
290
dispatch_ip2(void)291 static inline void dispatch_ip2(void)
292 {
293 unsigned int cpu = smp_processor_id();
294 unsigned long long mask;
295
296 /*
297 * Default...we've hit an IP[2] interrupt, which means we've got to
298 * check the 1250 interrupt registers to figure out what to do. Need
299 * to detect which CPU we're on, now that smp_affinity is supported.
300 */
301 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
302 R_IMR_INTERRUPT_STATUS_BASE)));
303 if (mask)
304 do_IRQ(fls64(mask) - 1);
305 }
306
plat_irq_dispatch(void)307 asmlinkage void plat_irq_dispatch(void)
308 {
309 unsigned int cpu = smp_processor_id();
310 unsigned int pending;
311
312 /*
313 * What a pain. We have to be really careful saving the upper 32 bits
314 * of any * register across function calls if we don't want them
315 * trashed--since were running in -o32, the calling routing never saves
316 * the full 64 bits of a register across a function call. Being the
317 * interrupt handler, we're guaranteed that interrupts are disabled
318 * during this code so we don't have to worry about random interrupts
319 * blasting the high 32 bits.
320 */
321
322 pending = read_c0_cause() & read_c0_status() & ST0_IM;
323
324 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
325 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
326 else if (pending & CAUSEF_IP4)
327 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
328
329 #ifdef CONFIG_SMP
330 else if (pending & CAUSEF_IP3)
331 sb1250_mailbox_interrupt();
332 #endif
333
334 else if (pending & CAUSEF_IP2)
335 dispatch_ip2();
336 else
337 spurious_interrupt();
338 }
339