1 /*
2 * linux/arch/m32r/platforms/usrv/setup.c
3 *
4 * Setup routines for MITSUBISHI uServer
5 *
6 * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto
8 */
9
10 #include <linux/irq.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13
14 #include <asm/system.h>
15 #include <asm/m32r.h>
16 #include <asm/io.h>
17
18 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
19
20 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
21
disable_mappi_irq(unsigned int irq)22 static void disable_mappi_irq(unsigned int irq)
23 {
24 unsigned long port, data;
25
26 port = irq2port(irq);
27 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
28 outl(data, port);
29 }
30
enable_mappi_irq(unsigned int irq)31 static void enable_mappi_irq(unsigned int irq)
32 {
33 unsigned long port, data;
34
35 port = irq2port(irq);
36 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
37 outl(data, port);
38 }
39
mask_mappi(struct irq_data * data)40 static void mask_mappi(struct irq_data *data)
41 {
42 disable_mappi_irq(data->irq);
43 }
44
unmask_mappi(struct irq_data * data)45 static void unmask_mappi(struct irq_data *data)
46 {
47 enable_mappi_irq(data->irq);
48 }
49
shutdown_mappi(struct irq_data * data)50 static void shutdown_mappi(struct irq_data *data)
51 {
52 unsigned long port;
53
54 port = irq2port(data->irq);
55 outl(M32R_ICUCR_ILEVEL7, port);
56 }
57
58 static struct irq_chip mappi_irq_type =
59 {
60 .name = "M32700-IRQ",
61 .irq_shutdown = shutdown_mappi,
62 .irq_mask = mask_mappi,
63 .irq_unmask = unmask_mappi,
64 };
65
66 /*
67 * Interrupt Control Unit of PLD on M32700UT (Level 2)
68 */
69 #define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
70 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
71 (((x) - 1) * sizeof(unsigned short)))
72
73 typedef struct {
74 unsigned short icucr; /* ICU Control Register */
75 } pld_icu_data_t;
76
77 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
78
disable_m32700ut_pld_irq(unsigned int irq)79 static void disable_m32700ut_pld_irq(unsigned int irq)
80 {
81 unsigned long port, data;
82 unsigned int pldirq;
83
84 pldirq = irq2pldirq(irq);
85 port = pldirq2port(pldirq);
86 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
87 outw(data, port);
88 }
89
enable_m32700ut_pld_irq(unsigned int irq)90 static void enable_m32700ut_pld_irq(unsigned int irq)
91 {
92 unsigned long port, data;
93 unsigned int pldirq;
94
95 pldirq = irq2pldirq(irq);
96 port = pldirq2port(pldirq);
97 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
98 outw(data, port);
99 }
100
mask_m32700ut_pld(struct irq_data * data)101 static void mask_m32700ut_pld(struct irq_data *data)
102 {
103 disable_m32700ut_pld_irq(data->irq);
104 }
105
unmask_m32700ut_pld(struct irq_data * data)106 static void unmask_m32700ut_pld(struct irq_data *data)
107 {
108 enable_m32700ut_pld_irq(data->irq);
109 enable_mappi_irq(M32R_IRQ_INT1);
110 }
111
shutdown_m32700ut_pld(struct irq_data * data)112 static void shutdown_m32700ut_pld(struct irq_data *data)
113 {
114 unsigned long port;
115 unsigned int pldirq;
116
117 pldirq = irq2pldirq(data->irq);
118 port = pldirq2port(pldirq);
119 outw(PLD_ICUCR_ILEVEL7, port);
120 }
121
122 static struct irq_chip m32700ut_pld_irq_type =
123 {
124 .name = "USRV-PLD-IRQ",
125 .irq_shutdown = shutdown_m32700ut_pld,
126 .irq_mask = mask_m32700ut_pld,
127 .irq_unmask = unmask_m32700ut_pld,
128 };
129
init_IRQ(void)130 void __init init_IRQ(void)
131 {
132 static int once = 0;
133 int i;
134
135 if (once)
136 return;
137 else
138 once++;
139
140 /* MFT2 : system timer */
141 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
142 handle_level_irq);
143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
144 disable_mappi_irq(M32R_IRQ_MFT2);
145
146 #if defined(CONFIG_SERIAL_M32R_SIO)
147 /* SIO0_R : uart receive data */
148 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
149 handle_level_irq);
150 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
151 disable_mappi_irq(M32R_IRQ_SIO0_R);
152
153 /* SIO0_S : uart send data */
154 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
155 handle_level_irq);
156 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
157 disable_mappi_irq(M32R_IRQ_SIO0_S);
158
159 /* SIO1_R : uart receive data */
160 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
161 handle_level_irq);
162 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
163 disable_mappi_irq(M32R_IRQ_SIO1_R);
164
165 /* SIO1_S : uart send data */
166 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
167 handle_level_irq);
168 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
169 disable_mappi_irq(M32R_IRQ_SIO1_S);
170 #endif /* CONFIG_SERIAL_M32R_SIO */
171
172 /* INT#67-#71: CFC#0 IREQ on PLD */
173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
174 irq_set_chip_and_handler(PLD_IRQ_CF0 + i,
175 &m32700ut_pld_irq_type,
176 handle_level_irq);
177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
178 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
179 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
180 }
181
182 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
183 /* INT#76: 16552D#0 IREQ on PLD */
184 irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
185 handle_level_irq);
186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
188 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
189
190 /* INT#77: 16552D#1 IREQ on PLD */
191 irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
192 handle_level_irq);
193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
195 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
196 #endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
197
198 #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
199 /* INT#80: AK4524 IREQ on PLD */
200 irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
201 handle_level_irq);
202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
204 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
205 #endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
206
207 /*
208 * INT1# is used for UART, MMC, CF Controller in FPGA.
209 * We enable it here.
210 */
211 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
212 enable_mappi_irq(M32R_IRQ_INT1);
213 }
214