1 /*
2 * Dynamic DMA mapping support.
3 */
4
5 #include <linux/types.h>
6 #include <linux/mm.h>
7 #include <linux/string.h>
8 #include <linux/pci.h>
9 #include <linux/module.h>
10 #include <linux/dmar.h>
11 #include <asm/iommu.h>
12 #include <asm/machvec.h>
13 #include <linux/dma-mapping.h>
14
15 #include <asm/system.h>
16
17 #ifdef CONFIG_INTEL_IOMMU
18
19 #include <linux/kernel.h>
20
21 #include <asm/page.h>
22
23 dma_addr_t bad_dma_address __read_mostly;
24 EXPORT_SYMBOL(bad_dma_address);
25
26 static int iommu_sac_force __read_mostly;
27
28 int no_iommu __read_mostly;
29 #ifdef CONFIG_IOMMU_DEBUG
30 int force_iommu __read_mostly = 1;
31 #else
32 int force_iommu __read_mostly;
33 #endif
34
35 int iommu_pass_through;
36 int iommu_group_mf;
37
38 /* Dummy device used for NULL arguments (normally ISA). Better would
39 be probably a smaller DMA mask, but this is bug-to-bug compatible
40 to i386. */
41 struct device fallback_dev = {
42 .init_name = "fallback device",
43 .coherent_dma_mask = DMA_BIT_MASK(32),
44 .dma_mask = &fallback_dev.coherent_dma_mask,
45 };
46
47 extern struct dma_map_ops intel_dma_ops;
48
pci_iommu_init(void)49 static int __init pci_iommu_init(void)
50 {
51 if (iommu_detected)
52 intel_iommu_init();
53
54 return 0;
55 }
56
57 /* Must execute after PCI subsystem */
58 fs_initcall(pci_iommu_init);
59
pci_iommu_shutdown(void)60 void pci_iommu_shutdown(void)
61 {
62 return;
63 }
64
65 void __init
iommu_dma_init(void)66 iommu_dma_init(void)
67 {
68 return;
69 }
70
iommu_dma_supported(struct device * dev,u64 mask)71 int iommu_dma_supported(struct device *dev, u64 mask)
72 {
73 /* Copied from i386. Doesn't make much sense, because it will
74 only work for pci_alloc_coherent.
75 The caller just has to use GFP_DMA in this case. */
76 if (mask < DMA_BIT_MASK(24))
77 return 0;
78
79 /* Tell the device to use SAC when IOMMU force is on. This
80 allows the driver to use cheaper accesses in some cases.
81
82 Problem with this is that if we overflow the IOMMU area and
83 return DAC as fallback address the device may not handle it
84 correctly.
85
86 As a special case some controllers have a 39bit address
87 mode that is as efficient as 32bit (aic79xx). Don't force
88 SAC for these. Assume all masks <= 40 bits are of this
89 type. Normally this doesn't make any difference, but gives
90 more gentle handling of IOMMU overflow. */
91 if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
92 dev_info(dev, "Force SAC with mask %llx\n", mask);
93 return 0;
94 }
95
96 return 1;
97 }
98 EXPORT_SYMBOL(iommu_dma_supported);
99
pci_iommu_alloc(void)100 void __init pci_iommu_alloc(void)
101 {
102 dma_ops = &intel_dma_ops;
103
104 dma_ops->sync_single_for_cpu = machvec_dma_sync_single;
105 dma_ops->sync_sg_for_cpu = machvec_dma_sync_sg;
106 dma_ops->sync_single_for_device = machvec_dma_sync_single;
107 dma_ops->sync_sg_for_device = machvec_dma_sync_sg;
108 dma_ops->dma_supported = iommu_dma_supported;
109
110 /*
111 * The order of these functions is important for
112 * fall-back/fail-over reasons
113 */
114 detect_intel_iommu();
115
116 #ifdef CONFIG_SWIOTLB
117 pci_swiotlb_init();
118 #endif
119 }
120
121 #endif
122