1 /* irq.c: FRV IRQ handling
2 *
3 * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/ioport.h>
17 #include <linux/interrupt.h>
18 #include <linux/timex.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/irq.h>
23 #include <linux/proc_fs.h>
24 #include <linux/seq_file.h>
25 #include <linux/module.h>
26 #include <linux/bitops.h>
27
28 #include <linux/atomic.h>
29 #include <asm/io.h>
30 #include <asm/smp.h>
31 #include <asm/system.h>
32 #include <asm/uaccess.h>
33 #include <asm/pgalloc.h>
34 #include <asm/delay.h>
35 #include <asm/irq.h>
36 #include <asm/irc-regs.h>
37 #include <asm/gdb-stub.h>
38
39 #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
40
41 extern void __init fpga_init(void);
42 #ifdef CONFIG_FUJITSU_MB93493
43 extern void __init mb93493_init(void);
44 #endif
45
46 #define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
47
48 atomic_t irq_err_count;
49
arch_show_interrupts(struct seq_file * p,int prec)50 int arch_show_interrupts(struct seq_file *p, int prec)
51 {
52 seq_printf(p, "%*s: ", prec, "ERR");
53 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
54 return 0;
55 }
56
57 /*
58 * on-CPU PIC operations
59 */
frv_cpupic_ack(struct irq_data * d)60 static void frv_cpupic_ack(struct irq_data *d)
61 {
62 __clr_RC(d->irq);
63 __clr_IRL();
64 }
65
frv_cpupic_mask(struct irq_data * d)66 static void frv_cpupic_mask(struct irq_data *d)
67 {
68 __set_MASK(d->irq);
69 }
70
frv_cpupic_mask_ack(struct irq_data * d)71 static void frv_cpupic_mask_ack(struct irq_data *d)
72 {
73 __set_MASK(d->irq);
74 __clr_RC(d->irq);
75 __clr_IRL();
76 }
77
frv_cpupic_unmask(struct irq_data * d)78 static void frv_cpupic_unmask(struct irq_data *d)
79 {
80 __clr_MASK(d->irq);
81 }
82
83 static struct irq_chip frv_cpu_pic = {
84 .name = "cpu",
85 .irq_ack = frv_cpupic_ack,
86 .irq_mask = frv_cpupic_mask,
87 .irq_mask_ack = frv_cpupic_mask_ack,
88 .irq_unmask = frv_cpupic_unmask,
89 };
90
91 /*
92 * handles all normal device IRQs
93 * - registers are referred to by the __frame variable (GR28)
94 * - IRQ distribution is complicated in this arch because of the many PICs, the
95 * way they work and the way they cascade
96 */
do_IRQ(void)97 asmlinkage void do_IRQ(void)
98 {
99 irq_enter();
100 generic_handle_irq(__get_IRL());
101 irq_exit();
102 }
103
104 /*
105 * handles all NMIs when not co-opted by the debugger
106 * - registers are referred to by the __frame variable (GR28)
107 */
do_NMI(void)108 asmlinkage void do_NMI(void)
109 {
110 }
111
112 /*
113 * initialise the interrupt system
114 */
init_IRQ(void)115 void __init init_IRQ(void)
116 {
117 int level;
118
119 for (level = 1; level <= 14; level++)
120 irq_set_chip_and_handler(level, &frv_cpu_pic,
121 handle_level_irq);
122
123 irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
124
125 /* set the trigger levels for internal interrupt sources
126 * - timers all falling-edge
127 * - ERR0 is rising-edge
128 * - all others are high-level
129 */
130 __set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 */
131 __set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 */
132
133 /* route internal interrupts */
134 set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL,
135 IRQ_DMA0_LEVEL);
136 set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
137 set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL,
138 IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
139 set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL,
140 IRQ_DMA4_LEVEL);
141
142 /* route external interrupts */
143 set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL,
144 IRQ_XIRQ4_LEVEL);
145 set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL,
146 IRQ_XIRQ0_LEVEL);
147
148 #if defined(CONFIG_MB93091_VDK)
149 __set_TM1(0x55550000); /* XIRQ7-0 all active low */
150 #elif defined(CONFIG_MB93093_PDK)
151 __set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
152 #else
153 #error dont know external IRQ trigger levels for this setup
154 #endif
155
156 fpga_init();
157 #ifdef CONFIG_FUJITSU_MB93493
158 mb93493_init();
159 #endif
160 }
161