1 /* 2 * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory 3 * 4 * Copyright 2004-2008 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9 #include <linux/linkage.h> 10 #include <linux/init.h> 11 #include <asm/blackfin.h> 12 13 #include <asm/dma.h> 14 #include <asm/clocks.h> 15 #include <asm/mem_init.h> 16 #include <asm/dpmc.h> 17 18 #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 19 #define PLL_CTL_VAL \ 20 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 21 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) 22 23 __attribute__((l1_text)) do_sync(void)24static void do_sync(void) 25 { 26 __builtin_bfin_ssync(); 27 } 28 29 __attribute__((l1_text)) init_clocks(void)30void init_clocks(void) 31 { 32 /* Kill any active DMAs as they may trigger external memory accesses 33 * in the middle of reprogramming things, and that'll screw us up. 34 * For example, any automatic DMAs left by U-Boot for splash screens. 35 */ 36 size_t i; 37 for (i = 0; i < MAX_DMA_CHANNELS; ++i) { 38 struct dma_register *dma = dma_io_base_addr[i]; 39 dma->cfg = 0; 40 } 41 42 do_sync(); 43 44 #ifdef SIC_IWR0 45 bfin_write_SIC_IWR0(IWR_ENABLE(0)); 46 # ifdef SIC_IWR1 47 /* BF52x system reset does not properly reset SIC_IWR1 which 48 * will screw up the bootrom as it relies on MDMA0/1 waking it 49 * up from IDLE instructions. See this report for more info: 50 * http://blackfin.uclinux.org/gf/tracker/4323 51 */ 52 if (ANOMALY_05000435) 53 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); 54 else 55 bfin_write_SIC_IWR1(IWR_DISABLE_ALL); 56 # endif 57 # ifdef SIC_IWR2 58 bfin_write_SIC_IWR2(IWR_DISABLE_ALL); 59 # endif 60 #else 61 bfin_write_SIC_IWR(IWR_ENABLE(0)); 62 #endif 63 do_sync(); 64 #ifdef EBIU_SDGCTL 65 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); 66 do_sync(); 67 #endif 68 69 #ifdef CLKBUFOE 70 bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); 71 do_sync(); 72 __asm__ __volatile__("IDLE;"); 73 #endif 74 bfin_write_PLL_LOCKCNT(0x300); 75 do_sync(); 76 /* We always write PLL_CTL thus avoiding Anomaly 05000242 */ 77 bfin_write16(PLL_CTL, PLL_CTL_VAL); 78 __asm__ __volatile__("IDLE;"); 79 bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); 80 #ifdef EBIU_SDGCTL 81 bfin_write_EBIU_SDRRC(mem_SDRRC); 82 bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); 83 #else 84 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); 85 do_sync(); 86 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); 87 bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); 88 bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); 89 bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); 90 #ifdef CONFIG_MEM_EBIU_DDRQUE 91 bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); 92 #endif 93 #endif 94 do_sync(); 95 bfin_read16(0); 96 } 97