1 /*
2  * DO NOT EDIT THIS FILE
3  * This file is under version control at
4  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5  * and can be replaced with that version at any time
6  * DO NOT EDIT THIS FILE
7  *
8  * Copyright 2004-2011 Analog Devices Inc.
9  * Licensed under the ADI BSD license.
10  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11  */
12 
13 /* This file should be up to date with:
14  *  - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
15  */
16 
17 #ifndef _MACH_ANOMALY_H_
18 #define _MACH_ANOMALY_H_
19 
20 /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
21 #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
22 # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
23 #endif
24 
25 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
26 #define ANOMALY_05000074 (1)
27 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
28 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
29 /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
30 #define ANOMALY_05000120 (1)
31 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
32 #define ANOMALY_05000122 (1)
33 /* SIGNBITS Instruction Not Functional under Certain Conditions */
34 #define ANOMALY_05000127 (1)
35 /* IMDMA S1/D1 Channel May Stall */
36 #define ANOMALY_05000149 (1)
37 /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
38 #define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
39 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
40 #define ANOMALY_05000166 (1)
41 /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
42 #define ANOMALY_05000167 (1)
43 /* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
44 #define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
45 /* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
46 #define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
47 /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
48 #define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
49 /* Cache Fill Buffer Data lost */
50 #define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
51 /* Overlapping Sequencer and Memory Stalls */
52 #define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
53 /* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
54 #define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
55 /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
56 #define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
57 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
58 #define ANOMALY_05000180 (1)
59 /* Disabling the PPI Resets the PPI Configuration Registers */
60 #define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
61 /* Internal Memory DMA Does Not Operate at Full Speed */
62 #define ANOMALY_05000182 (1)
63 /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
64 #define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
65 /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
66 #define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
67 /* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
68 #define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
69 /* IMDMA Corrupted Data after a Halt */
70 #define ANOMALY_05000187 (1)
71 /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
72 #define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
73 /* False Protection Exceptions when Speculative Fetch Is Cancelled */
74 #define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
75 /* PPI Not Functional at Core Voltage < 1Volt */
76 #define ANOMALY_05000190 (1)
77 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
78 #define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
79 /* Restarting SPORT in Specific Modes May Cause Data Corruption */
80 #define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
81 /* Failing MMR Accesses when Preceding Memory Read Stalls */
82 #define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
83 /* Current DMA Address Shows Wrong Value During Carry Fix */
84 #define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
85 /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
86 #define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
87 /* Possible Infinite Stall with Specific Dual-DAG Situation */
88 #define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
89 /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
90 #define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
91 /* Specific Sequence that Can Cause DMA Error or DMA Stopping */
92 #define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
93 /* Recovery from "Brown-Out" Condition */
94 #define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
95 /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
96 #define ANOMALY_05000208 (1)
97 /* Speed Path in Computational Unit Affects Certain Instructions */
98 #define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
99 /* UART TX Interrupt Masked Erroneously */
100 #define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
101 /* NMI Event at Boot Time Results in Unpredictable State */
102 #define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
103 /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
104 #define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
105 /* Incorrect Pulse-Width of UART Start Bit */
106 #define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
107 /* Scratchpad Memory Bank Reads May Return Incorrect Data */
108 #define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
109 /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
110 #define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
111 /* UART STB Bit Incorrectly Affects Receiver Setting */
112 #define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
113 /* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
114 #define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
115 /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
116 #define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
117 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
118 #define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
119 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
120 #define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
121 /* TESTSET Operation Forces Stall on the Other Core */
122 #define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
123 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
124 #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
125 /* Exception Not Generated for MMR Accesses in Reserved Region */
126 #define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
127 /* Maximum External Clock Speed for Timers */
128 #define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
129 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
130 #define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
131 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
132 /* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
133  * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
134  * after the behavior and the root cause are confirmed with hardware team.
135  */
136 #define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
137 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
138 #define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
139 /* ICPLB_STATUS MMR Register May Be Corrupted */
140 #define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
141 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
142 #define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
143 /* Stores To Data Cache May Be Lost */
144 #define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
145 /* Hardware Loop Corrupted When Taking an ICPLB Exception */
146 #define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
147 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
148 #define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
149 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
150 #define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
151 /* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
152 #define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
153 /* IMDMA May Corrupt Data under Certain Conditions */
154 #define ANOMALY_05000267 (1)
155 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
156 #define ANOMALY_05000269 (1)
157 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
158 #define ANOMALY_05000270 (1)
159 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
160 #define ANOMALY_05000272 (1)
161 /* Data Cache Write Back to External Synchronous Memory May Be Lost */
162 #define ANOMALY_05000274 (1)
163 /* PPI Timing and Sampling Information Updates */
164 #define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
165 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
166 #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
167 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
168 #define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
169 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
170 #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
171 /* False Hardware Error when ISR Context Is Not Restored */
172 /* Temporarily walk around for bug 5423 till this issue is confirmed by
173  * official anomaly document. It looks 05000281 still exists on bf561
174  * v0.5.
175  */
176 #define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
177 /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
178 #define ANOMALY_05000283 (1)
179 /* Reads Will Receive Incorrect Data under Certain Conditions */
180 #define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
181 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
182 #define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
183 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
184 #define ANOMALY_05000301 (1)
185 /* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
186 #define ANOMALY_05000302 (1)
187 /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
188 #define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
189 /* SCKELOW Bit Does Not Maintain State Through Hibernate */
190 #define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
191 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
192 #define ANOMALY_05000310 (1)
193 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
194 #define ANOMALY_05000312 (1)
195 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
196 #define ANOMALY_05000313 (1)
197 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
198 #define ANOMALY_05000315 (1)
199 /* PF2 Output Remains Asserted after SPI Master Boot */
200 #define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
201 /* Erroneous GPIO Flag Pin Operations under Specific Sequences */
202 #define ANOMALY_05000323 (1)
203 /* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
204 #define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
205 /* 24-Bit SPI Boot Mode Is Not Functional */
206 #define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
207 /* Slave SPI Boot Mode Is Not Functional */
208 #define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
209 /* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
210 #define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
211 /* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
212 #define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
213 /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
214 #define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
215 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
216 #define ANOMALY_05000357 (1)
217 /* Conflicting Column Address Widths Causes SDRAM Errors */
218 #define ANOMALY_05000362 (1)
219 /* UART Break Signal Issues */
220 #define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
221 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
222 #define ANOMALY_05000366 (1)
223 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
224 #define ANOMALY_05000371 (1)
225 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
226 #define ANOMALY_05000403 (1)
227 /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
228 #define ANOMALY_05000412 (1)
229 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
230 #define ANOMALY_05000416 (1)
231 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
232 #define ANOMALY_05000425 (1)
233 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
234 #define ANOMALY_05000426 (1)
235 /* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
236 #define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
237 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
238 #define ANOMALY_05000443 (1)
239 /* SCKELOW Feature Is Not Functional */
240 #define ANOMALY_05000458 (1)
241 /* False Hardware Error when RETI Points to Invalid Memory */
242 #define ANOMALY_05000461 (1)
243 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
244 #define ANOMALY_05000462 (1)
245 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
246 #define ANOMALY_05000471 (1)
247 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
248 #define ANOMALY_05000473 (1)
249 /* Possible Lockup Condition when Modifying PLL from External Memory */
250 #define ANOMALY_05000475 (1)
251 /* TESTSET Instruction Cannot Be Interrupted */
252 #define ANOMALY_05000477 (1)
253 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
254 #define ANOMALY_05000481 (1)
255 /* PLL May Latch Incorrect Values Coming Out of Reset */
256 #define ANOMALY_05000489 (1)
257 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
258 #define ANOMALY_05000491 (1)
259 /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
260 #define ANOMALY_05000494 (1)
261 /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
262 #define ANOMALY_05000501 (1)
263 
264 /*
265  * These anomalies have been "phased" out of analog.com anomaly sheets and are
266  * here to show running on older silicon just isn't feasible.
267  */
268 
269 /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
270 #define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
271 /* Erroneous Exception when Enabling Cache */
272 #define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
273 /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
274 #define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
275 /* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
276 #define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
277 /* Stall in multi-unit DMA operations */
278 #define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
279 /* Allowing the SPORT RX FIFO to fill will cause an overflow */
280 #define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
281 /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
282 #define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
283 /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
284 #define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
285 /* DMA and TESTSET conflict when both are accessing external memory */
286 #define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
287 /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
288 #define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
289 /* MDMA may lose the first few words of a descriptor chain */
290 #define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
291 /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
292 #define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
293 /* DMA engine may lose data due to incorrect handshaking */
294 #define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
295 /* DMA stalls when all three controllers read data from the same source */
296 #define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
297 /* Execution stall when executing in L2 and doing external accesses */
298 #define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
299 /* Frame Delay in SPORT Multichannel Mode */
300 #define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
301 /* SPORT TFS signal stays active in multichannel mode outside of valid channels */
302 #define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
303 /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
304 #define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
305 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
306 #define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
307 /* A read from external memory may return a wrong value with data cache enabled */
308 #define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
309 /* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
310 #define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
311 /* DMEM_CONTROL<12> is not set on Reset */
312 #define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
313 /* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
314 #define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
315 /* DSPID register values incorrect */
316 #define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
317 /* DMA vs Core accesses to external memory */
318 #define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
319 /* PPI does not invert the Driving PPICLK edge in Transmit Modes */
320 #define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
321 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
322 #define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
323 
324 /* Anomalies that don't exist on this proc */
325 #define ANOMALY_05000119 (0)
326 #define ANOMALY_05000158 (0)
327 #define ANOMALY_05000183 (0)
328 #define ANOMALY_05000233 (0)
329 #define ANOMALY_05000234 (0)
330 #define ANOMALY_05000273 (0)
331 #define ANOMALY_05000311 (0)
332 #define ANOMALY_05000353 (1)
333 #define ANOMALY_05000364 (0)
334 #define ANOMALY_05000380 (0)
335 #define ANOMALY_05000383 (0)
336 #define ANOMALY_05000386 (1)
337 #define ANOMALY_05000389 (0)
338 #define ANOMALY_05000400 (0)
339 #define ANOMALY_05000430 (0)
340 #define ANOMALY_05000432 (0)
341 #define ANOMALY_05000435 (0)
342 #define ANOMALY_05000440 (0)
343 #define ANOMALY_05000447 (0)
344 #define ANOMALY_05000448 (0)
345 #define ANOMALY_05000456 (0)
346 #define ANOMALY_05000450 (0)
347 #define ANOMALY_05000465 (0)
348 #define ANOMALY_05000467 (0)
349 #define ANOMALY_05000474 (0)
350 #define ANOMALY_05000480 (0)
351 #define ANOMALY_05000485 (0)
352 
353 #endif
354