1 /*
2 * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/interrupt.h>
10 #include <asm/bfin-global.h>
11 #include <asm/reboot.h>
12 #include <asm/system.h>
13 #include <asm/bfrom.h>
14
15 /* A system soft reset makes external memory unusable so force
16 * this function into L1. We use the compiler ssync here rather
17 * than SSYNC() because it's safe (no interrupts and such) and
18 * we save some L1. We do not need to force sanity in the SYSCR
19 * register as the BMODE selection bit is cleared by the soft
20 * reset while the Core B bit (on dual core parts) is cleared by
21 * the core reset.
22 */
23 __attribute__ ((__l1_text__, __noreturn__))
bfin_reset(void)24 static void bfin_reset(void)
25 {
26 if (!ANOMALY_05000353 && !ANOMALY_05000386)
27 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
28
29 /* Wait for completion of "system" events such as cache line
30 * line fills so that we avoid infinite stalls later on as
31 * much as possible. This code is in L1, so it won't trigger
32 * any such event after this point in time.
33 */
34 __builtin_bfin_ssync();
35
36 /* Initiate System software reset. */
37 bfin_write_SWRST(0x7);
38
39 /* Due to the way reset is handled in the hardware, we need
40 * to delay for 10 SCLKS. The only reliable way to do this is
41 * to calculate the CCLK/SCLK ratio and multiply 10. For now,
42 * we'll assume worse case which is a 1:15 ratio.
43 */
44 asm(
45 "LSETUP (1f, 1f) LC0 = %0\n"
46 "1: nop;"
47 :
48 : "a" (15 * 10)
49 : "LC0", "LB0", "LT0"
50 );
51
52 /* Clear System software reset */
53 bfin_write_SWRST(0);
54
55 /* The BF526 ROM will crash during reset */
56 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
57 /* Seems to be fixed with newer parts though ... */
58 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
59 bfin_read_SWRST();
60 #endif
61
62 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
63 * though as the System state is all reset now.
64 */
65 asm(
66 "LSETUP (1f, 1f) LC1 = %0\n"
67 "1: nop;"
68 :
69 : "a" (15 * 1)
70 : "LC1", "LB1", "LT1"
71 );
72
73 while (1)
74 /* Issue core reset */
75 asm("raise 1");
76 }
77
78 __attribute__((weak))
native_machine_restart(char * cmd)79 void native_machine_restart(char *cmd)
80 {
81 }
82
machine_restart(char * cmd)83 void machine_restart(char *cmd)
84 {
85 native_machine_restart(cmd);
86 local_irq_disable();
87 if (smp_processor_id())
88 smp_call_function((void *)bfin_reset, 0, 1);
89 else
90 bfin_reset();
91 }
92
93 __attribute__((weak))
native_machine_halt(void)94 void native_machine_halt(void)
95 {
96 idle_with_irq_disabled();
97 }
98
machine_halt(void)99 void machine_halt(void)
100 {
101 native_machine_halt();
102 }
103
104 __attribute__((weak))
native_machine_power_off(void)105 void native_machine_power_off(void)
106 {
107 idle_with_irq_disabled();
108 }
109
machine_power_off(void)110 void machine_power_off(void)
111 {
112 native_machine_power_off();
113 }
114