1 /* linux/arch/arm/plat-s3c24xx/cpu.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX CPU Support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/io.h>
33
34 #include <mach/hardware.h>
35 #include <asm/irq.h>
36 #include <asm/cacheflush.h>
37
38 #include <asm/mach/arch.h>
39 #include <asm/mach/map.h>
40
41 #include <mach/regs-gpio.h>
42 #include <plat/regs-serial.h>
43
44 #include <plat/cpu.h>
45 #include <plat/devs.h>
46 #include <plat/clock.h>
47 #include <plat/s3c2410.h>
48 #include <plat/s3c2412.h>
49 #include <plat/s3c2416.h>
50 #include <plat/s3c244x.h>
51 #include <plat/s3c2443.h>
52
53 /* table of supported CPUs */
54
55 static const char name_s3c2410[] = "S3C2410";
56 static const char name_s3c2412[] = "S3C2412";
57 static const char name_s3c2416[] = "S3C2416/S3C2450";
58 static const char name_s3c2440[] = "S3C2440";
59 static const char name_s3c2442[] = "S3C2442";
60 static const char name_s3c2442b[] = "S3C2442B";
61 static const char name_s3c2443[] = "S3C2443";
62 static const char name_s3c2410a[] = "S3C2410A";
63 static const char name_s3c2440a[] = "S3C2440A";
64
65 static struct cpu_table cpu_ids[] __initdata = {
66 {
67 .idcode = 0x32410000,
68 .idmask = 0xffffffff,
69 .map_io = s3c2410_map_io,
70 .init_clocks = s3c2410_init_clocks,
71 .init_uarts = s3c2410_init_uarts,
72 .init = s3c2410_init,
73 .name = name_s3c2410
74 },
75 {
76 .idcode = 0x32410002,
77 .idmask = 0xffffffff,
78 .map_io = s3c2410_map_io,
79 .init_clocks = s3c2410_init_clocks,
80 .init_uarts = s3c2410_init_uarts,
81 .init = s3c2410a_init,
82 .name = name_s3c2410a
83 },
84 {
85 .idcode = 0x32440000,
86 .idmask = 0xffffffff,
87 .map_io = s3c2440_map_io,
88 .init_clocks = s3c244x_init_clocks,
89 .init_uarts = s3c244x_init_uarts,
90 .init = s3c2440_init,
91 .name = name_s3c2440
92 },
93 {
94 .idcode = 0x32440001,
95 .idmask = 0xffffffff,
96 .map_io = s3c2440_map_io,
97 .init_clocks = s3c244x_init_clocks,
98 .init_uarts = s3c244x_init_uarts,
99 .init = s3c2440_init,
100 .name = name_s3c2440a
101 },
102 {
103 .idcode = 0x32440aaa,
104 .idmask = 0xffffffff,
105 .map_io = s3c2442_map_io,
106 .init_clocks = s3c244x_init_clocks,
107 .init_uarts = s3c244x_init_uarts,
108 .init = s3c2442_init,
109 .name = name_s3c2442
110 },
111 {
112 .idcode = 0x32440aab,
113 .idmask = 0xffffffff,
114 .map_io = s3c2442_map_io,
115 .init_clocks = s3c244x_init_clocks,
116 .init_uarts = s3c244x_init_uarts,
117 .init = s3c2442_init,
118 .name = name_s3c2442b
119 },
120 {
121 .idcode = 0x32412001,
122 .idmask = 0xffffffff,
123 .map_io = s3c2412_map_io,
124 .init_clocks = s3c2412_init_clocks,
125 .init_uarts = s3c2412_init_uarts,
126 .init = s3c2412_init,
127 .name = name_s3c2412,
128 },
129 { /* a newer version of the s3c2412 */
130 .idcode = 0x32412003,
131 .idmask = 0xffffffff,
132 .map_io = s3c2412_map_io,
133 .init_clocks = s3c2412_init_clocks,
134 .init_uarts = s3c2412_init_uarts,
135 .init = s3c2412_init,
136 .name = name_s3c2412,
137 },
138 { /* a strange version of the s3c2416 */
139 .idcode = 0x32450003,
140 .idmask = 0xffffffff,
141 .map_io = s3c2416_map_io,
142 .init_clocks = s3c2416_init_clocks,
143 .init_uarts = s3c2416_init_uarts,
144 .init = s3c2416_init,
145 .name = name_s3c2416,
146 },
147 {
148 .idcode = 0x32443001,
149 .idmask = 0xffffffff,
150 .map_io = s3c2443_map_io,
151 .init_clocks = s3c2443_init_clocks,
152 .init_uarts = s3c2443_init_uarts,
153 .init = s3c2443_init,
154 .name = name_s3c2443,
155 },
156 };
157
158 /* minimal IO mapping */
159
160 static struct map_desc s3c_iodesc[] __initdata = {
161 IODESC_ENT(GPIO),
162 IODESC_ENT(IRQ),
163 IODESC_ENT(MEMCTRL),
164 IODESC_ENT(UART)
165 };
166
167 /* read cpu identificaiton code */
168
s3c24xx_read_idcode_v5(void)169 static unsigned long s3c24xx_read_idcode_v5(void)
170 {
171 #if defined(CONFIG_CPU_S3C2416)
172 /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
173
174 u32 gs = __raw_readl(S3C24XX_GSTATUS1);
175
176 /* test for s3c2416 or similar device */
177 if ((gs >> 16) == 0x3245)
178 return gs;
179 #endif
180
181 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
182 return __raw_readl(S3C2412_GSTATUS1);
183 #else
184 return 1UL; /* don't look like an 2400 */
185 #endif
186 }
187
s3c24xx_read_idcode_v4(void)188 static unsigned long s3c24xx_read_idcode_v4(void)
189 {
190 return __raw_readl(S3C2410_GSTATUS1);
191 }
192
s3c24xx_init_io(struct map_desc * mach_desc,int size)193 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
194 {
195 /* initialise the io descriptors we need for initialisation */
196 iotable_init(mach_desc, size);
197 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
198
199 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
200 samsung_cpu_id = s3c24xx_read_idcode_v5();
201 } else {
202 samsung_cpu_id = s3c24xx_read_idcode_v4();
203 }
204 s3c24xx_init_cpu();
205
206 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
207 }
208