1 /* 2 * arch/arm/plat-omap/include/mach/mcbsp.h 3 * 4 * Defines for Multi-Channel Buffered Serial Port 5 * 6 * Copyright (C) 2002 RidgeRun, Inc. 7 * Author: Steve Johnson 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 #ifndef __ASM_ARCH_OMAP_MCBSP_H 25 #define __ASM_ARCH_OMAP_MCBSP_H 26 27 #include <linux/spinlock.h> 28 #include <linux/clk.h> 29 30 /* macro for building platform_device for McBSP ports */ 31 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ 32 static struct platform_device omap_mcbsp##port_nr = { \ 33 .name = "omap-mcbsp-dai", \ 34 .id = port_nr - 1, \ 35 } 36 37 #define MCBSP_CONFIG_TYPE2 0x2 38 #define MCBSP_CONFIG_TYPE3 0x3 39 #define MCBSP_CONFIG_TYPE4 0x4 40 41 /* McBSP register numbers. Register address offset = num * reg_step */ 42 enum { 43 /* Common registers */ 44 OMAP_MCBSP_REG_SPCR2 = 4, 45 OMAP_MCBSP_REG_SPCR1, 46 OMAP_MCBSP_REG_RCR2, 47 OMAP_MCBSP_REG_RCR1, 48 OMAP_MCBSP_REG_XCR2, 49 OMAP_MCBSP_REG_XCR1, 50 OMAP_MCBSP_REG_SRGR2, 51 OMAP_MCBSP_REG_SRGR1, 52 OMAP_MCBSP_REG_MCR2, 53 OMAP_MCBSP_REG_MCR1, 54 OMAP_MCBSP_REG_RCERA, 55 OMAP_MCBSP_REG_RCERB, 56 OMAP_MCBSP_REG_XCERA, 57 OMAP_MCBSP_REG_XCERB, 58 OMAP_MCBSP_REG_PCR0, 59 OMAP_MCBSP_REG_RCERC, 60 OMAP_MCBSP_REG_RCERD, 61 OMAP_MCBSP_REG_XCERC, 62 OMAP_MCBSP_REG_XCERD, 63 OMAP_MCBSP_REG_RCERE, 64 OMAP_MCBSP_REG_RCERF, 65 OMAP_MCBSP_REG_XCERE, 66 OMAP_MCBSP_REG_XCERF, 67 OMAP_MCBSP_REG_RCERG, 68 OMAP_MCBSP_REG_RCERH, 69 OMAP_MCBSP_REG_XCERG, 70 OMAP_MCBSP_REG_XCERH, 71 72 /* OMAP1-OMAP2420 registers */ 73 OMAP_MCBSP_REG_DRR2 = 0, 74 OMAP_MCBSP_REG_DRR1, 75 OMAP_MCBSP_REG_DXR2, 76 OMAP_MCBSP_REG_DXR1, 77 78 /* OMAP2430 and onwards */ 79 OMAP_MCBSP_REG_DRR = 0, 80 OMAP_MCBSP_REG_DXR = 2, 81 OMAP_MCBSP_REG_SYSCON = 35, 82 OMAP_MCBSP_REG_THRSH2, 83 OMAP_MCBSP_REG_THRSH1, 84 OMAP_MCBSP_REG_IRQST = 40, 85 OMAP_MCBSP_REG_IRQEN, 86 OMAP_MCBSP_REG_WAKEUPEN, 87 OMAP_MCBSP_REG_XCCR, 88 OMAP_MCBSP_REG_RCCR, 89 OMAP_MCBSP_REG_XBUFFSTAT, 90 OMAP_MCBSP_REG_RBUFFSTAT, 91 OMAP_MCBSP_REG_SSELCR, 92 }; 93 94 /* OMAP3 sidetone control registers */ 95 #define OMAP_ST_REG_REV 0x00 96 #define OMAP_ST_REG_SYSCONFIG 0x10 97 #define OMAP_ST_REG_IRQSTATUS 0x18 98 #define OMAP_ST_REG_IRQENABLE 0x1C 99 #define OMAP_ST_REG_SGAINCR 0x24 100 #define OMAP_ST_REG_SFIRCR 0x28 101 #define OMAP_ST_REG_SSELCR 0x2C 102 103 /************************** McBSP SPCR1 bit definitions ***********************/ 104 #define RRST 0x0001 105 #define RRDY 0x0002 106 #define RFULL 0x0004 107 #define RSYNC_ERR 0x0008 108 #define RINTM(value) ((value)<<4) /* bits 4:5 */ 109 #define ABIS 0x0040 110 #define DXENA 0x0080 111 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */ 112 #define RJUST(value) ((value)<<13) /* bits 13:14 */ 113 #define ALB 0x8000 114 #define DLB 0x8000 115 116 /************************** McBSP SPCR2 bit definitions ***********************/ 117 #define XRST 0x0001 118 #define XRDY 0x0002 119 #define XEMPTY 0x0004 120 #define XSYNC_ERR 0x0008 121 #define XINTM(value) ((value)<<4) /* bits 4:5 */ 122 #define GRST 0x0040 123 #define FRST 0x0080 124 #define SOFT 0x0100 125 #define FREE 0x0200 126 127 /************************** McBSP PCR bit definitions *************************/ 128 #define CLKRP 0x0001 129 #define CLKXP 0x0002 130 #define FSRP 0x0004 131 #define FSXP 0x0008 132 #define DR_STAT 0x0010 133 #define DX_STAT 0x0020 134 #define CLKS_STAT 0x0040 135 #define SCLKME 0x0080 136 #define CLKRM 0x0100 137 #define CLKXM 0x0200 138 #define FSRM 0x0400 139 #define FSXM 0x0800 140 #define RIOEN 0x1000 141 #define XIOEN 0x2000 142 #define IDLE_EN 0x4000 143 144 /************************** McBSP RCR1 bit definitions ************************/ 145 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */ 146 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */ 147 148 /************************** McBSP XCR1 bit definitions ************************/ 149 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */ 150 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */ 151 152 /*************************** McBSP RCR2 bit definitions ***********************/ 153 #define RDATDLY(value) (value) /* Bits 0:1 */ 154 #define RFIG 0x0004 155 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */ 156 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */ 157 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */ 158 #define RPHASE 0x8000 159 160 /*************************** McBSP XCR2 bit definitions ***********************/ 161 #define XDATDLY(value) (value) /* Bits 0:1 */ 162 #define XFIG 0x0004 163 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */ 164 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */ 165 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */ 166 #define XPHASE 0x8000 167 168 /************************* McBSP SRGR1 bit definitions ************************/ 169 #define CLKGDV(value) (value) /* Bits 0:7 */ 170 #define FWID(value) ((value)<<8) /* Bits 8:15 */ 171 172 /************************* McBSP SRGR2 bit definitions ************************/ 173 #define FPER(value) (value) /* Bits 0:11 */ 174 #define FSGM 0x1000 175 #define CLKSM 0x2000 176 #define CLKSP 0x4000 177 #define GSYNC 0x8000 178 179 /************************* McBSP MCR1 bit definitions *************************/ 180 #define RMCM 0x0001 181 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */ 182 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */ 183 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */ 184 185 /************************* McBSP MCR2 bit definitions *************************/ 186 #define XMCM(value) (value) /* Bits 0:1 */ 187 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */ 188 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */ 189 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ 190 191 /*********************** McBSP XCCR bit definitions *************************/ 192 #define EXTCLKGATE 0x8000 193 #define PPCONNECT 0x4000 194 #define DXENDLY(value) ((value)<<12) /* Bits 12:13 */ 195 #define XFULL_CYCLE 0x0800 196 #define DILB 0x0020 197 #define XDMAEN 0x0008 198 #define XDISABLE 0x0001 199 200 /********************** McBSP RCCR bit definitions *************************/ 201 #define RFULL_CYCLE 0x0800 202 #define RDMAEN 0x0008 203 #define RDISABLE 0x0001 204 205 /********************** McBSP SYSCONFIG bit definitions ********************/ 206 #define CLOCKACTIVITY(value) ((value)<<8) 207 #define SIDLEMODE(value) ((value)<<3) 208 #define ENAWAKEUP 0x0004 209 #define SOFTRST 0x0002 210 211 /********************** McBSP SSELCR bit definitions ***********************/ 212 #define SIDETONEEN 0x0400 213 214 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/ 215 #define ST_AUTOIDLE 0x0001 216 217 /********************** McBSP Sidetone SGAINCR bit definitions *************/ 218 #define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */ 219 #define ST_CH0GAIN(value) (value) /* Bits 0:15 */ 220 221 /********************** McBSP Sidetone SFIRCR bit definitions **************/ 222 #define ST_FIRCOEFF(value) (value) /* Bits 0:15 */ 223 224 /********************** McBSP Sidetone SSELCR bit definitions **************/ 225 #define ST_COEFFWRDONE 0x0004 226 #define ST_COEFFWREN 0x0002 227 #define ST_SIDETONEEN 0x0001 228 229 /********************** McBSP DMA operating modes **************************/ 230 #define MCBSP_DMA_MODE_ELEMENT 0 231 #define MCBSP_DMA_MODE_THRESHOLD 1 232 #define MCBSP_DMA_MODE_FRAME 2 233 234 /********************** McBSP WAKEUPEN bit definitions *********************/ 235 #define XEMPTYEOFEN 0x4000 236 #define XRDYEN 0x0400 237 #define XEOFEN 0x0200 238 #define XFSXEN 0x0100 239 #define XSYNCERREN 0x0080 240 #define RRDYEN 0x0008 241 #define REOFEN 0x0004 242 #define RFSREN 0x0002 243 #define RSYNCERREN 0x0001 244 245 /* CLKR signal muxing options */ 246 #define CLKR_SRC_CLKR 0 247 #define CLKR_SRC_CLKX 1 248 249 /* FSR signal muxing options */ 250 #define FSR_SRC_FSR 0 251 #define FSR_SRC_FSX 1 252 253 /* McBSP functional clock sources */ 254 #define MCBSP_CLKS_PRCM_SRC 0 255 #define MCBSP_CLKS_PAD_SRC 1 256 257 /* we don't do multichannel for now */ 258 struct omap_mcbsp_reg_cfg { 259 u16 spcr2; 260 u16 spcr1; 261 u16 rcr2; 262 u16 rcr1; 263 u16 xcr2; 264 u16 xcr1; 265 u16 srgr2; 266 u16 srgr1; 267 u16 mcr2; 268 u16 mcr1; 269 u16 pcr0; 270 u16 rcerc; 271 u16 rcerd; 272 u16 xcerc; 273 u16 xcerd; 274 u16 rcere; 275 u16 rcerf; 276 u16 xcere; 277 u16 xcerf; 278 u16 rcerg; 279 u16 rcerh; 280 u16 xcerg; 281 u16 xcerh; 282 u16 xccr; 283 u16 rccr; 284 }; 285 286 typedef enum { 287 OMAP_MCBSP_WORD_8 = 0, 288 OMAP_MCBSP_WORD_12, 289 OMAP_MCBSP_WORD_16, 290 OMAP_MCBSP_WORD_20, 291 OMAP_MCBSP_WORD_24, 292 OMAP_MCBSP_WORD_32, 293 } omap_mcbsp_word_length; 294 295 /* Platform specific configuration */ 296 struct omap_mcbsp_ops { 297 void (*request)(unsigned int); 298 void (*free)(unsigned int); 299 }; 300 301 struct omap_mcbsp_platform_data { 302 struct omap_mcbsp_ops *ops; 303 u16 buffer_size; 304 u8 reg_size; 305 u8 reg_step; 306 307 /* McBSP platform and instance specific features */ 308 bool has_wakeup; /* Wakeup capability */ 309 bool has_ccr; /* Transceiver has configuration control registers */ 310 int (*enable_st_clock)(unsigned int, bool); 311 int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src); 312 int (*mux_signal)(struct device *dev, const char *signal, const char *src); 313 }; 314 315 struct omap_mcbsp_st_data { 316 void __iomem *io_base_st; 317 bool running; 318 bool enabled; 319 s16 taps[128]; /* Sidetone filter coefficients */ 320 int nr_taps; /* Number of filter coefficients in use */ 321 s16 ch0gain; 322 s16 ch1gain; 323 }; 324 325 struct omap_mcbsp { 326 struct device *dev; 327 unsigned long phys_base; 328 unsigned long phys_dma_base; 329 void __iomem *io_base; 330 u8 id; 331 u8 free; 332 333 int rx_irq; 334 int tx_irq; 335 336 /* DMA stuff */ 337 u8 dma_rx_sync; 338 u8 dma_tx_sync; 339 340 /* Protect the field .free, while checking if the mcbsp is in use */ 341 spinlock_t lock; 342 struct omap_mcbsp_platform_data *pdata; 343 struct clk *fclk; 344 struct omap_mcbsp_st_data *st_data; 345 int dma_op_mode; 346 u16 max_tx_thres; 347 u16 max_rx_thres; 348 void *reg_cache; 349 int reg_cache_size; 350 }; 351 352 /** 353 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod 354 * @sidetone: name of the sidetone device 355 */ 356 struct omap_mcbsp_dev_attr { 357 const char *sidetone; 358 }; 359 360 extern struct omap_mcbsp **mcbsp_ptr; 361 extern int omap_mcbsp_count; 362 363 int omap_mcbsp_init(void); 364 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 365 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 366 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); 367 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); 368 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id); 369 u16 omap_mcbsp_get_fifo_size(unsigned int id); 370 u16 omap_mcbsp_get_tx_delay(unsigned int id); 371 u16 omap_mcbsp_get_rx_delay(unsigned int id); 372 int omap_mcbsp_get_dma_op_mode(unsigned int id); 373 int omap_mcbsp_request(unsigned int id); 374 void omap_mcbsp_free(unsigned int id); 375 void omap_mcbsp_start(unsigned int id, int tx, int rx); 376 void omap_mcbsp_stop(unsigned int id, int tx, int rx); 377 378 /* McBSP functional clock source changing function */ 379 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); 380 381 /* McBSP signal muxing API */ 382 void omap2_mcbsp1_mux_clkr_src(u8 mux); 383 void omap2_mcbsp1_mux_fsr_src(u8 mux); 384 385 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); 386 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); 387 388 /* Sidetone specific API */ 389 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 390 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); 391 int omap_st_enable(unsigned int id); 392 int omap_st_disable(unsigned int id); 393 int omap_st_is_enabled(unsigned int id); 394 395 #endif 396