1 /* 2 * arch/arm/plat-omap/include/mach/io.h 3 * 4 * IO definitions for TI OMAP processors and boards 5 * 6 * Copied from arch/arm/mach-sa1100/include/mach/io.h 7 * Copyright (C) 1997-1999 Russell King 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * You should have received a copy of the GNU General Public License along 29 * with this program; if not, write to the Free Software Foundation, Inc., 30 * 675 Mass Ave, Cambridge, MA 02139, USA. 31 * 32 * Modifications: 33 * 06-12-1997 RMK Created. 34 * 07-04-1999 RMK Major cleanup 35 */ 36 37 #ifndef __ASM_ARM_ARCH_IO_H 38 #define __ASM_ARM_ARCH_IO_H 39 40 #include <mach/hardware.h> 41 42 #define IO_SPACE_LIMIT 0xffffffff 43 44 /* 45 * We don't actually have real ISA nor PCI buses, but there is so many 46 * drivers out there that might just work if we fake them... 47 */ 48 #define __io(a) __typesafe_io(a) 49 #define __mem_pci(a) (a) 50 51 /* 52 * ---------------------------------------------------------------------------- 53 * I/O mapping 54 * ---------------------------------------------------------------------------- 55 */ 56 57 #ifdef __ASSEMBLER__ 58 #define IOMEM(x) (x) 59 #else 60 #define IOMEM(x) ((void __force __iomem *)(x)) 61 #endif 62 63 #define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 64 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) 65 66 #define OMAP2_L3_IO_OFFSET 0x90000000 67 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ 68 69 70 #define OMAP2_L4_IO_OFFSET 0xb2000000 71 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ 72 73 #define OMAP4_L3_IO_OFFSET 0xb4000000 74 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 75 76 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000 77 #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) 78 79 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 80 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) 81 82 #define OMAP4_GPMC_IO_OFFSET 0xa9000000 83 #define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) 84 85 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ 86 #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) 87 88 /* 89 * ---------------------------------------------------------------------------- 90 * Omap1 specific IO mapping 91 * ---------------------------------------------------------------------------- 92 */ 93 94 #define OMAP1_IO_PHYS 0xFFFB0000 95 #define OMAP1_IO_SIZE 0x40000 96 #define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) 97 98 /* 99 * ---------------------------------------------------------------------------- 100 * Omap2 specific IO mapping 101 * ---------------------------------------------------------------------------- 102 */ 103 104 /* We map both L3 and L4 on OMAP2 */ 105 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ 106 #define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) 107 #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 108 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ 109 #define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) 110 #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 111 112 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ 113 #define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) 114 #define L4_WK_243X_SIZE SZ_1M 115 #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE 116 #define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 117 /* 0x6e000000 --> 0xfe000000 */ 118 #define OMAP243X_GPMC_SIZE SZ_1M 119 #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE 120 /* 0x6D000000 --> 0xfd000000 */ 121 #define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 122 #define OMAP243X_SDRC_SIZE SZ_1M 123 #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE 124 /* 0x6c000000 --> 0xfc000000 */ 125 #define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 126 #define OMAP243X_SMS_SIZE SZ_1M 127 128 /* 2420 IVA */ 129 #define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE 130 /* 0x58000000 --> 0xfc100000 */ 131 #define DSP_MEM_2420_VIRT 0xfc100000 132 #define DSP_MEM_2420_SIZE 0x28000 133 #define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE 134 /* 0x59000000 --> 0xfc128000 */ 135 #define DSP_IPI_2420_VIRT 0xfc128000 136 #define DSP_IPI_2420_SIZE SZ_4K 137 #define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE 138 /* 0x5a000000 --> 0xfc129000 */ 139 #define DSP_MMU_2420_VIRT 0xfc129000 140 #define DSP_MMU_2420_SIZE SZ_4K 141 142 /* 2430 IVA2.1 - currently unmapped */ 143 144 /* 145 * ---------------------------------------------------------------------------- 146 * Omap3 specific IO mapping 147 * ---------------------------------------------------------------------------- 148 */ 149 150 /* We map both L3 and L4 on OMAP3 */ 151 #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ 152 #define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) 153 #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 154 155 #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ 156 #define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) 157 #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 158 159 /* 160 * ---------------------------------------------------------------------------- 161 * AM33XX specific IO mapping 162 * ---------------------------------------------------------------------------- 163 */ 164 #define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE 165 #define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET) 166 #define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 167 168 /* 169 * Need to look at the Size 4M for L4. 170 * VPOM3430 was not working for Int controller 171 */ 172 173 #define L4_PER_34XX_PHYS L4_PER_34XX_BASE 174 /* 0x49000000 --> 0xfb000000 */ 175 #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) 176 #define L4_PER_34XX_SIZE SZ_1M 177 178 #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE 179 /* 0x54000000 --> 0xfe800000 */ 180 #define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) 181 #define L4_EMU_34XX_SIZE SZ_8M 182 183 #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE 184 /* 0x6e000000 --> 0xfe000000 */ 185 #define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 186 #define OMAP34XX_GPMC_SIZE SZ_1M 187 188 #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE 189 /* 0x6c000000 --> 0xfc000000 */ 190 #define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 191 #define OMAP343X_SMS_SIZE SZ_1M 192 193 #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE 194 /* 0x6D000000 --> 0xfd000000 */ 195 #define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 196 #define OMAP343X_SDRC_SIZE SZ_1M 197 198 /* 3430 IVA - currently unmapped */ 199 200 /* 201 * ---------------------------------------------------------------------------- 202 * Omap4 specific IO mapping 203 * ---------------------------------------------------------------------------- 204 */ 205 206 /* We map both L3 and L4 on OMAP4 */ 207 #define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ 208 #define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) 209 #define L3_44XX_SIZE SZ_1M 210 211 #define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ 212 #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) 213 #define L4_44XX_SIZE SZ_4M 214 215 #define L4_PER_44XX_PHYS L4_PER_44XX_BASE 216 /* 0x48000000 --> 0xfa000000 */ 217 #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) 218 #define L4_PER_44XX_SIZE SZ_4M 219 220 #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE 221 /* 0x49000000 --> 0xfb000000 */ 222 #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) 223 #define L4_ABE_44XX_SIZE SZ_1M 224 225 #define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE 226 /* 0x54000000 --> 0xfe800000 */ 227 #define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) 228 #define L4_EMU_44XX_SIZE SZ_8M 229 230 #define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE 231 /* 0x50000000 --> 0xf9000000 */ 232 #define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) 233 #define OMAP44XX_GPMC_SIZE SZ_1M 234 235 236 #define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE 237 /* 0x4c000000 --> 0xfd100000 */ 238 #define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) 239 #define OMAP44XX_EMIF1_SIZE SZ_1M 240 241 #define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE 242 /* 0x4d000000 --> 0xfd200000 */ 243 #define OMAP44XX_EMIF2_SIZE SZ_1M 244 #define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE) 245 246 #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE 247 /* 0x4e000000 --> 0xfd300000 */ 248 #define OMAP44XX_DMM_SIZE SZ_1M 249 #define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE) 250 /* 251 * ---------------------------------------------------------------------------- 252 * Omap specific register access 253 * ---------------------------------------------------------------------------- 254 */ 255 256 #ifndef __ASSEMBLER__ 257 258 /* 259 * NOTE: Please use ioremap + __raw_read/write where possible instead of these 260 */ 261 262 extern u8 omap_readb(u32 pa); 263 extern u16 omap_readw(u32 pa); 264 extern u32 omap_readl(u32 pa); 265 extern void omap_writeb(u8 v, u32 pa); 266 extern void omap_writew(u16 v, u32 pa); 267 extern void omap_writel(u32 v, u32 pa); 268 269 struct omap_sdrc_params; 270 extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 271 struct omap_sdrc_params *sdrc_cs1); 272 273 extern void __init omap_init_consistent_dma_size(void); 274 275 #endif 276 277 #endif 278