1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv6 processor support. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable.h> 20 21#include "proc-macros.S" 22 23#define D_CACHE_LINE_SIZE 32 24 25#define TTB_C (1 << 0) 26#define TTB_S (1 << 1) 27#define TTB_IMP (1 << 2) 28#define TTB_RGN_NC (0 << 3) 29#define TTB_RGN_WBWA (1 << 3) 30#define TTB_RGN_WT (2 << 3) 31#define TTB_RGN_WB (3 << 3) 32 33#define TTB_FLAGS_UP TTB_RGN_WBWA 34#define PMD_FLAGS_UP PMD_SECT_WB 35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S 36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 37 38ENTRY(cpu_v6_proc_init) 39 mov pc, lr 40 41ENTRY(cpu_v6_proc_fin) 42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 43 bic r0, r0, #0x1000 @ ...i............ 44 bic r0, r0, #0x0006 @ .............ca. 45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 46 mov pc, lr 47 48/* 49 * cpu_v6_reset(loc) 50 * 51 * Perform a soft reset of the system. Put the CPU into the 52 * same state as it would be if it had been reset, and branch 53 * to what would be the reset vector. 54 * 55 * - loc - location to jump to for soft reset 56 */ 57 .align 5 58 .pushsection .idmap.text, "ax" 59ENTRY(cpu_v6_reset) 60 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 61 bic r1, r1, #0x1 @ ...............m 62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 63 mov r1, #0 64 mcr p15, 0, r1, c7, c5, 4 @ ISB 65 mov pc, r0 66ENDPROC(cpu_v6_reset) 67 .popsection 68 69/* 70 * cpu_v6_do_idle() 71 * 72 * Idle the processor (eg, wait for interrupt). 73 * 74 * IRQs are already disabled. 75 */ 76ENTRY(cpu_v6_do_idle) 77 mov r1, #0 78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 80 mov pc, lr 81 82ENTRY(cpu_v6_dcache_clean_area) 83#ifndef TLB_CAN_READ_FROM_L1_CACHE 841: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 85 add r0, r0, #D_CACHE_LINE_SIZE 86 subs r1, r1, #D_CACHE_LINE_SIZE 87 bhi 1b 88#endif 89 mov pc, lr 90 91/* 92 * cpu_arm926_switch_mm(pgd_phys, tsk) 93 * 94 * Set the translation table base pointer to be pgd_phys 95 * 96 * - pgd_phys - physical address of new TTB 97 * 98 * It is assumed that: 99 * - we are not using split page tables 100 */ 101ENTRY(cpu_v6_switch_mm) 102#ifdef CONFIG_MMU 103 mov r2, #0 104 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 105 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 106 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 107 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 108 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 109 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 110 mcr p15, 0, r1, c13, c0, 1 @ set context ID 111#endif 112 mov pc, lr 113 114/* 115 * cpu_v6_set_pte_ext(ptep, pte, ext) 116 * 117 * Set a level 2 translation table entry. 118 * 119 * - ptep - pointer to level 2 translation table entry 120 * (hardware version is stored at -1024 bytes) 121 * - pte - PTE value to store 122 * - ext - value for extended PTE bits 123 */ 124 armv6_mt_table cpu_v6 125 126ENTRY(cpu_v6_set_pte_ext) 127#ifdef CONFIG_MMU 128 armv6_set_pte_ext cpu_v6 129#endif 130 mov pc, lr 131 132/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 133.globl cpu_v6_suspend_size 134.equ cpu_v6_suspend_size, 4 * 6 135#ifdef CONFIG_PM_SLEEP 136ENTRY(cpu_v6_do_suspend) 137 stmfd sp!, {r4 - r9, lr} 138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 139 mrc p15, 0, r5, c3, c0, 0 @ Domain ID 140 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1 141 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register 142 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control 143 mrc p15, 0, r9, c1, c0, 0 @ control register 144 stmia r0, {r4 - r9} 145 ldmfd sp!, {r4- r9, pc} 146ENDPROC(cpu_v6_do_suspend) 147 148ENTRY(cpu_v6_do_resume) 149 mov ip, #0 150 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 151 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 152 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 153 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 154 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 155 ldmia r0, {r4 - r9} 156 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 157 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 158 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 159 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 160 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0 161 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1 162 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register 163 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control 164 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 165 mcr p15, 0, ip, c7, c5, 4 @ ISB 166 mov r0, r9 @ control register 167 b cpu_resume_mmu 168ENDPROC(cpu_v6_do_resume) 169#endif 170 171 string cpu_v6_name, "ARMv6-compatible processor" 172 173 .align 174 175 __CPUINIT 176 177/* 178 * __v6_setup 179 * 180 * Initialise TLB, Caches, and MMU state ready to switch the MMU 181 * on. Return in r0 the new CP15 C1 control register setting. 182 * 183 * We automatically detect if we have a Harvard cache, and use the 184 * Harvard cache control instructions insead of the unified cache 185 * control instructions. 186 * 187 * This should be able to cover all ARMv6 cores. 188 * 189 * It is assumed that: 190 * - cache type register is implemented 191 */ 192__v6_setup: 193#ifdef CONFIG_SMP 194 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode 195 ALT_UP(nop) 196 orr r0, r0, #0x20 197 ALT_SMP(mcr p15, 0, r0, c1, c0, 1) 198 ALT_UP(nop) 199#endif 200 201 mov r0, #0 202 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 203 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 204 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 205 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 206#ifdef CONFIG_MMU 207 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 208 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 209 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 210 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 211 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 212 ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 213 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 214#endif /* CONFIG_MMU */ 215 adr r5, v6_crval 216 ldmia r5, {r5, r6} 217#ifdef CONFIG_CPU_ENDIAN_BE8 218 orr r6, r6, #1 << 25 @ big-endian page tables 219#endif 220 mrc p15, 0, r0, c1, c0, 0 @ read control register 221 bic r0, r0, r5 @ clear bits them 222 orr r0, r0, r6 @ set them 223#ifdef CONFIG_ARM_ERRATA_364296 224 /* 225 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data 226 * corruption with hit-under-miss enabled). The conditional code below 227 * (setting the undocumented bit 31 in the auxiliary control register 228 * and the FI bit in the control register) disables hit-under-miss 229 * without putting the processor into full low interrupt latency mode. 230 */ 231 ldr r6, =0x4107b362 @ id for ARM1136 r0p2 232 mrc p15, 0, r5, c0, c0, 0 @ get processor id 233 teq r5, r6 @ check for the faulty core 234 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg 235 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 236 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg 237 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration 238#endif 239 mov pc, lr @ return to head.S:__ret 240 241 /* 242 * V X F I D LR 243 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 244 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 245 * 0 110 0011 1.00 .111 1101 < we want 246 */ 247 .type v6_crval, #object 248v6_crval: 249 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c 250 251 __INITDATA 252 253 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 254 define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1 255 256 .section ".rodata" 257 258 string cpu_arch_name, "armv6" 259 string cpu_elf_name, "v6" 260 .align 261 262 .section ".proc.info.init", #alloc, #execinstr 263 264 /* 265 * Match any ARMv6 processor core. 266 */ 267 .type __v6_proc_info, #object 268__v6_proc_info: 269 .long 0x0007b000 270 .long 0x0007f000 271 ALT_SMP(.long \ 272 PMD_TYPE_SECT | \ 273 PMD_SECT_AP_WRITE | \ 274 PMD_SECT_AP_READ | \ 275 PMD_FLAGS_SMP) 276 ALT_UP(.long \ 277 PMD_TYPE_SECT | \ 278 PMD_SECT_AP_WRITE | \ 279 PMD_SECT_AP_READ | \ 280 PMD_FLAGS_UP) 281 .long PMD_TYPE_SECT | \ 282 PMD_SECT_XN | \ 283 PMD_SECT_AP_WRITE | \ 284 PMD_SECT_AP_READ 285 b __v6_setup 286 .long cpu_arch_name 287 .long cpu_elf_name 288 /* See also feat_v6_fixup() for HWCAP_TLS */ 289 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS 290 .long cpu_v6_name 291 .long v6_processor_functions 292 .long v6wbi_tlb_fns 293 .long v6_user_fns 294 .long v6_cache_fns 295 .size __v6_proc_info, . - __v6_proc_info 296