1/*
2 *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
3 *
4 *  Written by : Luke Lee
5 *  Copyright (C) 2005 Faraday Corp.
6 *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 *
14 * These are the low level assembler for performing cache and TLB
15 * functions on the fa526.
16 */
17#include <linux/linkage.h>
18#include <linux/init.h>
19#include <asm/assembler.h>
20#include <asm/hwcap.h>
21#include <asm/pgtable-hwdef.h>
22#include <asm/pgtable.h>
23#include <asm/page.h>
24#include <asm/ptrace.h>
25#include <asm/system.h>
26
27#include "proc-macros.S"
28
29#define CACHE_DLINESIZE	16
30
31	.text
32/*
33 * cpu_fa526_proc_init()
34 */
35ENTRY(cpu_fa526_proc_init)
36	mov	pc, lr
37
38/*
39 * cpu_fa526_proc_fin()
40 */
41ENTRY(cpu_fa526_proc_fin)
42	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
43	bic	r0, r0, #0x1000			@ ...i............
44	bic	r0, r0, #0x000e			@ ............wca.
45	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
46	nop
47	nop
48	mov	pc, lr
49
50/*
51 * cpu_fa526_reset(loc)
52 *
53 * Perform a soft reset of the system.  Put the CPU into the
54 * same state as it would be if it had been reset, and branch
55 * to what would be the reset vector.
56 *
57 * loc: location to jump to for soft reset
58 */
59	.align	4
60	.pushsection	.idmap.text, "ax"
61ENTRY(cpu_fa526_reset)
62/* TODO: Use CP8 if possible... */
63	mov	ip, #0
64	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
65	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
66#ifdef CONFIG_MMU
67	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
68#endif
69	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
70	bic	ip, ip, #0x000f			@ ............wcam
71	bic	ip, ip, #0x1100			@ ...i...s........
72	bic	ip, ip, #0x0800			@ BTB off
73	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
74	nop
75	nop
76	mov	pc, r0
77ENDPROC(cpu_fa526_reset)
78	.popsection
79
80/*
81 * cpu_fa526_do_idle()
82 */
83	.align	4
84ENTRY(cpu_fa526_do_idle)
85	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
86	mov	pc, lr
87
88
89ENTRY(cpu_fa526_dcache_clean_area)
901:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
91	add	r0, r0, #CACHE_DLINESIZE
92	subs	r1, r1, #CACHE_DLINESIZE
93	bhi	1b
94	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
95	mov	pc, lr
96
97/* =============================== PageTable ============================== */
98
99/*
100 * cpu_fa526_switch_mm(pgd)
101 *
102 * Set the translation base pointer to be as described by pgd.
103 *
104 * pgd: new page tables
105 */
106	.align	4
107ENTRY(cpu_fa526_switch_mm)
108#ifdef CONFIG_MMU
109	mov	ip, #0
110#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
111	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
112#else
113	mcr	p15, 0, ip, c7, c14, 0		@ clean and invalidate whole D cache
114#endif
115	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
116	mcr	p15, 0, ip, c7, c5, 6		@ invalidate BTB since mm changed
117	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
118	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
119	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
120	mcr	p15, 0, ip, c8, c7, 0		@ invalidate UTLB
121#endif
122	mov	pc, lr
123
124/*
125 * cpu_fa526_set_pte_ext(ptep, pte, ext)
126 *
127 * Set a PTE and flush it out
128 */
129	.align	4
130ENTRY(cpu_fa526_set_pte_ext)
131#ifdef CONFIG_MMU
132	armv3_set_pte_ext
133	mov	r0, r0
134	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
135	mov	r0, #0
136	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
137#endif
138	mov	pc, lr
139
140	__CPUINIT
141
142	.type	__fa526_setup, #function
143__fa526_setup:
144	/* On return of this routine, r0 must carry correct flags for CFG register */
145	mov	r0, #0
146	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
147	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
148#ifdef CONFIG_MMU
149	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
150#endif
151	mcr	p15, 0, r0, c7, c5, 5		@ invalidate IScratchpad RAM
152
153	mov	r0, #1
154	mcr	p15, 0, r0, c1, c1, 0		@ turn-on ECR
155
156	mov	r0, #0
157	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB All
158	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
159	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
160
161	mov	r0, #0x1f			@ Domains 0, 1 = manager, 2 = client
162	mcr	p15, 0, r0, c3, c0		@ load domain access register
163
164	mrc	p15, 0, r0, c1, c0		@ get control register v4
165	ldr	r5, fa526_cr1_clear
166	bic	r0, r0, r5
167	ldr	r5, fa526_cr1_set
168	orr	r0, r0, r5
169	mov	pc, lr
170	.size	__fa526_setup, . - __fa526_setup
171
172	/*
173	 * .RVI ZFRS BLDP WCAM
174	 * ..11 1001 .111 1101
175	 *
176	 */
177	.type	fa526_cr1_clear, #object
178	.type	fa526_cr1_set, #object
179fa526_cr1_clear:
180	.word	0x3f3f
181fa526_cr1_set:
182	.word	0x397D
183
184	__INITDATA
185
186	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
187	define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
188
189	.section ".rodata"
190
191	string	cpu_arch_name, "armv4"
192	string	cpu_elf_name, "v4"
193	string	cpu_fa526_name, "FA526"
194
195	.align
196
197	.section ".proc.info.init", #alloc, #execinstr
198
199	.type	__fa526_proc_info,#object
200__fa526_proc_info:
201	.long	0x66015261
202	.long	0xff01fff1
203	.long   PMD_TYPE_SECT | \
204		PMD_SECT_BUFFERABLE | \
205		PMD_SECT_CACHEABLE | \
206		PMD_BIT4 | \
207		PMD_SECT_AP_WRITE | \
208		PMD_SECT_AP_READ
209	.long   PMD_TYPE_SECT | \
210		PMD_BIT4 | \
211		PMD_SECT_AP_WRITE | \
212		PMD_SECT_AP_READ
213	b	__fa526_setup
214	.long	cpu_arch_name
215	.long	cpu_elf_name
216	.long	HWCAP_SWP | HWCAP_HALF
217	.long	cpu_fa526_name
218	.long	fa526_processor_functions
219	.long	fa_tlb_fns
220	.long	fa_user_fns
221	.long	fa_cache_fns
222	.size	__fa526_proc_info, . - __fa526_proc_info
223