1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/clcd.h>
31 #include <linux/amba/pl061.h>
32 #include <linux/amba/mmci.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/io.h>
35 #include <linux/gfp.h>
36 #include <linux/clkdev.h>
37 #include <linux/mtd/physmap.h>
38
39 #include <asm/system.h>
40 #include <asm/irq.h>
41 #include <asm/leds.h>
42 #include <asm/hardware/arm_timer.h>
43 #include <asm/hardware/icst.h>
44 #include <asm/hardware/vic.h>
45 #include <asm/mach-types.h>
46
47 #include <asm/mach/arch.h>
48 #include <asm/mach/irq.h>
49 #include <asm/mach/time.h>
50 #include <asm/mach/map.h>
51 #include <mach/hardware.h>
52 #include <mach/platform.h>
53 #include <asm/hardware/timer-sp.h>
54
55 #include <plat/clcd.h>
56 #include <plat/fpga-irq.h>
57 #include <plat/sched_clock.h>
58
59 #include "core.h"
60
61 /*
62 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * is the (PA >> 12).
64 *
65 * Setup a VA for the Versatile Vectored Interrupt Controller.
66 */
67 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
68 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
69
70 static struct fpga_irq_data sic_irq = {
71 .base = VA_SIC_BASE,
72 .irq_start = IRQ_SIC_START,
73 .chip.name = "SIC",
74 };
75
76 #if 1
77 #define IRQ_MMCI0A IRQ_VICSOURCE22
78 #define IRQ_AACI IRQ_VICSOURCE24
79 #define IRQ_ETH IRQ_VICSOURCE25
80 #define PIC_MASK 0xFFD00000
81 #else
82 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
83 #define IRQ_AACI IRQ_SIC_AACI
84 #define IRQ_ETH IRQ_SIC_ETH
85 #define PIC_MASK 0
86 #endif
87
88 /* Lookup table for finding a DT node that represents the vic instance */
89 static const struct of_device_id vic_of_match[] __initconst = {
90 { .compatible = "arm,versatile-vic", },
91 {}
92 };
93
94 static const struct of_device_id sic_of_match[] __initconst = {
95 { .compatible = "arm,versatile-sic", },
96 {}
97 };
98
versatile_init_irq(void)99 void __init versatile_init_irq(void)
100 {
101 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
102 irq_domain_generate_simple(vic_of_match, VERSATILE_VIC_BASE, IRQ_VIC_START);
103
104 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
105
106 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
107 irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
108
109 /*
110 * Interrupts on secondary controller from 0 to 8 are routed to
111 * source 31 on PIC.
112 * Interrupts from 21 to 31 are routed directly to the VIC on
113 * the corresponding number on primary controller. This is controlled
114 * by setting PIC_ENABLEx.
115 */
116 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
117 }
118
119 static struct map_desc versatile_io_desc[] __initdata = {
120 {
121 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
122 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
123 .length = SZ_4K,
124 .type = MT_DEVICE
125 }, {
126 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
127 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
128 .length = SZ_4K,
129 .type = MT_DEVICE
130 }, {
131 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
132 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
133 .length = SZ_4K,
134 .type = MT_DEVICE
135 }, {
136 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
137 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
138 .length = SZ_4K * 9,
139 .type = MT_DEVICE
140 },
141 #ifdef CONFIG_MACH_VERSATILE_AB
142 {
143 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
144 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
145 .length = SZ_64M,
146 .type = MT_DEVICE
147 },
148 #endif
149 #ifdef CONFIG_DEBUG_LL
150 {
151 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
152 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
153 .length = SZ_4K,
154 .type = MT_DEVICE
155 },
156 #endif
157 #ifdef CONFIG_PCI
158 {
159 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
160 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
161 .length = SZ_4K,
162 .type = MT_DEVICE
163 }, {
164 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
165 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
166 .length = VERSATILE_PCI_BASE_SIZE,
167 .type = MT_DEVICE
168 }, {
169 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
170 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
171 .length = VERSATILE_PCI_CFG_BASE_SIZE,
172 .type = MT_DEVICE
173 },
174 #if 0
175 {
176 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
177 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
178 .length = SZ_16M,
179 .type = MT_DEVICE
180 }, {
181 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
182 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
183 .length = SZ_16M,
184 .type = MT_DEVICE
185 }, {
186 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
187 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
188 .length = SZ_16M,
189 .type = MT_DEVICE
190 },
191 #endif
192 #endif
193 };
194
versatile_map_io(void)195 void __init versatile_map_io(void)
196 {
197 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
198 }
199
200
201 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
202
versatile_flash_set_vpp(struct platform_device * pdev,int on)203 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
204 {
205 u32 val;
206
207 val = __raw_readl(VERSATILE_FLASHCTRL);
208 if (on)
209 val |= VERSATILE_FLASHPROG_FLVPPEN;
210 else
211 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
212 __raw_writel(val, VERSATILE_FLASHCTRL);
213 }
214
215 static struct physmap_flash_data versatile_flash_data = {
216 .width = 4,
217 .set_vpp = versatile_flash_set_vpp,
218 };
219
220 static struct resource versatile_flash_resource = {
221 .start = VERSATILE_FLASH_BASE,
222 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
223 .flags = IORESOURCE_MEM,
224 };
225
226 static struct platform_device versatile_flash_device = {
227 .name = "physmap-flash",
228 .id = 0,
229 .dev = {
230 .platform_data = &versatile_flash_data,
231 },
232 .num_resources = 1,
233 .resource = &versatile_flash_resource,
234 };
235
236 static struct resource smc91x_resources[] = {
237 [0] = {
238 .start = VERSATILE_ETH_BASE,
239 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
240 .flags = IORESOURCE_MEM,
241 },
242 [1] = {
243 .start = IRQ_ETH,
244 .end = IRQ_ETH,
245 .flags = IORESOURCE_IRQ,
246 },
247 };
248
249 static struct platform_device smc91x_device = {
250 .name = "smc91x",
251 .id = 0,
252 .num_resources = ARRAY_SIZE(smc91x_resources),
253 .resource = smc91x_resources,
254 };
255
256 static struct resource versatile_i2c_resource = {
257 .start = VERSATILE_I2C_BASE,
258 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
259 .flags = IORESOURCE_MEM,
260 };
261
262 static struct platform_device versatile_i2c_device = {
263 .name = "versatile-i2c",
264 .id = 0,
265 .num_resources = 1,
266 .resource = &versatile_i2c_resource,
267 };
268
269 static struct i2c_board_info versatile_i2c_board_info[] = {
270 {
271 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
272 },
273 };
274
versatile_i2c_init(void)275 static int __init versatile_i2c_init(void)
276 {
277 return i2c_register_board_info(0, versatile_i2c_board_info,
278 ARRAY_SIZE(versatile_i2c_board_info));
279 }
280 arch_initcall(versatile_i2c_init);
281
282 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
283
mmc_status(struct device * dev)284 unsigned int mmc_status(struct device *dev)
285 {
286 struct amba_device *adev = container_of(dev, struct amba_device, dev);
287 u32 mask;
288
289 if (adev->res.start == VERSATILE_MMCI0_BASE)
290 mask = 1;
291 else
292 mask = 2;
293
294 return readl(VERSATILE_SYSMCI) & mask;
295 }
296
297 static struct mmci_platform_data mmc0_plat_data = {
298 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
299 .status = mmc_status,
300 .gpio_wp = -1,
301 .gpio_cd = -1,
302 };
303
304 static struct resource char_lcd_resources[] = {
305 {
306 .start = VERSATILE_CHAR_LCD_BASE,
307 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
308 .flags = IORESOURCE_MEM,
309 },
310 };
311
312 static struct platform_device char_lcd_device = {
313 .name = "arm-charlcd",
314 .id = -1,
315 .num_resources = ARRAY_SIZE(char_lcd_resources),
316 .resource = char_lcd_resources,
317 };
318
319 /*
320 * Clock handling
321 */
322 static const struct icst_params versatile_oscvco_params = {
323 .ref = 24000000,
324 .vco_max = ICST307_VCO_MAX,
325 .vco_min = ICST307_VCO_MIN,
326 .vd_min = 4 + 8,
327 .vd_max = 511 + 8,
328 .rd_min = 1 + 2,
329 .rd_max = 127 + 2,
330 .s2div = icst307_s2div,
331 .idx2s = icst307_idx2s,
332 };
333
versatile_oscvco_set(struct clk * clk,struct icst_vco vco)334 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
335 {
336 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
337 u32 val;
338
339 val = readl(clk->vcoreg) & ~0x7ffff;
340 val |= vco.v | (vco.r << 9) | (vco.s << 16);
341
342 writel(0xa05f, sys_lock);
343 writel(val, clk->vcoreg);
344 writel(0, sys_lock);
345 }
346
347 static const struct clk_ops osc4_clk_ops = {
348 .round = icst_clk_round,
349 .set = icst_clk_set,
350 .setvco = versatile_oscvco_set,
351 };
352
353 static struct clk osc4_clk = {
354 .ops = &osc4_clk_ops,
355 .params = &versatile_oscvco_params,
356 };
357
358 /*
359 * These are fixed clocks.
360 */
361 static struct clk ref24_clk = {
362 .rate = 24000000,
363 };
364
365 static struct clk sp804_clk = {
366 .rate = 1000000,
367 };
368
369 static struct clk dummy_apb_pclk;
370
371 static struct clk_lookup lookups[] = {
372 { /* AMBA bus clock */
373 .con_id = "apb_pclk",
374 .clk = &dummy_apb_pclk,
375 }, { /* UART0 */
376 .dev_id = "dev:f1",
377 .clk = &ref24_clk,
378 }, { /* UART1 */
379 .dev_id = "dev:f2",
380 .clk = &ref24_clk,
381 }, { /* UART2 */
382 .dev_id = "dev:f3",
383 .clk = &ref24_clk,
384 }, { /* UART3 */
385 .dev_id = "fpga:09",
386 .clk = &ref24_clk,
387 }, { /* KMI0 */
388 .dev_id = "fpga:06",
389 .clk = &ref24_clk,
390 }, { /* KMI1 */
391 .dev_id = "fpga:07",
392 .clk = &ref24_clk,
393 }, { /* MMC0 */
394 .dev_id = "fpga:05",
395 .clk = &ref24_clk,
396 }, { /* MMC1 */
397 .dev_id = "fpga:0b",
398 .clk = &ref24_clk,
399 }, { /* SSP */
400 .dev_id = "dev:f4",
401 .clk = &ref24_clk,
402 }, { /* CLCD */
403 .dev_id = "dev:20",
404 .clk = &osc4_clk,
405 }, { /* SP804 timers */
406 .dev_id = "sp804",
407 .clk = &sp804_clk,
408 },
409 };
410
411 /*
412 * CLCD support.
413 */
414 #define SYS_CLCD_MODE_MASK (3 << 0)
415 #define SYS_CLCD_MODE_888 (0 << 0)
416 #define SYS_CLCD_MODE_5551 (1 << 0)
417 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
418 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
419 #define SYS_CLCD_NLCDIOON (1 << 2)
420 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
421 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
422 #define SYS_CLCD_ID_MASK (0x1f << 8)
423 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
424 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
425 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
426 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
427 #define SYS_CLCD_ID_VGA (0x1f << 8)
428
429 static bool is_sanyo_2_5_lcd;
430
431 /*
432 * Disable all display connectors on the interface module.
433 */
versatile_clcd_disable(struct clcd_fb * fb)434 static void versatile_clcd_disable(struct clcd_fb *fb)
435 {
436 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
437 u32 val;
438
439 val = readl(sys_clcd);
440 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
441 writel(val, sys_clcd);
442
443 #ifdef CONFIG_MACH_VERSATILE_AB
444 /*
445 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
446 */
447 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
448 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
449 unsigned long ctrl;
450
451 ctrl = readl(versatile_ib2_ctrl);
452 ctrl &= ~0x01;
453 writel(ctrl, versatile_ib2_ctrl);
454 }
455 #endif
456 }
457
458 /*
459 * Enable the relevant connector on the interface module.
460 */
versatile_clcd_enable(struct clcd_fb * fb)461 static void versatile_clcd_enable(struct clcd_fb *fb)
462 {
463 struct fb_var_screeninfo *var = &fb->fb.var;
464 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
465 u32 val;
466
467 val = readl(sys_clcd);
468 val &= ~SYS_CLCD_MODE_MASK;
469
470 switch (var->green.length) {
471 case 5:
472 val |= SYS_CLCD_MODE_5551;
473 break;
474 case 6:
475 if (var->red.offset == 0)
476 val |= SYS_CLCD_MODE_565_RLSB;
477 else
478 val |= SYS_CLCD_MODE_565_BLSB;
479 break;
480 case 8:
481 val |= SYS_CLCD_MODE_888;
482 break;
483 }
484
485 /*
486 * Set the MUX
487 */
488 writel(val, sys_clcd);
489
490 /*
491 * And now enable the PSUs
492 */
493 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
494 writel(val, sys_clcd);
495
496 #ifdef CONFIG_MACH_VERSATILE_AB
497 /*
498 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
499 */
500 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
501 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
502 unsigned long ctrl;
503
504 ctrl = readl(versatile_ib2_ctrl);
505 ctrl |= 0x01;
506 writel(ctrl, versatile_ib2_ctrl);
507 }
508 #endif
509 }
510
511 /*
512 * Detect which LCD panel is connected, and return the appropriate
513 * clcd_panel structure. Note: we do not have any information on
514 * the required timings for the 8.4in panel, so we presently assume
515 * VGA timings.
516 */
versatile_clcd_setup(struct clcd_fb * fb)517 static int versatile_clcd_setup(struct clcd_fb *fb)
518 {
519 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
520 const char *panel_name;
521 u32 val;
522
523 is_sanyo_2_5_lcd = false;
524
525 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
526 if (val == SYS_CLCD_ID_SANYO_3_8)
527 panel_name = "Sanyo TM38QV67A02A";
528 else if (val == SYS_CLCD_ID_SANYO_2_5) {
529 panel_name = "Sanyo QVGA Portrait";
530 is_sanyo_2_5_lcd = true;
531 } else if (val == SYS_CLCD_ID_EPSON_2_2)
532 panel_name = "Epson L2F50113T00";
533 else if (val == SYS_CLCD_ID_VGA)
534 panel_name = "VGA";
535 else {
536 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
537 val);
538 panel_name = "VGA";
539 }
540
541 fb->panel = versatile_clcd_get_panel(panel_name);
542 if (!fb->panel)
543 return -EINVAL;
544
545 return versatile_clcd_setup_dma(fb, SZ_1M);
546 }
547
versatile_clcd_decode(struct clcd_fb * fb,struct clcd_regs * regs)548 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
549 {
550 clcdfb_decode(fb, regs);
551
552 /* Always clear BGR for RGB565: we do the routing externally */
553 if (fb->fb.var.green.length == 6)
554 regs->cntl &= ~CNTL_BGR;
555 }
556
557 static struct clcd_board clcd_plat_data = {
558 .name = "Versatile",
559 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
560 .check = clcdfb_check,
561 .decode = versatile_clcd_decode,
562 .disable = versatile_clcd_disable,
563 .enable = versatile_clcd_enable,
564 .setup = versatile_clcd_setup,
565 .mmap = versatile_clcd_mmap_dma,
566 .remove = versatile_clcd_remove_dma,
567 };
568
569 static struct pl061_platform_data gpio0_plat_data = {
570 .gpio_base = 0,
571 .irq_base = IRQ_GPIO0_START,
572 };
573
574 static struct pl061_platform_data gpio1_plat_data = {
575 .gpio_base = 8,
576 .irq_base = IRQ_GPIO1_START,
577 };
578
579 static struct pl022_ssp_controller ssp0_plat_data = {
580 .bus_id = 0,
581 .enable_dma = 0,
582 .num_chipselect = 1,
583 };
584
585 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
586 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
587 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
588 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
589
590 /*
591 * These devices are connected directly to the multi-layer AHB switch
592 */
593 #define SMC_IRQ { NO_IRQ, NO_IRQ }
594 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
595 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
596 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
597
598 /*
599 * These devices are connected via the core APB bridge
600 */
601 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
602 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
603 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
604 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
605 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
606
607 /*
608 * These devices are connected via the DMA APB bridge
609 */
610 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
611 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
612 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
613 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
614 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
615
616 /* FPGA Primecells */
617 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
618 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
619 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
620 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
621
622 /* DevChip Primecells */
623 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
624 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
625 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
626 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
627 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
628 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
629 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
630 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
631 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
632 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
633 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
634 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
635 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
636 AMBA_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
637
638 static struct amba_device *amba_devs[] __initdata = {
639 &dmac_device,
640 &uart0_device,
641 &uart1_device,
642 &uart2_device,
643 &smc_device,
644 &mpmc_device,
645 &clcd_device,
646 &sctl_device,
647 &wdog_device,
648 &gpio0_device,
649 &gpio1_device,
650 &rtc_device,
651 &sci0_device,
652 &ssp0_device,
653 &aaci_device,
654 &mmc0_device,
655 &kmi0_device,
656 &kmi1_device,
657 };
658
659 #ifdef CONFIG_OF
660 /*
661 * Lookup table for attaching a specific name and platform_data pointer to
662 * devices as they get created by of_platform_populate(). Ideally this table
663 * would not exist, but the current clock implementation depends on some devices
664 * having a specific name.
665 */
666 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
667 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
672
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
677 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
678
679 #if 0
680 /*
681 * These entries are unnecessary because no clocks referencing
682 * them. I've left them in for now as place holders in case
683 * any of them need to be added back, but they should be
684 * removed before actually committing this patch. --gcl
685 */
686 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
687 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
688 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
689 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
690 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
691
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
694 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
695 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
696 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
697 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
698 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
699 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
700 #endif
701 {}
702 };
703 #endif
704
705 #ifdef CONFIG_LEDS
706 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
707
versatile_leds_event(led_event_t ledevt)708 static void versatile_leds_event(led_event_t ledevt)
709 {
710 unsigned long flags;
711 u32 val;
712
713 local_irq_save(flags);
714 val = readl(VA_LEDS_BASE);
715
716 switch (ledevt) {
717 case led_idle_start:
718 val = val & ~VERSATILE_SYS_LED0;
719 break;
720
721 case led_idle_end:
722 val = val | VERSATILE_SYS_LED0;
723 break;
724
725 case led_timer:
726 val = val ^ VERSATILE_SYS_LED1;
727 break;
728
729 case led_halted:
730 val = 0;
731 break;
732
733 default:
734 break;
735 }
736
737 writel(val, VA_LEDS_BASE);
738 local_irq_restore(flags);
739 }
740 #endif /* CONFIG_LEDS */
741
versatile_restart(char mode,const char * cmd)742 void versatile_restart(char mode, const char *cmd)
743 {
744 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
745 u32 val;
746
747 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
748 val |= 0x105;
749
750 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
751 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
752 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
753 }
754
755 /* Early initializations */
versatile_init_early(void)756 void __init versatile_init_early(void)
757 {
758 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
759
760 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
761 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
762
763 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
764 }
765
versatile_init(void)766 void __init versatile_init(void)
767 {
768 int i;
769
770 platform_device_register(&versatile_flash_device);
771 platform_device_register(&versatile_i2c_device);
772 platform_device_register(&smc91x_device);
773 platform_device_register(&char_lcd_device);
774
775 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
776 struct amba_device *d = amba_devs[i];
777 amba_device_register(d, &iomem_resource);
778 }
779
780 #ifdef CONFIG_LEDS
781 leds_event = versatile_leds_event;
782 #endif
783 }
784
785 /*
786 * Where is the timer (VA)?
787 */
788 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
789 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
790 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
791 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
792
793 /*
794 * Set up timer interrupt, and return the current time in seconds.
795 */
versatile_timer_init(void)796 static void __init versatile_timer_init(void)
797 {
798 u32 val;
799
800 /*
801 * set clock frequency:
802 * VERSATILE_REFCLK is 32KHz
803 * VERSATILE_TIMCLK is 1MHz
804 */
805 val = readl(__io_address(VERSATILE_SCTL_BASE));
806 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
807 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
808 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
809 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
810 __io_address(VERSATILE_SCTL_BASE));
811
812 /*
813 * Initialise to a known state (all timers off)
814 */
815 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
816 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
817 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
818 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
819
820 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
821 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
822 }
823
824 struct sys_timer versatile_timer = {
825 .init = versatile_timer_init,
826 };
827
828