1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> 5 * License terms: GNU General Public License (GPL) version 2 6 */ 7 8 #ifndef __MACH_IRQS_DB5500_H 9 #define __MACH_IRQS_DB5500_H 10 11 #define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4) 12 #define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6) 13 #define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7) 14 #define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8) 15 #define IRQ_DB5500_RTT (IRQ_SHPI_START + 9) 16 #define IRQ_DB5500_PKA (IRQ_SHPI_START + 10) 17 #define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11) 18 #define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12) 19 #define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13) 20 #define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14) 21 #define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15) 22 #define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16) 23 #define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17) 24 #define IRQ_DB5500_RTC (IRQ_SHPI_START + 18) 25 #define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19) 26 #define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20) 27 #define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21) 28 #define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22) 29 #define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23) 30 #define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24) 31 #define IRQ_DB5500_DMA (IRQ_SHPI_START + 25) 32 #define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26) 33 #define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27) 34 #define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28) 35 #define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29) 36 #define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30) 37 #define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31) 38 #define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33) 39 #define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34) 40 #define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35) 41 #define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36) 42 #define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37) 43 #define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38) 44 #define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39) 45 #define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40) 46 #define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41) 47 #define IRQ_DB5500_SIA (IRQ_SHPI_START + 42) 48 #define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43) 49 #define IRQ_DB5500_HVA (IRQ_SHPI_START + 44) 50 #define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45) 51 #define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46) 52 #define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47) 53 #define IRQ_DB5500_DISP (IRQ_SHPI_START + 48) 54 #define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50) 55 #define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52) 56 #define IRQ_DB5500_KBD (IRQ_SHPI_START + 53) 57 #define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55) 58 #define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56) 59 #define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57) 60 #define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59) 61 #define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) 62 #define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) 63 #define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) 64 #define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65) 65 #define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) 66 #define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) 67 #define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) 68 #define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108) 69 #define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109) 70 #define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110) 71 #define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112) 72 #define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113) 73 #define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114) 74 #define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115) 75 #define IRQ_DB5500_MALI (IRQ_SHPI_START + 116) 76 #define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118) 77 #define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119) 78 #define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120) 79 #define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121) 80 #define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122) 81 #define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123) 82 #define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124) 83 #define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125) 84 #define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126) 85 86 #ifdef CONFIG_UX500_SOC_DB5500 87 88 /* 89 * After the GPIO ones we reserve a range of IRQ:s in which virtual 90 * IRQ:s representing modem IRQ:s can be allocated 91 */ 92 #define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START 93 #define IRQ_MODEM_EVENTS_NBR 72 94 #define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR) 95 96 /* List of virtual IRQ:s that are allocated from the range above */ 97 #define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43) 98 #define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45) 99 #define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41) 100 101 /* 102 * We may have several SoCs, but only one will run at a 103 * time, so the one with most IRQs will bump this ahead, 104 * but the IRQ_SOC_START remains the same for either SoC. 105 */ 106 #if IRQ_SOC_END < IRQ_MODEM_EVENTS_END 107 #undef IRQ_SOC_END 108 #define IRQ_SOC_END IRQ_MODEM_EVENTS_END 109 #endif 110 111 #endif /* CONFIG_UX500_SOC_DB5500 */ 112 113 #endif 114