1 /*
2 * drivers/powergate/tegra-powergate.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/debugfs.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/seq_file.h>
28 #include <linux/spinlock.h>
29
30 #include <mach/clk.h>
31 #include <mach/iomap.h>
32 #include <mach/powergate.h>
33
34 #define PWRGATE_TOGGLE 0x30
35 #define PWRGATE_TOGGLE_START (1 << 8)
36
37 #define REMOVE_CLAMPING 0x34
38
39 #define PWRGATE_STATUS 0x38
40
41 static DEFINE_SPINLOCK(tegra_powergate_lock);
42
43 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
44
pmc_read(unsigned long reg)45 static u32 pmc_read(unsigned long reg)
46 {
47 return readl(pmc + reg);
48 }
49
pmc_write(u32 val,unsigned long reg)50 static void pmc_write(u32 val, unsigned long reg)
51 {
52 writel(val, pmc + reg);
53 }
54
tegra_powergate_set(int id,bool new_state)55 static int tegra_powergate_set(int id, bool new_state)
56 {
57 bool status;
58 unsigned long flags;
59
60 spin_lock_irqsave(&tegra_powergate_lock, flags);
61
62 status = pmc_read(PWRGATE_STATUS) & (1 << id);
63
64 if (status == new_state) {
65 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
66 return -EINVAL;
67 }
68
69 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
70
71 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
72
73 return 0;
74 }
75
tegra_powergate_power_on(int id)76 int tegra_powergate_power_on(int id)
77 {
78 if (id < 0 || id >= TEGRA_NUM_POWERGATE)
79 return -EINVAL;
80
81 return tegra_powergate_set(id, true);
82 }
83
tegra_powergate_power_off(int id)84 int tegra_powergate_power_off(int id)
85 {
86 if (id < 0 || id >= TEGRA_NUM_POWERGATE)
87 return -EINVAL;
88
89 return tegra_powergate_set(id, false);
90 }
91
tegra_powergate_is_powered(int id)92 static bool tegra_powergate_is_powered(int id)
93 {
94 u32 status;
95
96 WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
97
98 status = pmc_read(PWRGATE_STATUS) & (1 << id);
99 return !!status;
100 }
101
tegra_powergate_remove_clamping(int id)102 int tegra_powergate_remove_clamping(int id)
103 {
104 u32 mask;
105
106 if (id < 0 || id >= TEGRA_NUM_POWERGATE)
107 return -EINVAL;
108
109 /*
110 * Tegra 2 has a bug where PCIE and VDE clamping masks are
111 * swapped relatively to the partition ids
112 */
113 if (id == TEGRA_POWERGATE_VDEC)
114 mask = (1 << TEGRA_POWERGATE_PCIE);
115 else if (id == TEGRA_POWERGATE_PCIE)
116 mask = (1 << TEGRA_POWERGATE_VDEC);
117 else
118 mask = (1 << id);
119
120 pmc_write(mask, REMOVE_CLAMPING);
121
122 return 0;
123 }
124
125 /* Must be called with clk disabled, and returns with clk enabled */
tegra_powergate_sequence_power_up(int id,struct clk * clk)126 int tegra_powergate_sequence_power_up(int id, struct clk *clk)
127 {
128 int ret;
129
130 tegra_periph_reset_assert(clk);
131
132 ret = tegra_powergate_power_on(id);
133 if (ret)
134 goto err_power;
135
136 ret = clk_enable(clk);
137 if (ret)
138 goto err_clk;
139
140 udelay(10);
141
142 ret = tegra_powergate_remove_clamping(id);
143 if (ret)
144 goto err_clamp;
145
146 udelay(10);
147 tegra_periph_reset_deassert(clk);
148
149 return 0;
150
151 err_clamp:
152 clk_disable(clk);
153 err_clk:
154 tegra_powergate_power_off(id);
155 err_power:
156 return ret;
157 }
158
159 #ifdef CONFIG_DEBUG_FS
160
161 static const char * const powergate_name[] = {
162 [TEGRA_POWERGATE_CPU] = "cpu",
163 [TEGRA_POWERGATE_3D] = "3d",
164 [TEGRA_POWERGATE_VENC] = "venc",
165 [TEGRA_POWERGATE_VDEC] = "vdec",
166 [TEGRA_POWERGATE_PCIE] = "pcie",
167 [TEGRA_POWERGATE_L2] = "l2",
168 [TEGRA_POWERGATE_MPE] = "mpe",
169 };
170
powergate_show(struct seq_file * s,void * data)171 static int powergate_show(struct seq_file *s, void *data)
172 {
173 int i;
174
175 seq_printf(s, " powergate powered\n");
176 seq_printf(s, "------------------\n");
177
178 for (i = 0; i < TEGRA_NUM_POWERGATE; i++)
179 seq_printf(s, " %9s %7s\n", powergate_name[i],
180 tegra_powergate_is_powered(i) ? "yes" : "no");
181 return 0;
182 }
183
powergate_open(struct inode * inode,struct file * file)184 static int powergate_open(struct inode *inode, struct file *file)
185 {
186 return single_open(file, powergate_show, inode->i_private);
187 }
188
189 static const struct file_operations powergate_fops = {
190 .open = powergate_open,
191 .read = seq_read,
192 .llseek = seq_lseek,
193 .release = single_release,
194 };
195
powergate_debugfs_init(void)196 static int __init powergate_debugfs_init(void)
197 {
198 struct dentry *d;
199 int err = -ENOMEM;
200
201 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
202 &powergate_fops);
203 if (!d)
204 return -ENOMEM;
205
206 return err;
207 }
208
209 late_initcall(powergate_debugfs_init);
210
211 #endif
212