1 /*
2 * arch/arm/mach-tegra/common.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/of_irq.h>
25
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/hardware/gic.h>
28
29 #include <mach/iomap.h>
30 #include <mach/system.h>
31
32 #include "board.h"
33 #include "clock.h"
34 #include "fuse.h"
35
36 #ifdef CONFIG_OF
37 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
38 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
39 { }
40 };
41
tegra_dt_init_irq(void)42 void __init tegra_dt_init_irq(void)
43 {
44 tegra_init_irq();
45 of_irq_init(tegra_dt_irq_match);
46 }
47 #endif
48
tegra_assert_system_reset(char mode,const char * cmd)49 void tegra_assert_system_reset(char mode, const char *cmd)
50 {
51 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
52 u32 reg;
53
54 reg = readl_relaxed(reset);
55 reg |= 0x10;
56 writel_relaxed(reg, reset);
57 }
58
59 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
60 static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
61 /* name parent rate enabled */
62 { "clk_m", NULL, 0, true },
63 { "pll_p", "clk_m", 216000000, true },
64 { "pll_p_out1", "pll_p", 28800000, true },
65 { "pll_p_out2", "pll_p", 48000000, true },
66 { "pll_p_out3", "pll_p", 72000000, true },
67 { "pll_p_out4", "pll_p", 108000000, true },
68 { "sclk", "pll_p_out4", 108000000, true },
69 { "hclk", "sclk", 108000000, true },
70 { "pclk", "hclk", 54000000, true },
71 { "csite", NULL, 0, true },
72 { "emc", NULL, 0, true },
73 { "cpu", NULL, 0, true },
74 { NULL, NULL, 0, 0},
75 };
76 #endif
77
tegra_init_cache(u32 tag_latency,u32 data_latency)78 static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
79 {
80 #ifdef CONFIG_CACHE_L2X0
81 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
82 u32 aux_ctrl, cache_type;
83
84 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
85 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
86
87 cache_type = readl(p + L2X0_CACHE_TYPE);
88 aux_ctrl = (cache_type & 0x700) << (17-8);
89 aux_ctrl |= 0x6C000001;
90
91 l2x0_init(p, aux_ctrl, 0x8200c3fe);
92 #endif
93
94 }
95
96 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
tegra20_init_early(void)97 void __init tegra20_init_early(void)
98 {
99 tegra_init_fuse();
100 tegra2_init_clocks();
101 tegra_clk_init_from_table(tegra20_clk_init_table);
102 tegra_init_cache(0x331, 0x441);
103 }
104 #endif
105 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
tegra30_init_early(void)106 void __init tegra30_init_early(void)
107 {
108 tegra_init_cache(0x441, 0x551);
109 }
110 #endif
111