1 /*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <asm/mach-types.h>
17 #include <plat/clock.h>
18 #include <mach/misc_regs.h>
19
20 /* root clks */
21 /* 32 KHz oscillator clock */
22 static struct clk osc_32k_clk = {
23 .flags = ALWAYS_ENABLED,
24 .rate = 32000,
25 };
26
27 /* 24 MHz oscillator clock */
28 static struct clk osc_24m_clk = {
29 .flags = ALWAYS_ENABLED,
30 .rate = 24000000,
31 };
32
33 /* clock derived from 32 KHz osc clk */
34 /* rtc clock */
35 static struct clk rtc_clk = {
36 .pclk = &osc_32k_clk,
37 .en_reg = PERIP1_CLK_ENB,
38 .en_reg_bit = RTC_CLK_ENB,
39 .recalc = &follow_parent,
40 };
41
42 /* clock derived from 24 MHz osc clk */
43 /* pll masks structure */
44 static struct pll_clk_masks pll1_masks = {
45 .mode_mask = PLL_MODE_MASK,
46 .mode_shift = PLL_MODE_SHIFT,
47 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
48 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
49 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
50 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
51 .div_p_mask = PLL_DIV_P_MASK,
52 .div_p_shift = PLL_DIV_P_SHIFT,
53 .div_n_mask = PLL_DIV_N_MASK,
54 .div_n_shift = PLL_DIV_N_SHIFT,
55 };
56
57 /* pll1 configuration structure */
58 static struct pll_clk_config pll1_config = {
59 .mode_reg = PLL1_CTR,
60 .cfg_reg = PLL1_FRQ,
61 .masks = &pll1_masks,
62 };
63
64 /* pll rate configuration table, in ascending order of rates */
65 struct pll_rate_tbl pll_rtbl[] = {
66 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
67 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
68 };
69
70 /* PLL1 clock */
71 static struct clk pll1_clk = {
72 .flags = ENABLED_ON_INIT,
73 .pclk = &osc_24m_clk,
74 .en_reg = PLL1_CTR,
75 .en_reg_bit = PLL_ENABLE,
76 .calc_rate = &pll_calc_rate,
77 .recalc = &pll_clk_recalc,
78 .set_rate = &pll_clk_set_rate,
79 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
80 .private_data = &pll1_config,
81 };
82
83 /* PLL3 48 MHz clock */
84 static struct clk pll3_48m_clk = {
85 .flags = ALWAYS_ENABLED,
86 .pclk = &osc_24m_clk,
87 .rate = 48000000,
88 };
89
90 /* watch dog timer clock */
91 static struct clk wdt_clk = {
92 .flags = ALWAYS_ENABLED,
93 .pclk = &osc_24m_clk,
94 .recalc = &follow_parent,
95 };
96
97 /* clock derived from pll1 clk */
98 /* cpu clock */
99 static struct clk cpu_clk = {
100 .flags = ALWAYS_ENABLED,
101 .pclk = &pll1_clk,
102 .recalc = &follow_parent,
103 };
104
105 /* ahb masks structure */
106 static struct bus_clk_masks ahb_masks = {
107 .mask = PLL_HCLK_RATIO_MASK,
108 .shift = PLL_HCLK_RATIO_SHIFT,
109 };
110
111 /* ahb configuration structure */
112 static struct bus_clk_config ahb_config = {
113 .reg = CORE_CLK_CFG,
114 .masks = &ahb_masks,
115 };
116
117 /* ahb rate configuration table, in ascending order of rates */
118 struct bus_rate_tbl bus_rtbl[] = {
119 {.div = 3}, /* == parent divided by 4 */
120 {.div = 2}, /* == parent divided by 3 */
121 {.div = 1}, /* == parent divided by 2 */
122 {.div = 0}, /* == parent divided by 1 */
123 };
124
125 /* ahb clock */
126 static struct clk ahb_clk = {
127 .flags = ALWAYS_ENABLED,
128 .pclk = &pll1_clk,
129 .calc_rate = &bus_calc_rate,
130 .recalc = &bus_clk_recalc,
131 .set_rate = &bus_clk_set_rate,
132 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
133 .private_data = &ahb_config,
134 };
135
136 /* auxiliary synthesizers masks */
137 static struct aux_clk_masks aux_masks = {
138 .eq_sel_mask = AUX_EQ_SEL_MASK,
139 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
140 .eq1_mask = AUX_EQ1_SEL,
141 .eq2_mask = AUX_EQ2_SEL,
142 .xscale_sel_mask = AUX_XSCALE_MASK,
143 .xscale_sel_shift = AUX_XSCALE_SHIFT,
144 .yscale_sel_mask = AUX_YSCALE_MASK,
145 .yscale_sel_shift = AUX_YSCALE_SHIFT,
146 };
147
148 /* uart synth configurations */
149 static struct aux_clk_config uart_synth_config = {
150 .synth_reg = UART_CLK_SYNT,
151 .masks = &aux_masks,
152 };
153
154 /* aux rate configuration table, in ascending order of rates */
155 struct aux_rate_tbl aux_rtbl[] = {
156 /* For PLL1 = 332 MHz */
157 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
158 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
159 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
160 };
161
162 /* uart synth clock */
163 static struct clk uart_synth_clk = {
164 .en_reg = UART_CLK_SYNT,
165 .en_reg_bit = AUX_SYNT_ENB,
166 .pclk = &pll1_clk,
167 .calc_rate = &aux_calc_rate,
168 .recalc = &aux_clk_recalc,
169 .set_rate = &aux_clk_set_rate,
170 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
171 .private_data = &uart_synth_config,
172 };
173
174 /* uart parents */
175 static struct pclk_info uart_pclk_info[] = {
176 {
177 .pclk = &uart_synth_clk,
178 .pclk_val = AUX_CLK_PLL1_VAL,
179 }, {
180 .pclk = &pll3_48m_clk,
181 .pclk_val = AUX_CLK_PLL3_VAL,
182 },
183 };
184
185 /* uart parent select structure */
186 static struct pclk_sel uart_pclk_sel = {
187 .pclk_info = uart_pclk_info,
188 .pclk_count = ARRAY_SIZE(uart_pclk_info),
189 .pclk_sel_reg = PERIP_CLK_CFG,
190 .pclk_sel_mask = UART_CLK_MASK,
191 };
192
193 /* uart clock */
194 static struct clk uart_clk = {
195 .en_reg = PERIP1_CLK_ENB,
196 .en_reg_bit = UART_CLK_ENB,
197 .pclk_sel = &uart_pclk_sel,
198 .pclk_sel_shift = UART_CLK_SHIFT,
199 .recalc = &follow_parent,
200 };
201
202 /* firda configurations */
203 static struct aux_clk_config firda_synth_config = {
204 .synth_reg = FIRDA_CLK_SYNT,
205 .masks = &aux_masks,
206 };
207
208 /* firda synth clock */
209 static struct clk firda_synth_clk = {
210 .en_reg = FIRDA_CLK_SYNT,
211 .en_reg_bit = AUX_SYNT_ENB,
212 .pclk = &pll1_clk,
213 .calc_rate = &aux_calc_rate,
214 .recalc = &aux_clk_recalc,
215 .set_rate = &aux_clk_set_rate,
216 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
217 .private_data = &firda_synth_config,
218 };
219
220 /* firda parents */
221 static struct pclk_info firda_pclk_info[] = {
222 {
223 .pclk = &firda_synth_clk,
224 .pclk_val = AUX_CLK_PLL1_VAL,
225 }, {
226 .pclk = &pll3_48m_clk,
227 .pclk_val = AUX_CLK_PLL3_VAL,
228 },
229 };
230
231 /* firda parent select structure */
232 static struct pclk_sel firda_pclk_sel = {
233 .pclk_info = firda_pclk_info,
234 .pclk_count = ARRAY_SIZE(firda_pclk_info),
235 .pclk_sel_reg = PERIP_CLK_CFG,
236 .pclk_sel_mask = FIRDA_CLK_MASK,
237 };
238
239 /* firda clock */
240 static struct clk firda_clk = {
241 .en_reg = PERIP1_CLK_ENB,
242 .en_reg_bit = FIRDA_CLK_ENB,
243 .pclk_sel = &firda_pclk_sel,
244 .pclk_sel_shift = FIRDA_CLK_SHIFT,
245 .recalc = &follow_parent,
246 };
247
248 /* gpt synthesizer masks */
249 static struct gpt_clk_masks gpt_masks = {
250 .mscale_sel_mask = GPT_MSCALE_MASK,
251 .mscale_sel_shift = GPT_MSCALE_SHIFT,
252 .nscale_sel_mask = GPT_NSCALE_MASK,
253 .nscale_sel_shift = GPT_NSCALE_SHIFT,
254 };
255
256 /* gpt rate configuration table, in ascending order of rates */
257 struct gpt_rate_tbl gpt_rtbl[] = {
258 /* For pll1 = 332 MHz */
259 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
260 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
261 {.mscale = 1, .nscale = 0}, /* 83 MHz */
262 };
263
264 /* gpt0 synth clk config*/
265 static struct gpt_clk_config gpt0_synth_config = {
266 .synth_reg = PRSC1_CLK_CFG,
267 .masks = &gpt_masks,
268 };
269
270 /* gpt synth clock */
271 static struct clk gpt0_synth_clk = {
272 .flags = ALWAYS_ENABLED,
273 .pclk = &pll1_clk,
274 .calc_rate = &gpt_calc_rate,
275 .recalc = &gpt_clk_recalc,
276 .set_rate = &gpt_clk_set_rate,
277 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
278 .private_data = &gpt0_synth_config,
279 };
280
281 /* gpt parents */
282 static struct pclk_info gpt0_pclk_info[] = {
283 {
284 .pclk = &gpt0_synth_clk,
285 .pclk_val = AUX_CLK_PLL1_VAL,
286 }, {
287 .pclk = &pll3_48m_clk,
288 .pclk_val = AUX_CLK_PLL3_VAL,
289 },
290 };
291
292 /* gpt parent select structure */
293 static struct pclk_sel gpt0_pclk_sel = {
294 .pclk_info = gpt0_pclk_info,
295 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
296 .pclk_sel_reg = PERIP_CLK_CFG,
297 .pclk_sel_mask = GPT_CLK_MASK,
298 };
299
300 /* gpt0 timer clock */
301 static struct clk gpt0_clk = {
302 .flags = ALWAYS_ENABLED,
303 .pclk_sel = &gpt0_pclk_sel,
304 .pclk_sel_shift = GPT0_CLK_SHIFT,
305 .recalc = &follow_parent,
306 };
307
308 /* gpt1 synth clk configurations */
309 static struct gpt_clk_config gpt1_synth_config = {
310 .synth_reg = PRSC2_CLK_CFG,
311 .masks = &gpt_masks,
312 };
313
314 /* gpt1 synth clock */
315 static struct clk gpt1_synth_clk = {
316 .flags = ALWAYS_ENABLED,
317 .pclk = &pll1_clk,
318 .calc_rate = &gpt_calc_rate,
319 .recalc = &gpt_clk_recalc,
320 .set_rate = &gpt_clk_set_rate,
321 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
322 .private_data = &gpt1_synth_config,
323 };
324
325 static struct pclk_info gpt1_pclk_info[] = {
326 {
327 .pclk = &gpt1_synth_clk,
328 .pclk_val = AUX_CLK_PLL1_VAL,
329 }, {
330 .pclk = &pll3_48m_clk,
331 .pclk_val = AUX_CLK_PLL3_VAL,
332 },
333 };
334
335 /* gpt parent select structure */
336 static struct pclk_sel gpt1_pclk_sel = {
337 .pclk_info = gpt1_pclk_info,
338 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
339 .pclk_sel_reg = PERIP_CLK_CFG,
340 .pclk_sel_mask = GPT_CLK_MASK,
341 };
342
343 /* gpt1 timer clock */
344 static struct clk gpt1_clk = {
345 .en_reg = PERIP1_CLK_ENB,
346 .en_reg_bit = GPT1_CLK_ENB,
347 .pclk_sel = &gpt1_pclk_sel,
348 .pclk_sel_shift = GPT1_CLK_SHIFT,
349 .recalc = &follow_parent,
350 };
351
352 /* gpt2 synth clk configurations */
353 static struct gpt_clk_config gpt2_synth_config = {
354 .synth_reg = PRSC3_CLK_CFG,
355 .masks = &gpt_masks,
356 };
357
358 /* gpt1 synth clock */
359 static struct clk gpt2_synth_clk = {
360 .flags = ALWAYS_ENABLED,
361 .pclk = &pll1_clk,
362 .calc_rate = &gpt_calc_rate,
363 .recalc = &gpt_clk_recalc,
364 .set_rate = &gpt_clk_set_rate,
365 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
366 .private_data = &gpt2_synth_config,
367 };
368
369 static struct pclk_info gpt2_pclk_info[] = {
370 {
371 .pclk = &gpt2_synth_clk,
372 .pclk_val = AUX_CLK_PLL1_VAL,
373 }, {
374 .pclk = &pll3_48m_clk,
375 .pclk_val = AUX_CLK_PLL3_VAL,
376 },
377 };
378
379 /* gpt parent select structure */
380 static struct pclk_sel gpt2_pclk_sel = {
381 .pclk_info = gpt2_pclk_info,
382 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
383 .pclk_sel_reg = PERIP_CLK_CFG,
384 .pclk_sel_mask = GPT_CLK_MASK,
385 };
386
387 /* gpt2 timer clock */
388 static struct clk gpt2_clk = {
389 .en_reg = PERIP1_CLK_ENB,
390 .en_reg_bit = GPT2_CLK_ENB,
391 .pclk_sel = &gpt2_pclk_sel,
392 .pclk_sel_shift = GPT2_CLK_SHIFT,
393 .recalc = &follow_parent,
394 };
395
396 /* clock derived from pll3 clk */
397 /* usbh clock */
398 static struct clk usbh_clk = {
399 .pclk = &pll3_48m_clk,
400 .en_reg = PERIP1_CLK_ENB,
401 .en_reg_bit = USBH_CLK_ENB,
402 .recalc = &follow_parent,
403 };
404
405 /* usbd clock */
406 static struct clk usbd_clk = {
407 .pclk = &pll3_48m_clk,
408 .en_reg = PERIP1_CLK_ENB,
409 .en_reg_bit = USBD_CLK_ENB,
410 .recalc = &follow_parent,
411 };
412
413 /* clock derived from ahb clk */
414 /* apb masks structure */
415 static struct bus_clk_masks apb_masks = {
416 .mask = HCLK_PCLK_RATIO_MASK,
417 .shift = HCLK_PCLK_RATIO_SHIFT,
418 };
419
420 /* apb configuration structure */
421 static struct bus_clk_config apb_config = {
422 .reg = CORE_CLK_CFG,
423 .masks = &apb_masks,
424 };
425
426 /* apb clock */
427 static struct clk apb_clk = {
428 .flags = ALWAYS_ENABLED,
429 .pclk = &ahb_clk,
430 .calc_rate = &bus_calc_rate,
431 .recalc = &bus_clk_recalc,
432 .set_rate = &bus_clk_set_rate,
433 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
434 .private_data = &apb_config,
435 };
436
437 /* i2c clock */
438 static struct clk i2c_clk = {
439 .pclk = &ahb_clk,
440 .en_reg = PERIP1_CLK_ENB,
441 .en_reg_bit = I2C_CLK_ENB,
442 .recalc = &follow_parent,
443 };
444
445 /* dma clock */
446 static struct clk dma_clk = {
447 .pclk = &ahb_clk,
448 .en_reg = PERIP1_CLK_ENB,
449 .en_reg_bit = DMA_CLK_ENB,
450 .recalc = &follow_parent,
451 };
452
453 /* jpeg clock */
454 static struct clk jpeg_clk = {
455 .pclk = &ahb_clk,
456 .en_reg = PERIP1_CLK_ENB,
457 .en_reg_bit = JPEG_CLK_ENB,
458 .recalc = &follow_parent,
459 };
460
461 /* gmac clock */
462 static struct clk gmac_clk = {
463 .pclk = &ahb_clk,
464 .en_reg = PERIP1_CLK_ENB,
465 .en_reg_bit = GMAC_CLK_ENB,
466 .recalc = &follow_parent,
467 };
468
469 /* smi clock */
470 static struct clk smi_clk = {
471 .pclk = &ahb_clk,
472 .en_reg = PERIP1_CLK_ENB,
473 .en_reg_bit = SMI_CLK_ENB,
474 .recalc = &follow_parent,
475 };
476
477 /* c3 clock */
478 static struct clk c3_clk = {
479 .pclk = &ahb_clk,
480 .en_reg = PERIP1_CLK_ENB,
481 .en_reg_bit = C3_CLK_ENB,
482 .recalc = &follow_parent,
483 };
484
485 /* clock derived from apb clk */
486 /* adc clock */
487 static struct clk adc_clk = {
488 .pclk = &apb_clk,
489 .en_reg = PERIP1_CLK_ENB,
490 .en_reg_bit = ADC_CLK_ENB,
491 .recalc = &follow_parent,
492 };
493
494 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
495 /* emi clock */
496 static struct clk emi_clk = {
497 .flags = ALWAYS_ENABLED,
498 .pclk = &ahb_clk,
499 .recalc = &follow_parent,
500 };
501 #endif
502
503 /* ssp clock */
504 static struct clk ssp0_clk = {
505 .pclk = &apb_clk,
506 .en_reg = PERIP1_CLK_ENB,
507 .en_reg_bit = SSP_CLK_ENB,
508 .recalc = &follow_parent,
509 };
510
511 /* gpio clock */
512 static struct clk gpio_clk = {
513 .pclk = &apb_clk,
514 .en_reg = PERIP1_CLK_ENB,
515 .en_reg_bit = GPIO_CLK_ENB,
516 .recalc = &follow_parent,
517 };
518
519 static struct clk dummy_apb_pclk;
520
521 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
522 defined(CONFIG_MACH_SPEAR320)
523 /* fsmc clock */
524 static struct clk fsmc_clk = {
525 .flags = ALWAYS_ENABLED,
526 .pclk = &ahb_clk,
527 .recalc = &follow_parent,
528 };
529 #endif
530
531 /* common clocks to spear310 and spear320 */
532 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
533 /* uart1 clock */
534 static struct clk uart1_clk = {
535 .flags = ALWAYS_ENABLED,
536 .pclk = &apb_clk,
537 .recalc = &follow_parent,
538 };
539
540 /* uart2 clock */
541 static struct clk uart2_clk = {
542 .flags = ALWAYS_ENABLED,
543 .pclk = &apb_clk,
544 .recalc = &follow_parent,
545 };
546 #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
547
548 /* common clocks to spear300 and spear320 */
549 #if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
550 /* clcd clock */
551 static struct clk clcd_clk = {
552 .flags = ALWAYS_ENABLED,
553 .pclk = &pll3_48m_clk,
554 .recalc = &follow_parent,
555 };
556
557 /* sdhci clock */
558 static struct clk sdhci_clk = {
559 .flags = ALWAYS_ENABLED,
560 .pclk = &ahb_clk,
561 .recalc = &follow_parent,
562 };
563 #endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
564
565 /* spear300 machine specific clock structures */
566 #ifdef CONFIG_MACH_SPEAR300
567 /* gpio1 clock */
568 static struct clk gpio1_clk = {
569 .flags = ALWAYS_ENABLED,
570 .pclk = &apb_clk,
571 .recalc = &follow_parent,
572 };
573
574 /* keyboard clock */
575 static struct clk kbd_clk = {
576 .flags = ALWAYS_ENABLED,
577 .pclk = &apb_clk,
578 .recalc = &follow_parent,
579 };
580
581 #endif
582
583 /* spear310 machine specific clock structures */
584 #ifdef CONFIG_MACH_SPEAR310
585 /* uart3 clock */
586 static struct clk uart3_clk = {
587 .flags = ALWAYS_ENABLED,
588 .pclk = &apb_clk,
589 .recalc = &follow_parent,
590 };
591
592 /* uart4 clock */
593 static struct clk uart4_clk = {
594 .flags = ALWAYS_ENABLED,
595 .pclk = &apb_clk,
596 .recalc = &follow_parent,
597 };
598
599 /* uart5 clock */
600 static struct clk uart5_clk = {
601 .flags = ALWAYS_ENABLED,
602 .pclk = &apb_clk,
603 .recalc = &follow_parent,
604 };
605 #endif
606
607 /* spear320 machine specific clock structures */
608 #ifdef CONFIG_MACH_SPEAR320
609 /* can0 clock */
610 static struct clk can0_clk = {
611 .flags = ALWAYS_ENABLED,
612 .pclk = &apb_clk,
613 .recalc = &follow_parent,
614 };
615
616 /* can1 clock */
617 static struct clk can1_clk = {
618 .flags = ALWAYS_ENABLED,
619 .pclk = &apb_clk,
620 .recalc = &follow_parent,
621 };
622
623 /* i2c1 clock */
624 static struct clk i2c1_clk = {
625 .flags = ALWAYS_ENABLED,
626 .pclk = &ahb_clk,
627 .recalc = &follow_parent,
628 };
629
630 /* ssp1 clock */
631 static struct clk ssp1_clk = {
632 .flags = ALWAYS_ENABLED,
633 .pclk = &apb_clk,
634 .recalc = &follow_parent,
635 };
636
637 /* ssp2 clock */
638 static struct clk ssp2_clk = {
639 .flags = ALWAYS_ENABLED,
640 .pclk = &apb_clk,
641 .recalc = &follow_parent,
642 };
643
644 /* pwm clock */
645 static struct clk pwm_clk = {
646 .flags = ALWAYS_ENABLED,
647 .pclk = &apb_clk,
648 .recalc = &follow_parent,
649 };
650 #endif
651
652 /* array of all spear 3xx clock lookups */
653 static struct clk_lookup spear_clk_lookups[] = {
654 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
655 /* root clks */
656 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
657 { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
658 /* clock derived from 32 KHz osc clk */
659 { .dev_id = "rtc-spear", .clk = &rtc_clk},
660 /* clock derived from 24 MHz osc clk */
661 { .con_id = "pll1_clk", .clk = &pll1_clk},
662 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
663 { .dev_id = "wdt", .clk = &wdt_clk},
664 /* clock derived from pll1 clk */
665 { .con_id = "cpu_clk", .clk = &cpu_clk},
666 { .con_id = "ahb_clk", .clk = &ahb_clk},
667 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
668 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
669 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
670 { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk},
671 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
672 { .dev_id = "uart", .clk = &uart_clk},
673 { .dev_id = "firda", .clk = &firda_clk},
674 { .dev_id = "gpt0", .clk = &gpt0_clk},
675 { .dev_id = "gpt1", .clk = &gpt1_clk},
676 { .dev_id = "gpt2", .clk = &gpt2_clk},
677 /* clock derived from pll3 clk */
678 { .dev_id = "designware_udc", .clk = &usbd_clk},
679 { .con_id = "usbh_clk", .clk = &usbh_clk},
680 /* clock derived from ahb clk */
681 { .con_id = "apb_clk", .clk = &apb_clk},
682 { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
683 { .dev_id = "dma", .clk = &dma_clk},
684 { .dev_id = "jpeg", .clk = &jpeg_clk},
685 { .dev_id = "gmac", .clk = &gmac_clk},
686 { .dev_id = "smi", .clk = &smi_clk},
687 { .dev_id = "c3", .clk = &c3_clk},
688 /* clock derived from apb clk */
689 { .dev_id = "adc", .clk = &adc_clk},
690 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
691 { .dev_id = "gpio", .clk = &gpio_clk},
692 };
693
694 /* array of all spear 300 clock lookups */
695 #ifdef CONFIG_MACH_SPEAR300
696 static struct clk_lookup spear300_clk_lookups[] = {
697 { .dev_id = "clcd", .clk = &clcd_clk},
698 { .con_id = "fsmc", .clk = &fsmc_clk},
699 { .dev_id = "gpio1", .clk = &gpio1_clk},
700 { .dev_id = "keyboard", .clk = &kbd_clk},
701 { .dev_id = "sdhci", .clk = &sdhci_clk},
702 };
703 #endif
704
705 /* array of all spear 310 clock lookups */
706 #ifdef CONFIG_MACH_SPEAR310
707 static struct clk_lookup spear310_clk_lookups[] = {
708 { .con_id = "fsmc", .clk = &fsmc_clk},
709 { .con_id = "emi", .clk = &emi_clk},
710 { .dev_id = "uart1", .clk = &uart1_clk},
711 { .dev_id = "uart2", .clk = &uart2_clk},
712 { .dev_id = "uart3", .clk = &uart3_clk},
713 { .dev_id = "uart4", .clk = &uart4_clk},
714 { .dev_id = "uart5", .clk = &uart5_clk},
715 };
716 #endif
717
718 /* array of all spear 320 clock lookups */
719 #ifdef CONFIG_MACH_SPEAR320
720 static struct clk_lookup spear320_clk_lookups[] = {
721 { .dev_id = "clcd", .clk = &clcd_clk},
722 { .con_id = "fsmc", .clk = &fsmc_clk},
723 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
724 { .con_id = "emi", .clk = &emi_clk},
725 { .dev_id = "pwm", .clk = &pwm_clk},
726 { .dev_id = "sdhci", .clk = &sdhci_clk},
727 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
728 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
729 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
730 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
731 { .dev_id = "uart1", .clk = &uart1_clk},
732 { .dev_id = "uart2", .clk = &uart2_clk},
733 };
734 #endif
735
spear3xx_clk_init(void)736 void __init spear3xx_clk_init(void)
737 {
738 int i, cnt;
739 struct clk_lookup *lookups;
740
741 if (machine_is_spear300()) {
742 cnt = ARRAY_SIZE(spear300_clk_lookups);
743 lookups = spear300_clk_lookups;
744 } else if (machine_is_spear310()) {
745 cnt = ARRAY_SIZE(spear310_clk_lookups);
746 lookups = spear310_clk_lookups;
747 } else {
748 cnt = ARRAY_SIZE(spear320_clk_lookups);
749 lookups = spear320_clk_lookups;
750 }
751
752 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
753 clk_register(&spear_clk_lookups[i]);
754
755 for (i = 0; i < cnt; i++)
756 clk_register(&lookups[i]);
757
758 clk_init();
759 }
760