1 /*
2 * sh7377 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
28 #include <linux/io.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
35
36 /* SCIFA0 */
37 static struct plat_sci_port scif0_platform_data = {
38 .mapbase = 0xe6c40000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE,
41 .scbrr_algo_id = SCBRR_ALGO_4,
42 .type = PORT_SCIFA,
43 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
44 evt2irq(0xc00), evt2irq(0xc00) },
45 };
46
47 static struct platform_device scif0_device = {
48 .name = "sh-sci",
49 .id = 0,
50 .dev = {
51 .platform_data = &scif0_platform_data,
52 },
53 };
54
55 /* SCIFA1 */
56 static struct plat_sci_port scif1_platform_data = {
57 .mapbase = 0xe6c50000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .scscr = SCSCR_RE | SCSCR_TE,
60 .scbrr_algo_id = SCBRR_ALGO_4,
61 .type = PORT_SCIFA,
62 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
63 evt2irq(0xc20), evt2irq(0xc20) },
64 };
65
66 static struct platform_device scif1_device = {
67 .name = "sh-sci",
68 .id = 1,
69 .dev = {
70 .platform_data = &scif1_platform_data,
71 },
72 };
73
74 /* SCIFA2 */
75 static struct plat_sci_port scif2_platform_data = {
76 .mapbase = 0xe6c60000,
77 .flags = UPF_BOOT_AUTOCONF,
78 .scscr = SCSCR_RE | SCSCR_TE,
79 .scbrr_algo_id = SCBRR_ALGO_4,
80 .type = PORT_SCIFA,
81 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
82 evt2irq(0xc40), evt2irq(0xc40) },
83 };
84
85 static struct platform_device scif2_device = {
86 .name = "sh-sci",
87 .id = 2,
88 .dev = {
89 .platform_data = &scif2_platform_data,
90 },
91 };
92
93 /* SCIFA3 */
94 static struct plat_sci_port scif3_platform_data = {
95 .mapbase = 0xe6c70000,
96 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE,
98 .scbrr_algo_id = SCBRR_ALGO_4,
99 .type = PORT_SCIFA,
100 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
101 evt2irq(0xc60), evt2irq(0xc60) },
102 };
103
104 static struct platform_device scif3_device = {
105 .name = "sh-sci",
106 .id = 3,
107 .dev = {
108 .platform_data = &scif3_platform_data,
109 },
110 };
111
112 /* SCIFA4 */
113 static struct plat_sci_port scif4_platform_data = {
114 .mapbase = 0xe6c80000,
115 .flags = UPF_BOOT_AUTOCONF,
116 .scscr = SCSCR_RE | SCSCR_TE,
117 .scbrr_algo_id = SCBRR_ALGO_4,
118 .type = PORT_SCIFA,
119 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
120 evt2irq(0xd20), evt2irq(0xd20) },
121 };
122
123 static struct platform_device scif4_device = {
124 .name = "sh-sci",
125 .id = 4,
126 .dev = {
127 .platform_data = &scif4_platform_data,
128 },
129 };
130
131 /* SCIFA5 */
132 static struct plat_sci_port scif5_platform_data = {
133 .mapbase = 0xe6cb0000,
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE,
136 .scbrr_algo_id = SCBRR_ALGO_4,
137 .type = PORT_SCIFA,
138 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
139 evt2irq(0xd40), evt2irq(0xd40) },
140 };
141
142 static struct platform_device scif5_device = {
143 .name = "sh-sci",
144 .id = 5,
145 .dev = {
146 .platform_data = &scif5_platform_data,
147 },
148 };
149
150 /* SCIFA6 */
151 static struct plat_sci_port scif6_platform_data = {
152 .mapbase = 0xe6cc0000,
153 .flags = UPF_BOOT_AUTOCONF,
154 .scscr = SCSCR_RE | SCSCR_TE,
155 .scbrr_algo_id = SCBRR_ALGO_4,
156 .type = PORT_SCIFA,
157 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
158 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
159 };
160
161 static struct platform_device scif6_device = {
162 .name = "sh-sci",
163 .id = 6,
164 .dev = {
165 .platform_data = &scif6_platform_data,
166 },
167 };
168
169 /* SCIFB */
170 static struct plat_sci_port scif7_platform_data = {
171 .mapbase = 0xe6c30000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFB,
176 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
177 evt2irq(0xd60), evt2irq(0xd60) },
178 };
179
180 static struct platform_device scif7_device = {
181 .name = "sh-sci",
182 .id = 7,
183 .dev = {
184 .platform_data = &scif7_platform_data,
185 },
186 };
187
188 static struct sh_timer_config cmt10_platform_data = {
189 .name = "CMT10",
190 .channel_offset = 0x10,
191 .timer_bit = 0,
192 .clockevent_rating = 125,
193 .clocksource_rating = 125,
194 };
195
196 static struct resource cmt10_resources[] = {
197 [0] = {
198 .name = "CMT10",
199 .start = 0xe6138010,
200 .end = 0xe613801b,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = evt2irq(0xb00), /* CMT1_CMT10 */
205 .flags = IORESOURCE_IRQ,
206 },
207 };
208
209 static struct platform_device cmt10_device = {
210 .name = "sh_cmt",
211 .id = 10,
212 .dev = {
213 .platform_data = &cmt10_platform_data,
214 },
215 .resource = cmt10_resources,
216 .num_resources = ARRAY_SIZE(cmt10_resources),
217 };
218
219 /* VPU */
220 static struct uio_info vpu_platform_data = {
221 .name = "VPU5HG",
222 .version = "0",
223 .irq = intcs_evt2irq(0x980),
224 };
225
226 static struct resource vpu_resources[] = {
227 [0] = {
228 .name = "VPU",
229 .start = 0xfe900000,
230 .end = 0xfe900157,
231 .flags = IORESOURCE_MEM,
232 },
233 };
234
235 static struct platform_device vpu_device = {
236 .name = "uio_pdrv_genirq",
237 .id = 0,
238 .dev = {
239 .platform_data = &vpu_platform_data,
240 },
241 .resource = vpu_resources,
242 .num_resources = ARRAY_SIZE(vpu_resources),
243 };
244
245 /* VEU0 */
246 static struct uio_info veu0_platform_data = {
247 .name = "VEU0",
248 .version = "0",
249 .irq = intcs_evt2irq(0x700),
250 };
251
252 static struct resource veu0_resources[] = {
253 [0] = {
254 .name = "VEU0",
255 .start = 0xfe920000,
256 .end = 0xfe9200cb,
257 .flags = IORESOURCE_MEM,
258 },
259 };
260
261 static struct platform_device veu0_device = {
262 .name = "uio_pdrv_genirq",
263 .id = 1,
264 .dev = {
265 .platform_data = &veu0_platform_data,
266 },
267 .resource = veu0_resources,
268 .num_resources = ARRAY_SIZE(veu0_resources),
269 };
270
271 /* VEU1 */
272 static struct uio_info veu1_platform_data = {
273 .name = "VEU1",
274 .version = "0",
275 .irq = intcs_evt2irq(0x720),
276 };
277
278 static struct resource veu1_resources[] = {
279 [0] = {
280 .name = "VEU1",
281 .start = 0xfe924000,
282 .end = 0xfe9240cb,
283 .flags = IORESOURCE_MEM,
284 },
285 };
286
287 static struct platform_device veu1_device = {
288 .name = "uio_pdrv_genirq",
289 .id = 2,
290 .dev = {
291 .platform_data = &veu1_platform_data,
292 },
293 .resource = veu1_resources,
294 .num_resources = ARRAY_SIZE(veu1_resources),
295 };
296
297 /* VEU2 */
298 static struct uio_info veu2_platform_data = {
299 .name = "VEU2",
300 .version = "0",
301 .irq = intcs_evt2irq(0x740),
302 };
303
304 static struct resource veu2_resources[] = {
305 [0] = {
306 .name = "VEU2",
307 .start = 0xfe928000,
308 .end = 0xfe928307,
309 .flags = IORESOURCE_MEM,
310 },
311 };
312
313 static struct platform_device veu2_device = {
314 .name = "uio_pdrv_genirq",
315 .id = 3,
316 .dev = {
317 .platform_data = &veu2_platform_data,
318 },
319 .resource = veu2_resources,
320 .num_resources = ARRAY_SIZE(veu2_resources),
321 };
322
323 /* VEU3 */
324 static struct uio_info veu3_platform_data = {
325 .name = "VEU3",
326 .version = "0",
327 .irq = intcs_evt2irq(0x760),
328 };
329
330 static struct resource veu3_resources[] = {
331 [0] = {
332 .name = "VEU3",
333 .start = 0xfe92c000,
334 .end = 0xfe92c307,
335 .flags = IORESOURCE_MEM,
336 },
337 };
338
339 static struct platform_device veu3_device = {
340 .name = "uio_pdrv_genirq",
341 .id = 4,
342 .dev = {
343 .platform_data = &veu3_platform_data,
344 },
345 .resource = veu3_resources,
346 .num_resources = ARRAY_SIZE(veu3_resources),
347 };
348
349 /* JPU */
350 static struct uio_info jpu_platform_data = {
351 .name = "JPU",
352 .version = "0",
353 .irq = intcs_evt2irq(0x560),
354 };
355
356 static struct resource jpu_resources[] = {
357 [0] = {
358 .name = "JPU",
359 .start = 0xfe980000,
360 .end = 0xfe9902d3,
361 .flags = IORESOURCE_MEM,
362 },
363 };
364
365 static struct platform_device jpu_device = {
366 .name = "uio_pdrv_genirq",
367 .id = 5,
368 .dev = {
369 .platform_data = &jpu_platform_data,
370 },
371 .resource = jpu_resources,
372 .num_resources = ARRAY_SIZE(jpu_resources),
373 };
374
375 /* SPU2DSP0 */
376 static struct uio_info spu0_platform_data = {
377 .name = "SPU2DSP0",
378 .version = "0",
379 .irq = evt2irq(0x1800),
380 };
381
382 static struct resource spu0_resources[] = {
383 [0] = {
384 .name = "SPU2DSP0",
385 .start = 0xfe200000,
386 .end = 0xfe2fffff,
387 .flags = IORESOURCE_MEM,
388 },
389 };
390
391 static struct platform_device spu0_device = {
392 .name = "uio_pdrv_genirq",
393 .id = 6,
394 .dev = {
395 .platform_data = &spu0_platform_data,
396 },
397 .resource = spu0_resources,
398 .num_resources = ARRAY_SIZE(spu0_resources),
399 };
400
401 /* SPU2DSP1 */
402 static struct uio_info spu1_platform_data = {
403 .name = "SPU2DSP1",
404 .version = "0",
405 .irq = evt2irq(0x1820),
406 };
407
408 static struct resource spu1_resources[] = {
409 [0] = {
410 .name = "SPU2DSP1",
411 .start = 0xfe300000,
412 .end = 0xfe3fffff,
413 .flags = IORESOURCE_MEM,
414 },
415 };
416
417 static struct platform_device spu1_device = {
418 .name = "uio_pdrv_genirq",
419 .id = 7,
420 .dev = {
421 .platform_data = &spu1_platform_data,
422 },
423 .resource = spu1_resources,
424 .num_resources = ARRAY_SIZE(spu1_resources),
425 };
426
427 static struct platform_device *sh7377_early_devices[] __initdata = {
428 &scif0_device,
429 &scif1_device,
430 &scif2_device,
431 &scif3_device,
432 &scif4_device,
433 &scif5_device,
434 &scif6_device,
435 &scif7_device,
436 &cmt10_device,
437 };
438
439 static struct platform_device *sh7377_devices[] __initdata = {
440 &vpu_device,
441 &veu0_device,
442 &veu1_device,
443 &veu2_device,
444 &veu3_device,
445 &jpu_device,
446 &spu0_device,
447 &spu1_device,
448 };
449
sh7377_add_standard_devices(void)450 void __init sh7377_add_standard_devices(void)
451 {
452 platform_add_devices(sh7377_early_devices,
453 ARRAY_SIZE(sh7377_early_devices));
454
455 platform_add_devices(sh7377_devices,
456 ARRAY_SIZE(sh7377_devices));
457 }
458
459 #define SMSTPCR3 0xe615013c
460 #define SMSTPCR3_CMT1 (1 << 29)
461
sh7377_add_early_devices(void)462 void __init sh7377_add_early_devices(void)
463 {
464 /* enable clock to CMT1 */
465 __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
466
467 early_platform_add_devices(sh7377_early_devices,
468 ARRAY_SIZE(sh7377_early_devices));
469 }
470