1 /*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
28 #include <linux/io.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <mach/hardware.h>
35 #include <mach/sh7372.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 /* SCIFA0 */
40 static struct plat_sci_port scif0_platform_data = {
41 .mapbase = 0xe6c40000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE,
44 .scbrr_algo_id = SCBRR_ALGO_4,
45 .type = PORT_SCIFA,
46 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
47 evt2irq(0x0c00), evt2irq(0x0c00) },
48 };
49
50 static struct platform_device scif0_device = {
51 .name = "sh-sci",
52 .id = 0,
53 .dev = {
54 .platform_data = &scif0_platform_data,
55 },
56 };
57
58 /* SCIFA1 */
59 static struct plat_sci_port scif1_platform_data = {
60 .mapbase = 0xe6c50000,
61 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_RE | SCSCR_TE,
63 .scbrr_algo_id = SCBRR_ALGO_4,
64 .type = PORT_SCIFA,
65 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
66 evt2irq(0x0c20), evt2irq(0x0c20) },
67 };
68
69 static struct platform_device scif1_device = {
70 .name = "sh-sci",
71 .id = 1,
72 .dev = {
73 .platform_data = &scif1_platform_data,
74 },
75 };
76
77 /* SCIFA2 */
78 static struct plat_sci_port scif2_platform_data = {
79 .mapbase = 0xe6c60000,
80 .flags = UPF_BOOT_AUTOCONF,
81 .scscr = SCSCR_RE | SCSCR_TE,
82 .scbrr_algo_id = SCBRR_ALGO_4,
83 .type = PORT_SCIFA,
84 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
85 evt2irq(0x0c40), evt2irq(0x0c40) },
86 };
87
88 static struct platform_device scif2_device = {
89 .name = "sh-sci",
90 .id = 2,
91 .dev = {
92 .platform_data = &scif2_platform_data,
93 },
94 };
95
96 /* SCIFA3 */
97 static struct plat_sci_port scif3_platform_data = {
98 .mapbase = 0xe6c70000,
99 .flags = UPF_BOOT_AUTOCONF,
100 .scscr = SCSCR_RE | SCSCR_TE,
101 .scbrr_algo_id = SCBRR_ALGO_4,
102 .type = PORT_SCIFA,
103 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
104 evt2irq(0x0c60), evt2irq(0x0c60) },
105 };
106
107 static struct platform_device scif3_device = {
108 .name = "sh-sci",
109 .id = 3,
110 .dev = {
111 .platform_data = &scif3_platform_data,
112 },
113 };
114
115 /* SCIFA4 */
116 static struct plat_sci_port scif4_platform_data = {
117 .mapbase = 0xe6c80000,
118 .flags = UPF_BOOT_AUTOCONF,
119 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA,
122 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
123 evt2irq(0x0d20), evt2irq(0x0d20) },
124 };
125
126 static struct platform_device scif4_device = {
127 .name = "sh-sci",
128 .id = 4,
129 .dev = {
130 .platform_data = &scif4_platform_data,
131 },
132 };
133
134 /* SCIFA5 */
135 static struct plat_sci_port scif5_platform_data = {
136 .mapbase = 0xe6cb0000,
137 .flags = UPF_BOOT_AUTOCONF,
138 .scscr = SCSCR_RE | SCSCR_TE,
139 .scbrr_algo_id = SCBRR_ALGO_4,
140 .type = PORT_SCIFA,
141 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
142 evt2irq(0x0d40), evt2irq(0x0d40) },
143 };
144
145 static struct platform_device scif5_device = {
146 .name = "sh-sci",
147 .id = 5,
148 .dev = {
149 .platform_data = &scif5_platform_data,
150 },
151 };
152
153 /* SCIFB */
154 static struct plat_sci_port scif6_platform_data = {
155 .mapbase = 0xe6c30000,
156 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE,
158 .scbrr_algo_id = SCBRR_ALGO_4,
159 .type = PORT_SCIFB,
160 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
161 evt2irq(0x0d60), evt2irq(0x0d60) },
162 };
163
164 static struct platform_device scif6_device = {
165 .name = "sh-sci",
166 .id = 6,
167 .dev = {
168 .platform_data = &scif6_platform_data,
169 },
170 };
171
172 /* CMT */
173 static struct sh_timer_config cmt2_platform_data = {
174 .name = "CMT2",
175 .channel_offset = 0x40,
176 .timer_bit = 5,
177 .clockevent_rating = 125,
178 .clocksource_rating = 125,
179 };
180
181 static struct resource cmt2_resources[] = {
182 [0] = {
183 .name = "CMT2",
184 .start = 0xe6130040,
185 .end = 0xe613004b,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = evt2irq(0x0b80), /* CMT2 */
190 .flags = IORESOURCE_IRQ,
191 },
192 };
193
194 static struct platform_device cmt2_device = {
195 .name = "sh_cmt",
196 .id = 2,
197 .dev = {
198 .platform_data = &cmt2_platform_data,
199 },
200 .resource = cmt2_resources,
201 .num_resources = ARRAY_SIZE(cmt2_resources),
202 };
203
204 /* TMU */
205 static struct sh_timer_config tmu00_platform_data = {
206 .name = "TMU00",
207 .channel_offset = 0x4,
208 .timer_bit = 0,
209 .clockevent_rating = 200,
210 };
211
212 static struct resource tmu00_resources[] = {
213 [0] = {
214 .name = "TMU00",
215 .start = 0xfff60008,
216 .end = 0xfff60013,
217 .flags = IORESOURCE_MEM,
218 },
219 [1] = {
220 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
221 .flags = IORESOURCE_IRQ,
222 },
223 };
224
225 static struct platform_device tmu00_device = {
226 .name = "sh_tmu",
227 .id = 0,
228 .dev = {
229 .platform_data = &tmu00_platform_data,
230 },
231 .resource = tmu00_resources,
232 .num_resources = ARRAY_SIZE(tmu00_resources),
233 };
234
235 static struct sh_timer_config tmu01_platform_data = {
236 .name = "TMU01",
237 .channel_offset = 0x10,
238 .timer_bit = 1,
239 .clocksource_rating = 200,
240 };
241
242 static struct resource tmu01_resources[] = {
243 [0] = {
244 .name = "TMU01",
245 .start = 0xfff60014,
246 .end = 0xfff6001f,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
251 .flags = IORESOURCE_IRQ,
252 },
253 };
254
255 static struct platform_device tmu01_device = {
256 .name = "sh_tmu",
257 .id = 1,
258 .dev = {
259 .platform_data = &tmu01_platform_data,
260 },
261 .resource = tmu01_resources,
262 .num_resources = ARRAY_SIZE(tmu01_resources),
263 };
264
265 /* I2C */
266 static struct resource iic0_resources[] = {
267 [0] = {
268 .name = "IIC0",
269 .start = 0xFFF20000,
270 .end = 0xFFF20425 - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
275 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
276 .flags = IORESOURCE_IRQ,
277 },
278 };
279
280 static struct platform_device iic0_device = {
281 .name = "i2c-sh_mobile",
282 .id = 0, /* "i2c0" clock */
283 .num_resources = ARRAY_SIZE(iic0_resources),
284 .resource = iic0_resources,
285 };
286
287 static struct resource iic1_resources[] = {
288 [0] = {
289 .name = "IIC1",
290 .start = 0xE6C20000,
291 .end = 0xE6C20425 - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = evt2irq(0x780), /* IIC1_ALI1 */
296 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
297 .flags = IORESOURCE_IRQ,
298 },
299 };
300
301 static struct platform_device iic1_device = {
302 .name = "i2c-sh_mobile",
303 .id = 1, /* "i2c1" clock */
304 .num_resources = ARRAY_SIZE(iic1_resources),
305 .resource = iic1_resources,
306 };
307
308 /* DMA */
309 /* Transmit sizes and respective CHCR register values */
310 enum {
311 XMIT_SZ_8BIT = 0,
312 XMIT_SZ_16BIT = 1,
313 XMIT_SZ_32BIT = 2,
314 XMIT_SZ_64BIT = 7,
315 XMIT_SZ_128BIT = 3,
316 XMIT_SZ_256BIT = 4,
317 XMIT_SZ_512BIT = 5,
318 };
319
320 /* log2(size / 8) - used to calculate number of transfers */
321 #define TS_SHIFT { \
322 [XMIT_SZ_8BIT] = 0, \
323 [XMIT_SZ_16BIT] = 1, \
324 [XMIT_SZ_32BIT] = 2, \
325 [XMIT_SZ_64BIT] = 3, \
326 [XMIT_SZ_128BIT] = 4, \
327 [XMIT_SZ_256BIT] = 5, \
328 [XMIT_SZ_512BIT] = 6, \
329 }
330
331 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
332 (((i) & 0xc) << (20 - 2)))
333
334 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
335 {
336 .slave_id = SHDMA_SLAVE_SCIF0_TX,
337 .addr = 0xe6c40020,
338 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
339 .mid_rid = 0x21,
340 }, {
341 .slave_id = SHDMA_SLAVE_SCIF0_RX,
342 .addr = 0xe6c40024,
343 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
344 .mid_rid = 0x22,
345 }, {
346 .slave_id = SHDMA_SLAVE_SCIF1_TX,
347 .addr = 0xe6c50020,
348 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
349 .mid_rid = 0x25,
350 }, {
351 .slave_id = SHDMA_SLAVE_SCIF1_RX,
352 .addr = 0xe6c50024,
353 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
354 .mid_rid = 0x26,
355 }, {
356 .slave_id = SHDMA_SLAVE_SCIF2_TX,
357 .addr = 0xe6c60020,
358 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
359 .mid_rid = 0x29,
360 }, {
361 .slave_id = SHDMA_SLAVE_SCIF2_RX,
362 .addr = 0xe6c60024,
363 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
364 .mid_rid = 0x2a,
365 }, {
366 .slave_id = SHDMA_SLAVE_SCIF3_TX,
367 .addr = 0xe6c70020,
368 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
369 .mid_rid = 0x2d,
370 }, {
371 .slave_id = SHDMA_SLAVE_SCIF3_RX,
372 .addr = 0xe6c70024,
373 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
374 .mid_rid = 0x2e,
375 }, {
376 .slave_id = SHDMA_SLAVE_SCIF4_TX,
377 .addr = 0xe6c80020,
378 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
379 .mid_rid = 0x39,
380 }, {
381 .slave_id = SHDMA_SLAVE_SCIF4_RX,
382 .addr = 0xe6c80024,
383 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
384 .mid_rid = 0x3a,
385 }, {
386 .slave_id = SHDMA_SLAVE_SCIF5_TX,
387 .addr = 0xe6cb0020,
388 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
389 .mid_rid = 0x35,
390 }, {
391 .slave_id = SHDMA_SLAVE_SCIF5_RX,
392 .addr = 0xe6cb0024,
393 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
394 .mid_rid = 0x36,
395 }, {
396 .slave_id = SHDMA_SLAVE_SCIF6_TX,
397 .addr = 0xe6c30040,
398 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
399 .mid_rid = 0x3d,
400 }, {
401 .slave_id = SHDMA_SLAVE_SCIF6_RX,
402 .addr = 0xe6c30060,
403 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
404 .mid_rid = 0x3e,
405 }, {
406 .slave_id = SHDMA_SLAVE_SDHI0_TX,
407 .addr = 0xe6850030,
408 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
409 .mid_rid = 0xc1,
410 }, {
411 .slave_id = SHDMA_SLAVE_SDHI0_RX,
412 .addr = 0xe6850030,
413 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
414 .mid_rid = 0xc2,
415 }, {
416 .slave_id = SHDMA_SLAVE_SDHI1_TX,
417 .addr = 0xe6860030,
418 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
419 .mid_rid = 0xc9,
420 }, {
421 .slave_id = SHDMA_SLAVE_SDHI1_RX,
422 .addr = 0xe6860030,
423 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
424 .mid_rid = 0xca,
425 }, {
426 .slave_id = SHDMA_SLAVE_SDHI2_TX,
427 .addr = 0xe6870030,
428 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
429 .mid_rid = 0xcd,
430 }, {
431 .slave_id = SHDMA_SLAVE_SDHI2_RX,
432 .addr = 0xe6870030,
433 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
434 .mid_rid = 0xce,
435 }, {
436 .slave_id = SHDMA_SLAVE_MMCIF_TX,
437 .addr = 0xe6bd0034,
438 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
439 .mid_rid = 0xd1,
440 }, {
441 .slave_id = SHDMA_SLAVE_MMCIF_RX,
442 .addr = 0xe6bd0034,
443 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
444 .mid_rid = 0xd2,
445 },
446 };
447
448 #define SH7372_CHCLR 0x220
449
450 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
451 {
452 .offset = 0,
453 .dmars = 0,
454 .dmars_bit = 0,
455 .chclr_offset = SH7372_CHCLR + 0,
456 }, {
457 .offset = 0x10,
458 .dmars = 0,
459 .dmars_bit = 8,
460 .chclr_offset = SH7372_CHCLR + 0x10,
461 }, {
462 .offset = 0x20,
463 .dmars = 4,
464 .dmars_bit = 0,
465 .chclr_offset = SH7372_CHCLR + 0x20,
466 }, {
467 .offset = 0x30,
468 .dmars = 4,
469 .dmars_bit = 8,
470 .chclr_offset = SH7372_CHCLR + 0x30,
471 }, {
472 .offset = 0x50,
473 .dmars = 8,
474 .dmars_bit = 0,
475 .chclr_offset = SH7372_CHCLR + 0x50,
476 }, {
477 .offset = 0x60,
478 .dmars = 8,
479 .dmars_bit = 8,
480 .chclr_offset = SH7372_CHCLR + 0x60,
481 }
482 };
483
484 static const unsigned int ts_shift[] = TS_SHIFT;
485
486 static struct sh_dmae_pdata dma_platform_data = {
487 .slave = sh7372_dmae_slaves,
488 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
489 .channel = sh7372_dmae_channels,
490 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
491 .ts_low_shift = 3,
492 .ts_low_mask = 0x18,
493 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
494 .ts_high_mask = 0x00300000,
495 .ts_shift = ts_shift,
496 .ts_shift_num = ARRAY_SIZE(ts_shift),
497 .dmaor_init = DMAOR_DME,
498 .chclr_present = 1,
499 };
500
501 /* Resource order important! */
502 static struct resource sh7372_dmae0_resources[] = {
503 {
504 /* Channel registers and DMAOR */
505 .start = 0xfe008020,
506 .end = 0xfe00828f,
507 .flags = IORESOURCE_MEM,
508 },
509 {
510 /* DMARSx */
511 .start = 0xfe009000,
512 .end = 0xfe00900b,
513 .flags = IORESOURCE_MEM,
514 },
515 {
516 .name = "error_irq",
517 .start = evt2irq(0x20c0),
518 .end = evt2irq(0x20c0),
519 .flags = IORESOURCE_IRQ,
520 },
521 {
522 /* IRQ for channels 0-5 */
523 .start = evt2irq(0x2000),
524 .end = evt2irq(0x20a0),
525 .flags = IORESOURCE_IRQ,
526 },
527 };
528
529 /* Resource order important! */
530 static struct resource sh7372_dmae1_resources[] = {
531 {
532 /* Channel registers and DMAOR */
533 .start = 0xfe018020,
534 .end = 0xfe01828f,
535 .flags = IORESOURCE_MEM,
536 },
537 {
538 /* DMARSx */
539 .start = 0xfe019000,
540 .end = 0xfe01900b,
541 .flags = IORESOURCE_MEM,
542 },
543 {
544 .name = "error_irq",
545 .start = evt2irq(0x21c0),
546 .end = evt2irq(0x21c0),
547 .flags = IORESOURCE_IRQ,
548 },
549 {
550 /* IRQ for channels 0-5 */
551 .start = evt2irq(0x2100),
552 .end = evt2irq(0x21a0),
553 .flags = IORESOURCE_IRQ,
554 },
555 };
556
557 /* Resource order important! */
558 static struct resource sh7372_dmae2_resources[] = {
559 {
560 /* Channel registers and DMAOR */
561 .start = 0xfe028020,
562 .end = 0xfe02828f,
563 .flags = IORESOURCE_MEM,
564 },
565 {
566 /* DMARSx */
567 .start = 0xfe029000,
568 .end = 0xfe02900b,
569 .flags = IORESOURCE_MEM,
570 },
571 {
572 .name = "error_irq",
573 .start = evt2irq(0x22c0),
574 .end = evt2irq(0x22c0),
575 .flags = IORESOURCE_IRQ,
576 },
577 {
578 /* IRQ for channels 0-5 */
579 .start = evt2irq(0x2200),
580 .end = evt2irq(0x22a0),
581 .flags = IORESOURCE_IRQ,
582 },
583 };
584
585 static struct platform_device dma0_device = {
586 .name = "sh-dma-engine",
587 .id = 0,
588 .resource = sh7372_dmae0_resources,
589 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
590 .dev = {
591 .platform_data = &dma_platform_data,
592 },
593 };
594
595 static struct platform_device dma1_device = {
596 .name = "sh-dma-engine",
597 .id = 1,
598 .resource = sh7372_dmae1_resources,
599 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
600 .dev = {
601 .platform_data = &dma_platform_data,
602 },
603 };
604
605 static struct platform_device dma2_device = {
606 .name = "sh-dma-engine",
607 .id = 2,
608 .resource = sh7372_dmae2_resources,
609 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
610 .dev = {
611 .platform_data = &dma_platform_data,
612 },
613 };
614
615 /*
616 * USB-DMAC
617 */
618
619 unsigned int usbts_shift[] = {3, 4, 5};
620
621 enum {
622 XMIT_SZ_8BYTE = 0,
623 XMIT_SZ_16BYTE = 1,
624 XMIT_SZ_32BYTE = 2,
625 };
626
627 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
628
629 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
630 {
631 .offset = 0,
632 }, {
633 .offset = 0x20,
634 },
635 };
636
637 /* USB DMAC0 */
638 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
639 {
640 .slave_id = SHDMA_SLAVE_USB0_TX,
641 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
642 }, {
643 .slave_id = SHDMA_SLAVE_USB0_RX,
644 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
645 },
646 };
647
648 static struct sh_dmae_pdata usb_dma0_platform_data = {
649 .slave = sh7372_usb_dmae0_slaves,
650 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
651 .channel = sh7372_usb_dmae_channels,
652 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
653 .ts_low_shift = 6,
654 .ts_low_mask = 0xc0,
655 .ts_high_shift = 0,
656 .ts_high_mask = 0,
657 .ts_shift = usbts_shift,
658 .ts_shift_num = ARRAY_SIZE(usbts_shift),
659 .dmaor_init = DMAOR_DME,
660 .chcr_offset = 0x14,
661 .chcr_ie_bit = 1 << 5,
662 .dmaor_is_32bit = 1,
663 .needs_tend_set = 1,
664 .no_dmars = 1,
665 .slave_only = 1,
666 };
667
668 static struct resource sh7372_usb_dmae0_resources[] = {
669 {
670 /* Channel registers and DMAOR */
671 .start = 0xe68a0020,
672 .end = 0xe68a0064 - 1,
673 .flags = IORESOURCE_MEM,
674 },
675 {
676 /* VCR/SWR/DMICR */
677 .start = 0xe68a0000,
678 .end = 0xe68a0014 - 1,
679 .flags = IORESOURCE_MEM,
680 },
681 {
682 /* IRQ for channels */
683 .start = evt2irq(0x0a00),
684 .end = evt2irq(0x0a00),
685 .flags = IORESOURCE_IRQ,
686 },
687 };
688
689 static struct platform_device usb_dma0_device = {
690 .name = "sh-dma-engine",
691 .id = 3,
692 .resource = sh7372_usb_dmae0_resources,
693 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
694 .dev = {
695 .platform_data = &usb_dma0_platform_data,
696 },
697 };
698
699 /* USB DMAC1 */
700 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
701 {
702 .slave_id = SHDMA_SLAVE_USB1_TX,
703 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
704 }, {
705 .slave_id = SHDMA_SLAVE_USB1_RX,
706 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
707 },
708 };
709
710 static struct sh_dmae_pdata usb_dma1_platform_data = {
711 .slave = sh7372_usb_dmae1_slaves,
712 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
713 .channel = sh7372_usb_dmae_channels,
714 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
715 .ts_low_shift = 6,
716 .ts_low_mask = 0xc0,
717 .ts_high_shift = 0,
718 .ts_high_mask = 0,
719 .ts_shift = usbts_shift,
720 .ts_shift_num = ARRAY_SIZE(usbts_shift),
721 .dmaor_init = DMAOR_DME,
722 .chcr_offset = 0x14,
723 .chcr_ie_bit = 1 << 5,
724 .dmaor_is_32bit = 1,
725 .needs_tend_set = 1,
726 .no_dmars = 1,
727 .slave_only = 1,
728 };
729
730 static struct resource sh7372_usb_dmae1_resources[] = {
731 {
732 /* Channel registers and DMAOR */
733 .start = 0xe68c0020,
734 .end = 0xe68c0064 - 1,
735 .flags = IORESOURCE_MEM,
736 },
737 {
738 /* VCR/SWR/DMICR */
739 .start = 0xe68c0000,
740 .end = 0xe68c0014 - 1,
741 .flags = IORESOURCE_MEM,
742 },
743 {
744 /* IRQ for channels */
745 .start = evt2irq(0x1d00),
746 .end = evt2irq(0x1d00),
747 .flags = IORESOURCE_IRQ,
748 },
749 };
750
751 static struct platform_device usb_dma1_device = {
752 .name = "sh-dma-engine",
753 .id = 4,
754 .resource = sh7372_usb_dmae1_resources,
755 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
756 .dev = {
757 .platform_data = &usb_dma1_platform_data,
758 },
759 };
760
761 /* VPU */
762 static struct uio_info vpu_platform_data = {
763 .name = "VPU5HG",
764 .version = "0",
765 .irq = intcs_evt2irq(0x980),
766 };
767
768 static struct resource vpu_resources[] = {
769 [0] = {
770 .name = "VPU",
771 .start = 0xfe900000,
772 .end = 0xfe900157,
773 .flags = IORESOURCE_MEM,
774 },
775 };
776
777 static struct platform_device vpu_device = {
778 .name = "uio_pdrv_genirq",
779 .id = 0,
780 .dev = {
781 .platform_data = &vpu_platform_data,
782 },
783 .resource = vpu_resources,
784 .num_resources = ARRAY_SIZE(vpu_resources),
785 };
786
787 /* VEU0 */
788 static struct uio_info veu0_platform_data = {
789 .name = "VEU0",
790 .version = "0",
791 .irq = intcs_evt2irq(0x700),
792 };
793
794 static struct resource veu0_resources[] = {
795 [0] = {
796 .name = "VEU0",
797 .start = 0xfe920000,
798 .end = 0xfe9200cb,
799 .flags = IORESOURCE_MEM,
800 },
801 };
802
803 static struct platform_device veu0_device = {
804 .name = "uio_pdrv_genirq",
805 .id = 1,
806 .dev = {
807 .platform_data = &veu0_platform_data,
808 },
809 .resource = veu0_resources,
810 .num_resources = ARRAY_SIZE(veu0_resources),
811 };
812
813 /* VEU1 */
814 static struct uio_info veu1_platform_data = {
815 .name = "VEU1",
816 .version = "0",
817 .irq = intcs_evt2irq(0x720),
818 };
819
820 static struct resource veu1_resources[] = {
821 [0] = {
822 .name = "VEU1",
823 .start = 0xfe924000,
824 .end = 0xfe9240cb,
825 .flags = IORESOURCE_MEM,
826 },
827 };
828
829 static struct platform_device veu1_device = {
830 .name = "uio_pdrv_genirq",
831 .id = 2,
832 .dev = {
833 .platform_data = &veu1_platform_data,
834 },
835 .resource = veu1_resources,
836 .num_resources = ARRAY_SIZE(veu1_resources),
837 };
838
839 /* VEU2 */
840 static struct uio_info veu2_platform_data = {
841 .name = "VEU2",
842 .version = "0",
843 .irq = intcs_evt2irq(0x740),
844 };
845
846 static struct resource veu2_resources[] = {
847 [0] = {
848 .name = "VEU2",
849 .start = 0xfe928000,
850 .end = 0xfe928307,
851 .flags = IORESOURCE_MEM,
852 },
853 };
854
855 static struct platform_device veu2_device = {
856 .name = "uio_pdrv_genirq",
857 .id = 3,
858 .dev = {
859 .platform_data = &veu2_platform_data,
860 },
861 .resource = veu2_resources,
862 .num_resources = ARRAY_SIZE(veu2_resources),
863 };
864
865 /* VEU3 */
866 static struct uio_info veu3_platform_data = {
867 .name = "VEU3",
868 .version = "0",
869 .irq = intcs_evt2irq(0x760),
870 };
871
872 static struct resource veu3_resources[] = {
873 [0] = {
874 .name = "VEU3",
875 .start = 0xfe92c000,
876 .end = 0xfe92c307,
877 .flags = IORESOURCE_MEM,
878 },
879 };
880
881 static struct platform_device veu3_device = {
882 .name = "uio_pdrv_genirq",
883 .id = 4,
884 .dev = {
885 .platform_data = &veu3_platform_data,
886 },
887 .resource = veu3_resources,
888 .num_resources = ARRAY_SIZE(veu3_resources),
889 };
890
891 /* JPU */
892 static struct uio_info jpu_platform_data = {
893 .name = "JPU",
894 .version = "0",
895 .irq = intcs_evt2irq(0x560),
896 };
897
898 static struct resource jpu_resources[] = {
899 [0] = {
900 .name = "JPU",
901 .start = 0xfe980000,
902 .end = 0xfe9902d3,
903 .flags = IORESOURCE_MEM,
904 },
905 };
906
907 static struct platform_device jpu_device = {
908 .name = "uio_pdrv_genirq",
909 .id = 5,
910 .dev = {
911 .platform_data = &jpu_platform_data,
912 },
913 .resource = jpu_resources,
914 .num_resources = ARRAY_SIZE(jpu_resources),
915 };
916
917 /* SPU2DSP0 */
918 static struct uio_info spu0_platform_data = {
919 .name = "SPU2DSP0",
920 .version = "0",
921 .irq = evt2irq(0x1800),
922 };
923
924 static struct resource spu0_resources[] = {
925 [0] = {
926 .name = "SPU2DSP0",
927 .start = 0xfe200000,
928 .end = 0xfe2fffff,
929 .flags = IORESOURCE_MEM,
930 },
931 };
932
933 static struct platform_device spu0_device = {
934 .name = "uio_pdrv_genirq",
935 .id = 6,
936 .dev = {
937 .platform_data = &spu0_platform_data,
938 },
939 .resource = spu0_resources,
940 .num_resources = ARRAY_SIZE(spu0_resources),
941 };
942
943 /* SPU2DSP1 */
944 static struct uio_info spu1_platform_data = {
945 .name = "SPU2DSP1",
946 .version = "0",
947 .irq = evt2irq(0x1820),
948 };
949
950 static struct resource spu1_resources[] = {
951 [0] = {
952 .name = "SPU2DSP1",
953 .start = 0xfe300000,
954 .end = 0xfe3fffff,
955 .flags = IORESOURCE_MEM,
956 },
957 };
958
959 static struct platform_device spu1_device = {
960 .name = "uio_pdrv_genirq",
961 .id = 7,
962 .dev = {
963 .platform_data = &spu1_platform_data,
964 },
965 .resource = spu1_resources,
966 .num_resources = ARRAY_SIZE(spu1_resources),
967 };
968
969 static struct platform_device *sh7372_early_devices[] __initdata = {
970 &scif0_device,
971 &scif1_device,
972 &scif2_device,
973 &scif3_device,
974 &scif4_device,
975 &scif5_device,
976 &scif6_device,
977 &cmt2_device,
978 &tmu00_device,
979 &tmu01_device,
980 };
981
982 static struct platform_device *sh7372_late_devices[] __initdata = {
983 &iic0_device,
984 &iic1_device,
985 &dma0_device,
986 &dma1_device,
987 &dma2_device,
988 &usb_dma0_device,
989 &usb_dma1_device,
990 &vpu_device,
991 &veu0_device,
992 &veu1_device,
993 &veu2_device,
994 &veu3_device,
995 &jpu_device,
996 &spu0_device,
997 &spu1_device,
998 };
999
sh7372_add_standard_devices(void)1000 void __init sh7372_add_standard_devices(void)
1001 {
1002 sh7372_init_pm_domain(&sh7372_a4lc);
1003 sh7372_init_pm_domain(&sh7372_a4mp);
1004 sh7372_init_pm_domain(&sh7372_d4);
1005 sh7372_init_pm_domain(&sh7372_a4r);
1006 sh7372_init_pm_domain(&sh7372_a3rv);
1007 sh7372_init_pm_domain(&sh7372_a3ri);
1008 sh7372_init_pm_domain(&sh7372_a4s);
1009 sh7372_init_pm_domain(&sh7372_a3sp);
1010 sh7372_init_pm_domain(&sh7372_a3sg);
1011
1012 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1013 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1014
1015 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1016 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1017
1018 platform_add_devices(sh7372_early_devices,
1019 ARRAY_SIZE(sh7372_early_devices));
1020
1021 platform_add_devices(sh7372_late_devices,
1022 ARRAY_SIZE(sh7372_late_devices));
1023
1024 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1025 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1026 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1027 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1028 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1029 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1030 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1031 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1032 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1033 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1034 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1035 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1036 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1037 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1038 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1039 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1040 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1041 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1042 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1043 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1044 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1045 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1046 }
1047
sh7372_add_early_devices(void)1048 void __init sh7372_add_early_devices(void)
1049 {
1050 early_platform_add_devices(sh7372_early_devices,
1051 ARRAY_SIZE(sh7372_early_devices));
1052 }
1053