1 /*
2 * sh7372 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/sh_intc.h>
25 #include <mach/intc.h>
26 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28
29 enum {
30 UNUSED_INTCA = 0,
31
32 /* interrupt sources INTCA */
33 DIRC,
34 CRYPT_STD,
35 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
36 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
37 MFI_MFIM, MFI_MFIS,
38 BBIF1, BBIF2,
39 USBHSDMAC0_USHDMI,
40 _3DG_SGX540,
41 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
42 KEYSC_KEY,
43 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
44 MSIOF2, MSIOF1,
45 SCIFA4, SCIFA5, SCIFB,
46 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
47 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
48 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
49 IRREM,
50 IRDA,
51 TPU0,
52 TTI20,
53 DDM,
54 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
55 RWDT0,
56 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
57 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
58 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
59 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
60 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
61 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
62 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
63 HDMI,
64 SPU2_SPU0, SPU2_SPU1,
65 FSI, FMSI,
66 MIPI_HSI,
67 IPMMU_IPMMUD,
68 CEC_1, CEC_2,
69 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
70 MFIS2,
71 CPORTR2S,
72 CMT14, CMT15,
73 MMC_MMC_ERR, MMC_MMC_NOR,
74 IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
75 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
76 USB0_USB0I1, USB0_USB0I0,
77 USB1_USB1I1, USB1_USB1I0,
78 USBHSDMAC1_USHDMI,
79
80 /* interrupt groups INTCA */
81 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
82 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
83 };
84
85 static struct intc_vect intca_vectors[] __initdata = {
86 INTC_VECT(DIRC, 0x0560),
87 INTC_VECT(CRYPT_STD, 0x0700),
88 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
89 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
90 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
91 INTC_VECT(AP_ARM_COMMRX, 0x0860),
92 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
93 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
94 INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
95 INTC_VECT(_3DG_SGX540, 0x0a60),
96 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
97 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
98 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
99 INTC_VECT(KEYSC_KEY, 0x0be0),
100 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
101 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
102 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
103 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
104 INTC_VECT(SCIFB, 0x0d60),
105 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
106 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
107 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
108 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
109 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
110 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
111 INTC_VECT(IRREM, 0x0f60),
112 INTC_VECT(IRDA, 0x0480),
113 INTC_VECT(TPU0, 0x04a0),
114 INTC_VECT(TTI20, 0x1100),
115 INTC_VECT(DDM, 0x1140),
116 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
117 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
118 INTC_VECT(RWDT0, 0x1280),
119 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
120 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
121 INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
122 INTC_VECT(DMAC1_2_DADERR, 0x20c0),
123 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
124 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
125 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
126 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
127 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
128 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
129 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
130 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
131 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
132 INTC_VECT(SHWYSTAT_COM, 0x1340),
133 INTC_VECT(HDMI, 0x17e0),
134 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
135 INTC_VECT(FSI, 0x1840),
136 INTC_VECT(FMSI, 0x1860),
137 INTC_VECT(MIPI_HSI, 0x18e0),
138 INTC_VECT(IPMMU_IPMMUD, 0x1920),
139 INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
140 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
141 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
142 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
143 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
144 INTC_VECT(MFIS2, 0x1a00),
145 INTC_VECT(CPORTR2S, 0x1a20),
146 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
147 INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
148 INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
149 INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
150 INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
151 INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
152 INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
153 INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
154 INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
155 };
156
157 static struct intc_group intca_groups[] __initdata = {
158 INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
159 DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
160 INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
161 DMAC1_2_DEI5, DMAC1_2_DADERR),
162 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
163 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
164 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
165 DMAC2_2_DEI5, DMAC2_2_DADERR),
166 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
167 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
168 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
169 DMAC3_2_DEI5, DMAC3_2_DADERR),
170 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
171 INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
172 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
173 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
174 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
175 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
176 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
177 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
178 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
179 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
180 SDHI1_SDHI1I2),
181 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
182 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
183 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
184 };
185
186 static struct intc_mask_reg intca_mask_registers[] __initdata = {
187 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
188 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
189 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
190 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
191 { 0, CRYPT_STD, DIRC, 0,
192 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
193 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
194 { 0, 0, 0, 0,
195 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
196 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
197 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
198 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
199 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
200 { DDM, 0, 0, 0,
201 0, 0, 0, 0 } },
202 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
203 { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
204 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
205 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
206 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
207 0, 0, MSIOF2, 0 } },
208 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
209 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
210 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
211 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
212 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
213 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
214 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
215 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
216 CMT2, 0, 0, _3DG_SGX540 } },
217 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
218 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
219 0, 0, 0, 0 } },
220 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
221 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
222 0, 0, IRREM, 0 } },
223 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
224 { 0, 0, TPU0, 0,
225 0, 0, 0, 0 } },
226 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
227 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
228 0, CMT3, 0, RWDT0 } },
229 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
230 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
231 0, 0, 0, 0 } },
232 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
233 { 0, 0, 0, 0,
234 0, 0, 0, HDMI } },
235 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
236 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
237 0, 0, 0, MIPI_HSI } },
238 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
239 { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
240 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
241 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
242 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
243 { MFIS2, CPORTR2S, CMT14, CMT15,
244 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
245 { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
246 { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
247 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
248 { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
249 { 0, 0, 0, 0,
250 USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
251 { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
252 { USBHSDMAC1_USHDMI, 0, 0, 0,
253 0, 0, 0, 0 } },
254 };
255
256 static struct intc_prio_reg intca_prio_registers[] __initdata = {
257 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
258 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
259 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
260 CMT1_CMT11, AP_ARM1 } },
261 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
262 CMT1_CMT12, 0 } },
263 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
264 MFI_MFIM, 0 } },
265 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
266 _3DG_SGX540, CMT1_CMT10 } },
267 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
268 SCIFA2, SCIFA3 } },
269 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
270 FLCTL, SDHI0 } },
271 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
272 0/* MSU */, IIC1 } },
273 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
274 0/* MSUG */, TTI20 } },
275 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
276 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
277 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
278 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
279 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
280 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
281 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
282 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
283 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
284 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
285 CEC_1, CEC_2 } },
286 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
287 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
288 CMT14, CMT15 } },
289 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
290 MMC_MMC_ERR, MMC_MMC_NOR } },
291 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
292 IIC4_WAITI4, IIC4_DTEI4 } },
293 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
294 IIC3_WAITI3, IIC3_DTEI3 } },
295 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
296 0/*TXI*/, 0/*TEI*/} },
297 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
298 USB1_USB1I1, USB1_USB1I0 } },
299 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
300 };
301
302 static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
303 intca_vectors, intca_groups,
304 intca_mask_registers, intca_prio_registers,
305 NULL);
306
307 INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
308 INTC_VECT, "sh7372-intca-irq-pins");
309 enum {
310 UNUSED_INTCS = 0,
311 ENABLED_INTCS,
312
313 INTCS,
314
315 /* interrupt sources INTCS */
316
317 /* IRQ0S - IRQ31S */
318 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
319 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
320 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
321 /* MFI */
322 /* BBIF2 */
323 VPU,
324 TSIF1,
325 /* 3DG */
326 _2DDMAC,
327 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
328 IPMMU_IPMMUR, IPMMU_IPMMUR2,
329 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
330 /* KEYSC */
331 /* TTI20 */
332 MSIOF,
333 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
334 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
335 CMT0,
336 TSIF0,
337 /* CMT2 */
338 LMB,
339 CTI,
340 /* RWDT0 */
341 ICB,
342 JPU_JPEG,
343 LCDC,
344 LCRC,
345 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
346 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
347 ISP,
348 LCDC1,
349 CSIRX,
350 DSITX_DSITX0,
351 DSITX_DSITX1,
352 /* SPU2 */
353 /* FSI */
354 /* FMSI */
355 /* HDMI */
356 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
357 CMT4,
358 DSITX1_DSITX1_0,
359 DSITX1_DSITX1_1,
360 MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
361 CPORTS2R,
362 /* CEC */
363 JPU6E,
364
365 /* interrupt groups INTCS */
366 RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
367 RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
368 };
369
370 static struct intc_vect intcs_vectors[] = {
371 /* IRQ0S - IRQ31S */
372 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
373 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
374 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
375 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
376 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
377 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
378 /* MFI */
379 /* BBIF2 */
380 INTCS_VECT(VPU, 0x980),
381 INTCS_VECT(TSIF1, 0x9a0),
382 /* 3DG */
383 INTCS_VECT(_2DDMAC, 0xa00),
384 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
385 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
386 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
387 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
388 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
389 /* KEYSC */
390 /* TTI20 */
391 INTCS_VECT(MSIOF, 0x0d20),
392 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
393 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
394 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
395 INTCS_VECT(TMU_TUNI2, 0xec0),
396 INTCS_VECT(CMT0, 0xf00),
397 INTCS_VECT(TSIF0, 0xf20),
398 /* CMT2 */
399 INTCS_VECT(LMB, 0xf60),
400 INTCS_VECT(CTI, 0x400),
401 /* RWDT0 */
402 INTCS_VECT(ICB, 0x480),
403 INTCS_VECT(JPU_JPEG, 0x560),
404 INTCS_VECT(LCDC, 0x580),
405 INTCS_VECT(LCRC, 0x5a0),
406 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
407 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
408 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
409 INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
410 INTCS_VECT(ISP, 0x1720),
411 INTCS_VECT(LCDC1, 0x1780),
412 INTCS_VECT(CSIRX, 0x17a0),
413 INTCS_VECT(DSITX_DSITX0, 0x17c0),
414 INTCS_VECT(DSITX_DSITX1, 0x17e0),
415 /* SPU2 */
416 /* FSI */
417 /* FMSI */
418 /* HDMI */
419 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
420 INTCS_VECT(TMU1_TUNI2, 0x1940),
421 INTCS_VECT(CMT4, 0x1980),
422 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
423 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
424 INTCS_VECT(MFIS2_INTCS, 0x1a00),
425 INTCS_VECT(CPORTS2R, 0x1a20),
426 /* CEC */
427 INTCS_VECT(JPU6E, 0x1a80),
428
429 INTC_VECT(INTCS, 0xf80),
430 };
431
432 static struct intc_group intcs_groups[] __initdata = {
433 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
434 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
435 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
436 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
437 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
438 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
439 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
440 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
441 INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
442 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
443 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
444 RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
445 INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
446 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
447 };
448
449 static struct intc_mask_reg intcs_mask_registers[] = {
450 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
451 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
452 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
453 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
454 { 0, 0, 0, VPU,
455 0, 0, 0, 0 } },
456 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
457 { 0, 0, 0, _2DDMAC,
458 0, 0, 0, ICB } },
459 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
460 { 0, 0, 0, CTI,
461 JPU_JPEG, 0, LCRC, LCDC } },
462 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
463 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
464 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
465 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
466 { 0, 0, MSIOF, 0,
467 0, 0, 0, 0 } },
468 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
469 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
470 0, 0, 0, 0 } },
471 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
472 { 0, 0, 0, CMT0,
473 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
474 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
475 { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
476 0, 0, 0, 0 } },
477 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
478 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
479 0, TSIF1, LMB, TSIF0 } },
480 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
481 { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
482 RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
483 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
484 { 0, ISP, 0, 0,
485 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
486 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
487 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
488 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
489 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
490 { MFIS2_INTCS, CPORTS2R, 0, 0,
491 JPU6E, 0, 0, 0 } },
492 { 0xffd20104, 0, 16, /* INTAMASK */
493 { 0, 0, 0, 0, 0, 0, 0, 0,
494 0, 0, 0, 0, 0, 0, 0, INTCS } },
495 };
496
497 /* Priority is needed for INTCA to receive the INTCS interrupt */
498 static struct intc_prio_reg intcs_prio_registers[] = {
499 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
500 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
501 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
502 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
503 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
504 TMU_TUNI2, TSIF1 } },
505 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
506 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
507 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
508 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
509 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
510 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
511 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
512 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
513 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
514 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
515 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
516 DSITX1_DSITX1_1, 0 } },
517 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
518 0, 0 } },
519 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
520 };
521
522 static struct resource intcs_resources[] __initdata = {
523 [0] = {
524 .start = 0xffd20000,
525 .end = 0xffd201ff,
526 .flags = IORESOURCE_MEM,
527 },
528 [1] = {
529 .start = 0xffd50000,
530 .end = 0xffd501ff,
531 .flags = IORESOURCE_MEM,
532 }
533 };
534
535 static struct intc_desc intcs_desc __initdata = {
536 .name = "sh7372-intcs",
537 .force_enable = ENABLED_INTCS,
538 .skip_syscore_suspend = true,
539 .resource = intcs_resources,
540 .num_resources = ARRAY_SIZE(intcs_resources),
541 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
542 intcs_prio_registers, NULL, NULL),
543 };
544
intcs_demux(unsigned int irq,struct irq_desc * desc)545 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
546 {
547 void __iomem *reg = (void *)irq_get_handler_data(irq);
548 unsigned int evtcodeas = ioread32(reg);
549
550 generic_handle_irq(intcs_evt2irq(evtcodeas));
551 }
552
553 static void __iomem *intcs_ffd2;
554 static void __iomem *intcs_ffd5;
555
sh7372_init_irq(void)556 void __init sh7372_init_irq(void)
557 {
558 void __iomem *intevtsa;
559
560 intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
561 intevtsa = intcs_ffd2 + 0x100;
562 intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
563
564 register_intc_controller(&intca_desc);
565 register_intc_controller(&intca_irq_pins_desc);
566 register_intc_controller(&intcs_desc);
567
568 /* demux using INTEVTSA */
569 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
570 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
571 }
572
573 static unsigned short ffd2[0x200];
574 static unsigned short ffd5[0x100];
575
sh7372_intcs_suspend(void)576 void sh7372_intcs_suspend(void)
577 {
578 int k;
579
580 for (k = 0x00; k <= 0x30; k += 4)
581 ffd2[k] = __raw_readw(intcs_ffd2 + k);
582
583 for (k = 0x80; k <= 0xb0; k += 4)
584 ffd2[k] = __raw_readb(intcs_ffd2 + k);
585
586 for (k = 0x180; k <= 0x188; k += 4)
587 ffd2[k] = __raw_readb(intcs_ffd2 + k);
588
589 for (k = 0x00; k <= 0x3c; k += 4)
590 ffd5[k] = __raw_readw(intcs_ffd5 + k);
591
592 for (k = 0x80; k <= 0x9c; k += 4)
593 ffd5[k] = __raw_readb(intcs_ffd5 + k);
594 }
595
sh7372_intcs_resume(void)596 void sh7372_intcs_resume(void)
597 {
598 int k;
599
600 for (k = 0x00; k <= 0x30; k += 4)
601 __raw_writew(ffd2[k], intcs_ffd2 + k);
602
603 for (k = 0x80; k <= 0xb0; k += 4)
604 __raw_writeb(ffd2[k], intcs_ffd2 + k);
605
606 for (k = 0x180; k <= 0x188; k += 4)
607 __raw_writeb(ffd2[k], intcs_ffd2 + k);
608
609 for (k = 0x00; k <= 0x3c; k += 4)
610 __raw_writew(ffd5[k], intcs_ffd5 + k);
611
612 for (k = 0x80; k <= 0x9c; k += 4)
613 __raw_writeb(ffd5[k], intcs_ffd5 + k);
614 }
615
616 static unsigned short e694[0x200];
617 static unsigned short e695[0x200];
618
sh7372_intca_suspend(void)619 void sh7372_intca_suspend(void)
620 {
621 int k;
622
623 for (k = 0x00; k <= 0x38; k += 4)
624 e694[k] = __raw_readw(0xe6940000 + k);
625
626 for (k = 0x80; k <= 0xb4; k += 4)
627 e694[k] = __raw_readb(0xe6940000 + k);
628
629 for (k = 0x180; k <= 0x1b4; k += 4)
630 e694[k] = __raw_readb(0xe6940000 + k);
631
632 for (k = 0x00; k <= 0x50; k += 4)
633 e695[k] = __raw_readw(0xe6950000 + k);
634
635 for (k = 0x80; k <= 0xa8; k += 4)
636 e695[k] = __raw_readb(0xe6950000 + k);
637
638 for (k = 0x180; k <= 0x1a8; k += 4)
639 e695[k] = __raw_readb(0xe6950000 + k);
640 }
641
sh7372_intca_resume(void)642 void sh7372_intca_resume(void)
643 {
644 int k;
645
646 for (k = 0x00; k <= 0x38; k += 4)
647 __raw_writew(e694[k], 0xe6940000 + k);
648
649 for (k = 0x80; k <= 0xb4; k += 4)
650 __raw_writeb(e694[k], 0xe6940000 + k);
651
652 for (k = 0x180; k <= 0x1b4; k += 4)
653 __raw_writeb(e694[k], 0xe6940000 + k);
654
655 for (k = 0x00; k <= 0x50; k += 4)
656 __raw_writew(e695[k], 0xe6950000 + k);
657
658 for (k = 0x80; k <= 0xa8; k += 4)
659 __raw_writeb(e695[k], 0xe6950000 + k);
660
661 for (k = 0x180; k <= 0x1a8; k += 4)
662 __raw_writeb(e695[k], 0xe6950000 + k);
663 }
664